DE69524579T2 - High speed differential current sense amplifier with positive feedback - Google Patents

Description

Technical area

This invention is directed to sense amplifiers for semiconductor memories, and more particularly to an improved differential current sense amplifier of the type according to the preamble of claim 1 and a method as defined in the preamble of claim 9.

Background of the invention

Semiconductor memories are used to store information, often in conjunction with microprocessors. Typical memory devices include an array of memory cells along with various "peripheral" circuitry. Each memory cell can usually only store one value, typically in binary format, namely a "1" or a "0." The memory cells are arranged in rows and columns. Each row of memory cells corresponds to and is accessible by a word line, and each column of memory cells corresponds to and is accessible by bit lines, often a pair of bit lines. At or near each intersection of each row and bit line in the array is a memory cell. To write to or read from a specific memory cell, the memory device must be told which cell to access. This is accomplished by reading an address and decoding it into a row address and a column address. The row address is used to locate and activate the word line along which the specific memory cell lies. By activating the word line, all memory cells connected to the row are coupled to their respective bit lines. The column address then allows only the bit line (pair) for the selected memory cell to be coupled to the data line pair, with the corresponding data being transferred between the two. In the case of a memory read, the data is transferred from the memory cells to the data lines. In the case of a memory write, the data is transferred from the data lines to the memory cell. In this way, a specific memory cell is coupled to the data lines during a memory access.

During a memory read, the signal read from a memory cell creates a voltage differential. The voltage differential is small, typically in the range of 100-200 mV. Because the differential is small, it must be amplified before it can be used by the logic circuits in subsequent stages. The amplification is achieved, often in multiple stages, by means of sense amplifiers. When the amplifier inputs are connected to the data lines, the amplifier is called a If the amplifier inputs are connected to bit lines, the amplifier is a sense amplifier, often referred to as a presence amplifier.

Conventional sense amplifiers read and amplify the voltage differential between the two input lines. However, because bit lines and data lines are capacitively charged, there is a delay in transmitting a terminal voltage differential to the sense amplifiers. This results in an overall increase in the time required to read data from a memory cell.

While the voltage responds slowly, the current changes almost instantaneously. For this reason, differential current sense amplifiers have been developed that read current differentials between two input lines, as opposed to voltage differentials. In this way, circuits can respond much more quickly to changes in bit lines or data lines. A good description of differential current sense amplifiers can be found in US-A-4 766 333, owned by Inmos Corporation, entitled "Current Sensing Differential Amplifiers", which discloses the features of the preamble to the claims. From this prior art document, a sense amplifier and method of the type defined above are known. The sense amplifier according to this document provides two circuit paths between VCC and ground, each including the source-drain path of a corresponding primary transistor. Two impedance transistors are coupled to respective inputs. The primary transistors are kept in saturation so that the voltage differential between the inputs is minimized, but a large voltage differential is formed at outputs arranged in the two circuit paths. Secondary transistors are included to mimic voltage changes at each input.

US-A-4 823 031 discloses a single-ended sense amplifier constructed using five FET transistors in a configuration that uses positive feedback to increase the rate of voltage change at the amplifier output.

GB-A-2 250 842 discloses a cross-coupled differential sense amplifier with two output terminals having both high operating speed and high voltage gain, wherein at least one of the output terminals is adapted to be charged and discharged in response to a signal fed back from the other output terminal. In this document, the inputs of the Sense amplifier only connected to gate electrodes of FET, never to drain or source.

Figure 1 shows a prior art differential current sense amplifier and is an improvement over initial differential current sense amplifiers. Figure 1 shows an amplifier circuit 10 which includes a reference voltage circuit 11, a first input terminal 12, a second input terminal 14, a first negative feedback transistor 30 and a second negative feedback transistor 32, with the remainder of the circuit generally functioning as a voltage amplifier.

Input terminal 12 is coupled to the sources of P-channel transistors 22 and 24. Input 14 is coupled to the sources of P-channel transistors 26 and 28. The gates of transistors 22, 34, 26 and 44 and the drains of transistors 26 and 44 are connected to a first node 48. The gates of transistors 24, 28, 36 and 42 and the drains of transistors 24 and 42 are connected to a second node 46. The drain of transistor 22 is coupled through a load transistor 36 to ground (a source voltage) and to a first output terminal 38. Likewise, the drain of transistor 28 is coupled through a load transistor 36 to ground and to a second output terminal 40. Node 46 is coupled to ground through a load transistor 42. Node 48 is similarly coupled to ground through a load transistor 44. Circuit 10 additionally includes two P-channel transistors 30 and 32. Transistor 30 couples first input terminal 12 to VCC (a source voltage). Transistor 32 couples second input terminal 14 to VCC. Transistors 30 and 32 serve as an impedance load to read the changes applied to input terminals 12 and 14 in the memory array. The gates of transistors 30 and 32 are coupled to output terminals 38 and 40, respectively. By coupling the gates of both transistors 30 and 32 to the output terminals, both transistors 30 and 32 provide negative feedback to ensure that both input terminals are kept relatively close to each other in voltage. Negative feedback will be discussed in more detail below.

Both the relative size of transistors 22, 24, 26, and 28 and the relative size of transistors 34, 36, 42, and 44 are important. The channels of transistors 22, 24, 26, and 28 are fairly large so that they can be biased into saturation, can sink a lot of current, and can be insensitive to current and voltage variations across their drains and sources. The channels of transistors 34, 36, 42, and 44 are smaller so that they are sensitive to current and voltage variations across their drains and sources.

The current sense amplifier circuit 10 is put into operation by receiving signals (as inputs) from a pair of data lines (or bit lines). Assume an initial state of data "0" is initially present on the data lines. The voltage of input 12 is less than the voltage of input 14. When the data state changes due to an address change or similar event, the voltage of input 12 will attempt to rise or become greater than the voltage of input 14, which will attempt to fall. The voltage change will be slow due to a large line capacitance present on the data lines. If the sense amplifier were to respond to a voltage change, the output would respond equally slowly. While the voltages change very slowly, the currents driven by the data lines change almost instantly.

When the voltage on the data line connected to input 14 attempts to drop, current is caused to flow from the amplifier circuit into the data line. Since the voltage remains unchanged due to the capacitance at input 14, the drain to source voltage and the gate to source voltage remain unchanged. Consequently, current supplied by transistor 32 will also remain unchanged. The additional current drawn from the circuit by input 14 will result in less current flowing through transistors 26 and 28. Current flowing through transistor 44 will also drop because the current through transistor 44 is equal to the current through transistor 26.

The circuit 10 has been designed so that the size of transistors 36 and 44 has smaller channels which are more sensitive to both current and voltage changes. That is, their width to length ratio is smaller. The smaller ratio gives a transistor a higher impedance when conducting. Because of the higher impedance in transistor 44, the voltage across transistor 44 will drop to a greater extent in response to a current drop. This causes the voltage of internal reference node 48 to drop. Since transistor 26 is relatively large, operating in saturation, internal reference node 48 can leak a large amount without affecting the current through transistor 26 or the voltage at input 14.

As the voltage of internal reference node 48 decreases, the gate-to-source voltage of transistor 34 also decreases. This causes the voltage of output 38 to increase. The gate-to-source voltage of transistor 22 increases, but it remains in saturation because the transistor 22 is of relatively large size, and the voltage of output 38 can increase without affecting the operation of transistor 22.

Similar to the voltage of input 14, the voltage of input 12 will change slowly due to the high capacitance associated with the data lines. This will cause transistor 30 to continue to supply the same amount of current. The additional current available from the reduced current consumption of input 12 will be supplied to transistors 22 and 24. The increase in current in transistor 24 will cause an increase in the current of transistor 42. The sizing of the channel of transistor 42 will cause the voltage of internal reference node 46 to increase. The increase in voltage at internal reference node 46 will cause output 40 to be more coupled to ground through transistor 36.

In this way, a voltage differential is seen at outputs 38 and 40 in response to current changes at inputs 12 and 14.

The circuit 10 additionally includes negative feedback provided by transistors 30 and 32. For example, if the voltage of output 40 decreases as a result of the increased current sink of input 14, the gate-to-source voltage of transistor 32 increases. This causes transistor 32 to conduct more, which drives the voltage of input 14 upward. This is opposite to the influence exerted by the data lines. This keeps the voltage differential between input 12 and input 14 to a minimum. By keeping the voltage differential of inputs 12 and 14 to a minimum, future changes occur more quickly and easily.

However, circuit 10 has inherent characteristics that reduce switching performance. During the switching described above, the voltage of internal reference node 46 increases as a result of the increased current through transistor 42. As the voltage of internal reference node 46 increases, the gate-to-source voltage of transistor 42 increases. This causes transistor 42 to switch harder, reducing the resistance through transistor 42 to which internal reference node 46 is coupled to ground. This is negative feedback associated with the internal reference nodes and reduces the speed at which the circuit can switch by limiting the speed at which the voltage of internal reference node 46 can increase. Internal reference node 48 is also affected in the opposite direction.

It is an object of the invention to provide an improved current sense amplifier and a method of the type mentioned above, which are designed to accelerate the amplifier switching times.

Summary of the invention

The above object is achieved according to the invention by an amplifier as defined in claim 1 and a method as defined in claim 9. The present invention is particularly well suited for reading current differentials in bit lines and data lines of semiconductor memories.

The present invention incorporates positive feedback during the time the circuit is switching in response to the reading of a different value. This allows for a much faster response to current differentials at the circuit input. In a more specific application in the field of semiconductor memories, the present invention can be used to read current differentials on bit line pairs and data line pairs, allowing for much faster memory readings.

One of the important features of the invention is that faster circuit operation is achieved without increasing the power requirements of the circuit.

A method aspect of the present invention includes steps for developing a voltage differential at two output terminals based on a current differential at two input terminals. The current differential at the two inputs results from the impedance associated with the state of a memory cell being addressed. The causation of the voltage differential at the two outputs is accelerated by positive feedback and its magnitude is controlled by negative feedback.

Short description of the drawing

In describing the present invention, reference is made to the attached drawings, in which:

Fig. 1 is a circuit diagram of a current sense amplifier according to the prior art;

Fig. 2 is a circuit diagram illustrating an improved current sense amplifier according to the present invention; and

Fig. 3 is a more detailed schematic diagram illustrating an improved current sense amplifier particularly well suited for use in semiconductor memory devices.

Description of the preferred embodiments

Fig. 2 shows a differential current sense amplifier 20 according to an embodiment of the present invention. The circuit of Fig. 2 is based on Fig. 1 and in Fig. 2, like components are designated by the same numerals as shown in Fig. 1. In general, the circuit has been modified to include positive feedback. Transistors 42 and 44 are reconfigured by selectively coupling their drains. The drain of transistor 42 is decoupled from internal reference node 46 and coupled to internal reference node 48. Likewise, the drain of transistor 44 is decoupled from internal reference node 48 and coupled to internal reference node 46.

The general circuit operation of circuit 20, shown in Fig. 2, is the same as the general circuit operation of prior art circuit 10, shown in Fig. 1. However, the change is significant in overcoming the inherent switching limitations present in circuit 10. Circuit 10 includes the undesirable limitations associated with transistors 42 and 44. As arranged in circuit 10, transistors 42 and 44 limit themselves in their ability to modify internal reference nodes 46 and 48. This results in slower switching speeds for the amplifier.

In the prior art circuit 10, the voltage of the internal reference node 46 increases as the current in the transistor 24 increases. This causes the transistor 42 to turn on harder due to the increase in the gate to source voltage of the transistor 42. The transistor 42 has the effect of biasing the voltage of the internal reference node 46 downward. However, it is preferable for the voltage of the internal reference node 46 to increase, with the effect of biasing the transistor 36 downward. This would result in a faster response time for the sense amplifier. Although the voltage of the internal reference node 46 does ultimately increase in the prior art, the voltage increases much more slowly due to the downward bias.

In circuit 20, an embodiment of the present invention, the drain of transistor 42 is connected to internal reference node 48. As the voltage at node 46 increases, transistor 42 turns on harder, but it does not couple node 46 to ground as was done in the prior art. Instead, transistor 42 turns on harder, coupling node 48 more strongly to ground. As shown in Fig. 2, node 48 is connected to the gate of transistor 34. Thus, this promotes Coupling node 48 to ground increases the rate at which transistor 34 turns off, thereby increasing the voltage at output 38.

Switching the drain of transistor 44 to internal reference node 46 (as in Figure 2) also increases the switching speeds of the circuit. As the voltage of internal reference node 48 decreases, transistor 44 switches down (closer to off). Instead of decreasing the strength with which node 48 is coupled to ground (as in the prior art), transistor 44 now decreases the strength with which it pulls internal reference node 46 to ground. This increases the speed at which the amplifier switches by speeding up how quickly transistor 36 turns on, coupling output 40 closer to ground. The use of positive feedback increases the switching speeds of amplifier 20, allowing faster data accesses to semiconductor memories. The term "positive feedback" is used for the following reason. When node 12 (its voltage) drops, (a) this causes node 46 to drop. This causes (b) the gate-source voltage of element 42 to decrease. This causes (c) the voltage at node 48 to increase. When node 48 rises, (d) the gate-source voltage of element 44 increases. When this happens, this causes (e) the voltage of node 46 to drop.

Since the result (e) is the same as (a), this is a feedback loop that tends to amplify its effect, and so it should be called "positive feedback." Positive feedback can be dangerous. The gain can be so large that it will lead to circuit instability when fed back: a situation in which the circuit switches so hard that it cannot switch back. Transistors 30 and 32 provide negative feedback that prevents potential circuit instability. As described earlier, transistors 30 and 32 provide negative feedback that prevents inputs 12 and 14 from differing significantly in voltage. If outputs 38 and 40 try to switch too far, either transistor 30 or transistor 32 will switch harder to stop the process.

Although the negative feedback created by transistors 30 and 32 increases circuit stability, it does not adversely affect the speed at which the amplifier switches. This is because the negative feedback regulates the voltages at inputs 12 and 14, not the currents. The positive feedback begins when the circuit begins to switch as a result of current differences before a significant voltage difference occurs at inputs 12 and 14. The negative feedback does not begin until there is a voltage difference. This provides a beneficial mix of positive feedback to promote and accelerate the actual switching, and negative feedback to maintain circuit stability and reduce the voltage differential of the inputs for faster switching in the future. The negative feedback is primarily active after the switching has taken place.

Of course, the present invention as expressed in the above-mentioned non-limiting embodiment may alternatively be configured with N-channel transistors replacing the P-channel transistors, with P-channel transistors replacing the N-channel transistors, and with the polarity of the source voltages reversed.

Fig. 3 shows a differential current sense amplifier 80 according to an embodiment of the present invention, which is particularly well suited for use in semiconductor memory devices. The circuit of Fig. 3 is based on Fig. 2 and in Fig. 3, like circuit components are designated with the same numerals as shown in Fig. 2. The circuit 80 includes additional circuitry connected to both the write enable and the read enable.

Fig. 3 receives three additional signals, namely READ-EN 76, /RBAD-EN 77 and /WRITE-EN 78. The READ-EN 76 signal is active high when the memory cell array is enabled for reading. The /READ-EN 77 signal is the complement of the READ-EN 76 signal. The /READ-EN 77 signal is low when the memory cell array is enabled for reading. The /WRITE-EN signal is low when the memory cell array is enabled for writing.

Fig. 3 additionally includes eleven transistors and a NAND gate. Six transistors, namely 50, 52, 54, 56, 58 and 60, are connected to the signals READ-EN 76 and /READ-EN 77. Four transistors, namely 64, 66, 68 and 70, are connected to the signal /WRITE-EN 78. The NAND gate 72 is used to determine when the memory cell is not enabled for reading or writing and is used to control the transistor 62.

The additional transistors and the NAND gate modify the circuit 20 of the previously described Fig. 2 in the following way. The gate of the transistor 42 is no longer directly coupled to the internal reference node 46. The gate of the transistor 42 is now coupled to the internal reference node 46 through the transistor 54 and the gate of the transistor 42 is coupled to ground through the transistor 50. Likewise, the gate of the Transistor 44 is coupled to the internal reference node 48 through transistor 56 and the gate of transistor 44 is coupled to ground through transistor 52. The gates of both transistors 50 and 52 are coupled to the /READ-EN signal 77. The gates of both transistors 54 and 56 are coupled to the READ-EN signal 76. The internal reference node 48 is coupled to VCC through transistor 60. The internal reference node 46 is coupled to VCC through transistor 58. The gates of both transistors 58 and 60 are coupled to the READ-EN signal 76. The gate of transistor 30, which provides negative feedback, is coupled to the output 38 through transistor 64 and coupled to VCC through transistor 66. The gate of transistor 32, which also provides negative feedback, is coupled to output 40 through transistor 70 and to VCC through transistor 68. The gates of transistors 64, 66, 68 and 70 are coupled to the /WRITE-EN signal 77. And finally, input 12 is coupled to input 14 through transistor 62. The gate of transistor 62 is coupled to the output of NAND gate 72. NAND gate 72 has one input coupled to /WRITE-EN 78 and the other input coupled to /READ-EN 77.

The sense amplifier circuit 80, similar to the circuit 20 described above, only needs to operate when a memory cell is being read. Thus, when a memory cell is to be read, the signal READ-EN 76 goes high and the signal /READ-EN 77 goes low. During a read operation, the signal /WRITE-EN 78 is high. This keeps the transistors 66 and 68, which are P-channel transistors and have their gates coupled to the signal /WRITE-EN, in an off state. Transistors 50, 52, 58, 60 and 62 are also off. Transistors 54, 56, 64 and 70 are on. During a read operation, the circuit 80 is functionally equivalent to the circuit 20.

During a write operation, the sense amplifier circuit 80 is not needed to read the current value stored in the addressed memory cell. The addressed memory cell is written to and its current value is updated. When a memory cell is written to, the /WRITE-EN signal 78 goes low. The READ-EN signal 76 is low and the /READ-EN signal 77 is high. This places the sense amplifier in an inactive or standby mode. The output signals 38 and 40 are both coupled to ground. Transistors 58 and 60 are on and couple the two internal reference nodes 46 and 48 to VCC. This turns off transistors 22, 24, 26 and 28 and turns on transistors 34 and 36. Turning on transistors 34 and 36 couples both output signals 38 and 40 to ground. Transistors 54 and 56 are off and decouple the gates of transistors 42 and 44 from their respective internal reference nodes 48 and 46, respectively. Transistors 50 and 52 are on and couple the gates of transistors 42 and 44 to ground. As a result, transistors 42 and 44 are off. Input terminals 12 and 14 are decoupled from the rest of the circuit. Transistors 70 and 64 are off and decouple the gate of transistors 30 and 32 from output terminals 38 and 40. Transistors 66 and 68 are on and couple the gates of both transistors 30 and 32 to VCC. Coupling the gates of transistors 30 and 32 to VCC turns transistors 30 and 32 off. Transistor 62 is off as a result of the output of NAND gate 72 being high.

In summary, the current sense amplifier is effectively isolated from the memory cell array during a write operation. Input terminals 12 and 14 are decoupled from the rest of the current sense amplifier circuit 80. Output terminals 38 and 40 are coupled to ground.

During neither a memory read nor a memory write, the READ-EN 76 signal is low and both /READ-EN 77 and /WRITE-EN 78 signals are high. In this case, both inputs to NAND gate 72, namely /READ-EN 77 and /WRITE-EN 78, are high, resulting in an output whose value is low. Transistor 62 is on and couples input terminal 12 to input terminal 14. This effectively eliminates any voltage difference between the two input terminals 12 and 14 and allows a faster reading during the next memory read.

Both Fig. 2 and Fig. 3 illustrate an improved current sense amplifier in accordance with the present invention. Note that one of the circuit features allows for faster reading of current differentials without increasing power requirements.

While this invention has been described with respect to an illustrative embodiment, it is to be understood that this description is not intended to be construed in a limiting sense, but is intended to include all substitutions within the scope of the invention. Various modifications of the illustrative embodiment, as well as other embodiments, will become apparent to those skilled in the art upon reference to this description. The invention is intended to be set forth in the following claims.

Claims (11)

1. Amplifier (20; 80) for a semiconductor circuit, comprising a first and a second input (12, 14); a first and a second output (38, 40); first and second circuit paths (22, 30, 34; 28, 32, 36), each of which is coupled between a first source voltage (VCC) and a second source voltage (ground); wherein the first circuit path comprises a first, a second and a third transistor (22, 30, 34), wherein the first transistor (22) has its source-drain path coupled between the first input (12) and the first output (38); the second transistor (30) has its source-drain path coupled between the first input (12) and the first source voltage (VCC) and the third transistor (34) has its source-drain path coupled between the first output (38) and the second source voltage (ground); wherein the second circuit path comprises a fourth, a fifth and a sixth transistor (28, 32, 36), wherein the fourth transistor (28) has its source-drain path coupled between the second input (14) and the second output (40), the fifth transistor (32) has its source-drain path coupled between the second input (14) and the first source voltage (VCC) and the sixth transistor (36) has its source-drain path coupled between the second output (40) and the second source voltage (ground); and wherein the first, second, fourth and fifth transistors (22, 30, 28, 32) belong to a first channel type and the third and sixth transistors (34, 36) belong to a second channel type different from the first channel type; characterized in that a reference voltage circuit (11) is provided which comprises a first and a second reference node (48, 46) and a third and a fourth circuit path (24, 44; 26, 42); wherein the third circuit path (24, 44) of the reference circuit (11) is coupled between the first input (12) and the second source voltage (ground) and comprises a first resistance (24) and a seventh transistor (44), wherein the first impedance (24) is coupled between the first input (12) and the second reference node (46) and the seventh transistor (44) has its source-drain path coupled between the second reference node (46) and the second source voltage (ground), with its control electrode coupled to the first reference node (48) to provide positive feedback; wherein the fourth circuit path (26, 42) of the reference circuit (11) is coupled between the second input (14) and the second source voltage (ground) and comprises a second impedance (26) and an eighth transistor (42), wherein the second impedance (26) is coupled between the second input (14) and the first reference node (48) and the eighth transistor (42) has its source-drain path coupled between the first reference node (48) and the second source voltage (ground), with its control electrode coupled to the second reference node (46) to provide positive feedback; wherein the seventh and eighth transistors (44, 42) are of the second channel type; the control electrodes of the first and third transistors (22, 34) are coupled to the first reference node (48), the control electrodes of the fourth and sixth transistors (28, 36) are coupled to the second reference node (46); and the control electrodes of the second and fifth transistors (30, 32) are coupled to the first output (38) and the second output (40), respectively, to provide negative feedback. 2. Amplifier according to claim 1, wherein the first impedance is formed from a ninth transistor (24) and the second impedance is formed from a tenth transistor (26); wherein the ninth transistor (24) has its source-drain path coupled between the first input (12) and the second reference node (46) and has its control electrode coupled to the second reference node (46) and the tenth transistor (26) has its source-drain path coupled between the second input (14) and the first reference node (48) and has its control electrode coupled to the first reference node (48). 3. Amplifier according to claim 2, wherein the first, second, fourth, fifth, ninth and tenth transistors (22, 30, 28, 32, 24, 26) are P-channel transistors; and wherein the third, sixth, seventh and eighth transistors (34, 36, 44, 42) are N-channel transistors. 4. The amplifier of claim 2, wherein the first, second, fourth, fifth, ninth and tenth transistors (22, 30, 28, 32, 24, 26) are N-channel transistors; and wherein the third, sixth, seventh and eighth transistors (34, 36, 44, 42) are P-channel transistors. 5. An amplifier according to claim 3 or 4, wherein the first, fourth, ninth and tenth transistors (22, 28, 24, 26) are sized so that they operate in saturation and are insensitive to voltage changes between their drains and sources. 6. An amplifier according to claim 3 or 4, wherein the third, sixth, seventh and eighth transistors (34, 36, 44, 42) are sized so that they are sensitive to both small current changes and voltage changes between their drains and sources. 7. The amplifier of claim 1, wherein the first and second inputs (12, 14) are coupled to a pair of bit lines. 8. The amplifier of claim 1, wherein the first and second inputs (12, 14) are coupled to a pair of data lines. 9. A method for sensing a state of a memory cell, comprising the steps of developing different currents at two inputs (12, 14) of an amplifier (20; 80) related to the impedances associated with the state of the memory cell; developing voltage transitions in the amplifier (20; 80) corresponding to the pair of different currents and developing differential voltages at two outputs (38, 40) of the amplifier (20; 80) related to the pair of different currents; marked by accelerating the voltage transitions in the amplifier (20; 80) by positive feedback, the positive feedback responding to the different currents developed at the two inputs (12, 14); and controlling the voltages at the inputs (12, 14) by negative feedback, whereby the output voltages are fed back to the input voltages. 10. The method of claim 9, wherein the two inputs (12, 14) are coupled to a pair of bit lines. 11. The method of claim 9, wherein the two inputs (12, 14) are coupled to a pair of data lines.