DE69412778D1 - Decoding circuit insensitive to supply voltage fluctuations - Google Patents

Decoding circuit insensitive to supply voltage fluctuations

Info

Publication number
DE69412778D1
DE69412778D1 DE69412778T DE69412778T DE69412778D1 DE 69412778 D1 DE69412778 D1 DE 69412778D1 DE 69412778 T DE69412778 T DE 69412778T DE 69412778 T DE69412778 T DE 69412778T DE 69412778 D1 DE69412778 D1 DE 69412778D1
Authority
DE
Germany
Prior art keywords
supply voltage
decoding circuit
voltage fluctuations
circuit insensitive
insensitive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69412778T
Other languages
German (de)
Other versions
DE69412778T2 (en
Inventor
Chiaki Kondoh
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Electronics Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Application granted granted Critical
Publication of DE69412778D1 publication Critical patent/DE69412778D1/en
Publication of DE69412778T2 publication Critical patent/DE69412778T2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
    • H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01728—Modifications for accelerating switching in field-effect transistor circuits in synchronous circuits, i.e. by using clock signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/096—Synchronous circuits, i.e. using clock signals
    • H03K19/0963—Synchronous circuits, i.e. using clock signals using transistors of complementary type

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Logic Circuits (AREA)
  • Dram (AREA)
DE69412778T 1993-12-28 1994-12-20 Decoding circuit insensitive to supply voltage fluctuations Expired - Fee Related DE69412778T2 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5335189A JP2616684B2 (en) 1993-12-28 1993-12-28 Decoder circuit

Publications (2)

Publication Number Publication Date
DE69412778D1 true DE69412778D1 (en) 1998-10-01
DE69412778T2 DE69412778T2 (en) 1999-05-06

Family

ID=18285763

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69412778T Expired - Fee Related DE69412778T2 (en) 1993-12-28 1994-12-20 Decoding circuit insensitive to supply voltage fluctuations

Country Status (4)

Country Link
US (1) US5530380A (en)
EP (1) EP0664614B1 (en)
JP (1) JP2616684B2 (en)
DE (1) DE69412778T2 (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6184718B1 (en) 1996-12-20 2001-02-06 Translogic Technology, Inc. Dynamic logic circuit
US5859547A (en) * 1996-12-20 1999-01-12 Translogic Technology, Inc. Dynamic logic circuit
US6002271A (en) * 1997-05-12 1999-12-14 International Business Machines Corporation Dynamic MOS logic circuit without charge sharing noise
US7195642B2 (en) 2001-03-13 2007-03-27 Mckernan Daniel J Method and apparatus for fixing a graft in a bone tunnel
US7594917B2 (en) 2001-03-13 2009-09-29 Ethicon, Inc. Method and apparatus for fixing a graft in a bone tunnel
US6517546B2 (en) * 2001-03-13 2003-02-11 Gregory R. Whittaker Method and apparatus for fixing a graft in a bone tunnel
US8617176B2 (en) 2011-08-24 2013-12-31 Depuy Mitek, Llc Cross pinning guide devices and methods

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4345170A (en) * 1980-08-18 1982-08-17 Bell Telephone Laboratories, Incorporated Clocked IGFET logic circuit
US4668880A (en) * 1984-03-26 1987-05-26 American Telephone And Telegraph Company, At&T Bell Laboratories Chain logic scheme for programmed logic array
FR2596595B1 (en) * 1986-03-28 1988-05-13 Radiotechnique Compelec DOMINO TYPE MOS LOGIC HOLDER
JPS6342216A (en) * 1986-08-08 1988-02-23 Hitachi Ltd Composite circuit containing bipolar transistor and field effect transistor
JPS63228494A (en) * 1987-03-18 1988-09-22 Fujitsu Ltd Dynamic decoder circuit
US4797580A (en) * 1987-10-29 1989-01-10 Northern Telecom Limited Current-mirror-biased pre-charged logic circuit
US5144163A (en) * 1988-03-14 1992-09-01 Matsushita Electric Industrial Co., Ltd. Dynamic BiCMOS logic gates
US5146115A (en) * 1991-07-26 1992-09-08 Zilog, Inc. Domino-logic decoder

Also Published As

Publication number Publication date
US5530380A (en) 1996-06-25
JPH07202670A (en) 1995-08-04
EP0664614B1 (en) 1998-08-26
DE69412778T2 (en) 1999-05-06
EP0664614A1 (en) 1995-07-26
JP2616684B2 (en) 1997-06-04

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP

8339 Ceased/non-payment of the annual fee