DE69331941T2 - Protection against electrostatic discharge - Google Patents

Description

The present invention relates to circuits for protecting an internal circuit of a semiconductor device against electrostatic discharge phenomena (ESD).

A semiconductor memory device is usually provided with a circuit for protecting the internal circuit of a chip against static electricity supplied to the chip from the outside. The protection circuit includes an ESD prevention element provided at an input terminal of the chip. This means that punch-through phenomena occur in the ESD prevention element in the input terminal of the chip to discharge high-voltage current caused by electrostatic discharge to the ground voltage terminal when static electricity is supplied to the chip from the outside. The physical mechanism of ESD phenomena and the preventive measures against them are specifically described in "Internal Chip ESD Phenomena Protection Circuit" published in IEEE TRANSACTION ON ELECTRON DEVICE, pages 2133-2139, volume 35, No. 12, Dec. 1989. Also our patent application GB 2 252 200 (corresponding to Korean patent application No. 91-1128) discloses a device for preventing ESD between the input terminal, the source voltage and the ground voltage, wherein an n+; diffusion region separated by a field oxide layer is connected to the terminal and the ground voltage so that the current caused by static electricity is diverted to the ground voltage terminal when static electricity or ESD stress voltage is applied to the terminal, the technology of which is essentially realized by the punch-through phenomena of the n+ diffusion region separated by the field oxide layer.

Referring to Fig. 1 of the accompanying schematic diagrams, which shows an equivalent circuit of a conventional circuit for protecting an internal circuit against electrostatic discharge, an input terminal 1 and an internal circuit 20 are connected through a metal line 10. A TFD element for preventing ESD and a MOS diode T1 used for a clamping circuit are connected in parallel between the metal line 10 and the ground voltage Vss. There is also provided a resistor R1 consisting of an n+ diffusion region between a node 11 connecting the metal line 10 to the TFD element and a node 12 connecting the metal line 10 to the MOS diode T1. The resistor R1 has a high resistance value to protect a gate oxide layer 21 of an NMOS transistor N1 of the internal circuit 20 against an ESD stress voltage. When an ESD stress voltage is applied from the input terminal 1 to the metal line 10 (about 3000 V is used as a test voltage), the excess current is immediately discharged through the TFD element, and the overvoltage dropped by the resistor R1 is conducted to the internal circuit 20. Thus, the ESD stress voltage is prevented from affecting the internal circuit.

However, such a conventional circuit for protecting the internal circuit against electrostatic discharge generates a long delay time T1 during input signal transmission, which is caused by parasitic components induced between the node 12 and the internal circuit 20, i.e., the parasitic resistance τ1 and the capacitances c1 and c2. The RC delay time τ1 can be expressed by Equation 1:

τ1 = R1·c1 + (R1 + r1)·c2 = R1·(c1 + c2) + r1·c2 Equation 1)

If it is assumed that R1, r1, c1 and c2 are 500Ω, 200Ω, 2pF and 2pF, the delay time τ1 becomes equal to 2.4 ns.

The RC delay time increases with the values of the resistances and capacitances and with the length of the metal line 10. Furthermore, as the RC delay time increases, the transmission speed of the input signal from the terminal to the internal circuit is slowed down.

This is because an increase in the parametric values of the resistive components is required to reduce the excessive ESD stress voltage. This, however, results in an excessive delay in the transmission rate of the input signal.

The preferred embodiments of the present invention aim to provide a method for protecting an internal circuit of a semiconductor device against electrostatic discharge, which can reduce the RC delay time of an input signal.

According to one aspect of the present invention there is provided a method of protecting an internal circuit of a semiconductor device against electrostatic discharge as defined in claim 1. Further modifications are defined in claims 2 to 5.

Preferably, the resistor is connected to a gate of a MOS transistor provided in the internal circuit.

Preferably, the resistor has a diffusion region with a conductive material.

Preferably, another resistor and a clamping device are cascaded between the ground voltage terminal and a node of the conducting path connecting the input terminal and the RC delay stage.

For a better understanding of the invention and to show how it can be brought into effect, the following is now presented in the form By way of example, reference is made to Fig. 2 of the accompanying schematic diagrams which illustrates an equivalent circuit of a circuit for protecting an internal circuit of a semiconductor device against electrostatic discharge.

Referring to Fig. 2, a metal line 100 connects an input terminal 110 to an internal circuit 20. A TFD element is connected between a node 101 and a ground voltage Vss, and a resistor R2' and a MOS diode T1 are cascaded between a node 102 and a ground voltage. The resistor R2' is used to protect the MOS diode T1 used for a clamp circuit from an ESD stress voltage.

The internal circuit 200 is, for example, a DC-AC converter as generally used in a CMOS integrated circuit. Furthermore, a parasitic resistance r2 and the capacitances c3 and c4 are present between the node 102 and the internal circuit 200 of the metal line 100. In addition, another resistor R2 is connected to an input terminal 210 of the internal circuit 200 to protect the gate oxide layers of the MOS transistors against ESD stress voltage. The resistors R2' and R2 consist of n+ diffusion regions.

The resistor R2 for protecting the internal circuit 200 against ESD stress voltage is connected between the RC delay stage consisting of the parasitic resistance r2 and the capacitance c4 and the input terminal 210 of the internal circuit 200, so that the components that have an influence on the RC delay time are only the parasitic resistance r2 and the capacitance c4. Thus, the RC delay time τ2 can be expressed by Equation 2.

τ2 = r2·c4 (Equation 2)

If it is assumed that the values of the parasitic resistance r2 and the capacitance c4 are 200Ω and 2pF, respectively, the RC delay time τ2 becomes 0.4 ns. This is 2 ns less than the RC delay time τ1 (= 2.4 ns) of the conventional circuit of Fig. 1. In the present embodiment, the values of the resistors R2' and R2 are set to 500Ω. If the values of the resistors R2' and R2 are set to more than 500Ω in order to protect the gate oxide layer of the MOS transistor of the internal circuit 200 against larger ESD stress voltage, the RC delay time is not affected thereby. Namely, according to the present embodiment, the RC delay time is determined only by the parasitic resistance and capacitance physically associated with the metal line 100 connecting the input terminal 110 and the internal circuit 200. Of course, the parasitic resistance is proportional to the length of the metal line 100.

Thus, the resistance for protecting the internal circuit against electrostatic discharge is designed so that it does not affect the RC delay time, and the delay time of the input signal is considerably reduced by the circuit for protecting the internal circuit against electrostatic charge according to the invention.

The term "earth potential" (or similar terms such as for example, "earth voltage" or "earth" potential or "earth" voltage) is used for convenience in this specification to denote a reference potential. As will be understood by those skilled in the art, although such a reference potential may normally be a zero potential, it is not essential that it be so and it may be a non-zero reference potential.

The invention is not limited to the details of the above embodiment.

Claims (5)

1. A method for protecting an internal circuit (200) of a semiconductor device against electrostatic discharge, comprising: Connecting a first end of a conductive path (100) containing an RC delay stage (r2, c4) between the first end and a second end directly to an input terminal (110) for receiving an input signal to be supplied to the internal circuit; Connecting a punch-through element (TFD) to connect the conducting path (100) to a ground voltage (Vss) directly to the conducting path between the input terminal (110) and the RC delay stage (r2, c4); marked by: Determining that the RC delay time (τ2) for the propagation of signals from the input terminal to the second end of the conductive path when the second end of the conductive path is directly connected to the internal circuit (200) is equal to the RC delay time (τ2) for the propagation of signals from the input terminal to the second end of the conductive path when respective ends of a resistor (R2) having a certain resistance value are directly connected to the second end of the conductive path and the internal circuit (200); and then connecting the respective ends of a resistor (R2) having this specific resistance value directly to the second end of the conductor track and the internal circuit (200). 2. Method according to claim 1, wherein the resistance (R2) has a value of 500Ω and the values of the parasitic resistance and capacitance are 200Ω and 2pF respectively. 3. A method according to claim 1 or claim 2, wherein the resistor (R2) is connected to a gate (201) of a MOS transistor provided in the internal circuit (200). 4. The method of claim 3, wherein the resistor (R2) has a diffusion region with a conductive material. 5. A method according to claim 1, 2, 3 or 4, wherein a further resistor (R2') and a clamping device (T1) are cascaded between the ground voltage and a node (102) on the conducting path (100) which connects the input terminal (110) and the RC delay stage (r2, c3, c4).