DE69327858T2 - Semiconductor memory device with a test circuit - Google Patents

Description

BACKGROUND OF THE INVENTION Field of the invention

The present invention relates to a semiconductor memory device having a test circuit for implementing an operation test.

Description of the state of the art

A typical semiconductor memory device is described as a DRAM (dynamic random access memory) with a storage capacity of 4 Mbit.

Fig. 1 is a block diagram showing an example of a 4-bit DRAM. According to this figure, a single input and output section and two memory cell arrays 52a and 52b are allocated to four blocks 50, respectively. Furthermore, in Fig. 1, the input and output section 51 for inputting a test signal and for outputting a test result signal are shown at two different positions to facilitate understanding of their functions.

Each memory cell array 52a and 52b can store information data for 512 kbits. Thus, each block 50 has a storage capacity of 1 Mbit, and the device has a storage capacity of 4 Mbits in total.

To implement an operation test of the semiconductor memory device described above, three switches 53a, 53b and 53c are first set to test (T in Fig. 1) for the Input of test signals through the input and output section 51 so that the same signal is simultaneously written into a single memory cell of the memory cell array 51a and a single memory cell of the memory cell array 52b. Thus, when these two test signals are simultaneously read, an output of a logic circuit 57a (an inverted value or an exclusive OR) is at a "high" level (hereinafter referred to as an H level) and an output of a logic circuit 57b (non-inverted value or an exclusive OR) is at a "low" level (hereinafter referred to as an L level) as long as the semiconductor memory device is normal in terms of its operation. Thus, a MOS transistor 56a is turned on and a MOS transistor 56b is turned off so that a signal of Vcc volts (the H level) is output from the input and output section 51. On the other hand, in the case where the semiconductor memory device does not perform a normal operation, due to the fact that the output signal from the input and output section 51 is at the L level, it is possible to discriminate the memory device as a defective device.

In the 4-bit DRAM described above, since the memory cell array is divided into two parts in a single block 50, in the operation test, the test signal is simultaneously written and read for each bit from the two memory cells. Here, since the storage capacity of each memory cell array 52a or 52b is 512 kbit, the signal writing and reading operation is repeated 512 x 1024 times to complete the overall operation test for a single DRAM.

Fig. 2 is a block diagram showing a similar example of an 8-bit DRAM with a total storage capacity of 4 Mbit. In the DRAM shown in Fig. 2, a single memory cell array 62 is assigned to each of eight blocks 60.

To implement an operation test, test signals are input to each memory cell array 62 having a storage capacity of 512 kbits through each of the eight input and output sections 61 and then read therefrom. In this case, when the level of the read test signal is "1", an output A is at an "H" level and an output /A is at an L level, so that a MOS transistor 63a is turned on and a MOS transistor 63b is turned off in a read circuit 63. Accordingly, a signal of Vcc volts (i.e., the H level) is output from the input and output section 61. In contrast, when the signal read from the memory cell array 62 is "0", a signal of 0 volts (i.e., L level) is output from the input and output section 61.

Furthermore, a prior art 16-bit DRAM is almost identical to this 8-bit DRAM in terms of device configuration. That is, the DRAM includes 16 blocks each having a single memory cell array and a single input and output section without providing any test circuit. Furthermore, in the case of the memory capacity of 4 Mbit, the memory capacity of a single memory cell array is 256 kbit.

As described above, in the prior art multi-bit (8- or 16-bit) DRAM, which is different from the case of the 4-bit DRAM described above, the Test signal for only a single memory cell at a time for each bit written and read.

In the 8-bit DRAM shown in Fig. 2, due to the fact that the storage capacity of each memory cell array 62 is 512 kbit, the signal writing and reading operations must be repeated 512 x 1024 times to implement the overall operation test of a single DRAM.

Furthermore, as already explained, in the case of the 16-bit DRAM in which the memory cell capacity of a single memory cell array is 256 kbit, the signal writing and reading operations must be repeated 256 x 1024 times to implement the entire operation test of a single DRAM.

As described above, in the case of the multi-bit DRAMs with the same storage capacity, the repetition number of test signal write and read operations required for the overall operation test of a single DRAM decreases as the number of bits increases.

In contrast, in the actual operational test, due to the fact that the number of drivers and operators is limited, the number of chips that can be simultaneously tested by a single test system decreases as the number of bits increases, with the result that a long time is required to implement the operational test of the DRAMs.

The reason for this is described in more detail by considering a case of a test system in which the number of drivers and comparators is 40 each and the maximum number for simultaneous measurement is 8 This means that this system is equipped with 40 drivers for writing the test signals into the memory cells, as well as 40 comparators for distinguishing whether the read test signals are correct or not (in other words, 40 bits can be measured simultaneously), and the maximum number of chips that can be tested simultaneously is 8.

In the case of the operation test of the 4-bit DRAM, as shown in Fig. 3, the test system 71 can implement the operation test of 8 DRAMs 70 simultaneously (i.e., the same number as the maximum number for simultaneous measurement). Further, in Fig. 3, P1 to P32 denotes terminals (i.e., I/O pins) for connecting the input and output portions of the DRAMs to the test system 71, respectively.

Here, the test time T(4) required to implement the operational test of 100 units of 4-bit DRAM 70 can be estimated, for example, as follows:

T(4) = (100 / 8) {k + (512 x 1024. t) } = 12. 5 (k + 2¹⁹ t)

such that k denotes a set-up time required to implement a single operation test; and t denotes the time required to write and read a single test signal. Furthermore, the signal writing and reading operation is repeated 512 x 1024 times for each operation test.

Here, for K = 12.5 k and T = 12.5 · 2¹⁹t, T(4) = K + T

Furthermore, as shown in Fig. 4, in the case of the operation test of the 8-bit DRAMs 80 due to the fact that the number of drivers and comparators is 40, the number of chips that can be simultaneously tested by the test system 71 is 5. Furthermore, in Fig. 4, P1 to P40 designates the connection for connecting the input and output sections of the DRAM to the test system.

Here, the test time T(8) required to implement the operational test of 100 units of 8-bit DRAMs 80 can be estimated, for example, as follows:

T(8) = (100 / 5) {k + (512-1024 . t) } = 20 (k + 2¹⁹ t)

Accordingly,

T(8) = 1 . 6 (K + T)

Furthermore, in the case of the operational test of the 16-bit DRAMs (not shown), the number of chips that can be tested simultaneously is 2.

Here, the test time T(16) required to implement the operational test of 100 units of 16-bit DRAMs can be estimated as follows:

T(16) = (100 / 2) {k + (256 x 1024 t) } = 50 (k + 2¹⁸ t)

Accordingly:

T(6) = 4 . 0 (K + 0 . 5 T)

This means that the test time of the 8-bit DRAMs 80 is approximately 1.6 times longer than that of the 4-bit DRAM 70. The time required to write and read data to and from On the other hand, the time required for the start-up of a single cell is approximately 300 ns at most; on the other hand, several tens of seconds are required as the start-up time when the ambient temperature is high, so that K » T. Therefore, the test time of the 16-bit DRAMs is approximately 4 times longer than that of the 4-bit DRAMs. In other words, the time required for the operational test increases as the number of chips that can be tested simultaneously decreases.

In order to reduce the time required for implementing the operation test of the multi-bit DRAMs, it may be possible to divide the memory cell array into two or more arrays according to a single bit, in the same manner as in the case of the 4-bit DRAM 70 mentioned above and shown in Fig. 1.

However, in the case of multi-bit DRAMs, it is practically impossible to divide the memory cell array of a single block into two or more parts, since the chip size inevitably increases and hence the cost thereof also increases.

In addition, due to the fact that K » T as described above, even if the time t required for the individual test signal writing and reading operations is reduced, it is impossible to sufficiently reduce the total time required for the test operation.

Furthermore, without limitation only DRAMs, other semiconductor memory devices also have the same problems as described above.

SUMMARY OF THE INVENTION

Taking these problems into account, a technical object of the present invention is to provide a semiconductor memory device whose test operation can be implemented in a short time, regardless of the number of bits.

According to the present invention, there is provided an integrated semiconductor circuit comprising:

several memory cell arrays;

input and output sections, each provided so as to be associated with each of the memory cell arrays; and

an allocation device provided between the memory cell arrays and the input and output sections for allocating one of the memory cell arrays to one of the input/output sections in an ordinary mode and a plurality of the memory cell arrays to a part of the input and output sections in a test mode.

In the semiconductor memory device according to the present invention, in the ordinary mode, a single memory cell array is allocated to a single input and output section. In the information signal writing and reading operation, information signals are written or read between each memory cell array and input and output section corresponding to each memory cell array. However, in the test operation, the test signals are written or read between a single input and output section and a plurality of memory cell arrays.

In other words, due to the fact that only a part of the input and output sections are used during test operation, it is possible to reduce the number of I/O pins, associated with the chip, thereby increasing the number of chips whose test operation can be implemented simultaneously, thereby reducing the overall time required for the operational test of the memory device.

BRIEF DESCRIPTION OF THE DRAWINGS

The attached drawing shows:

Fig. 1 is a schematic block diagram showing an example of semiconductor memory devices according to the prior art;

Fig. 2 is a schematic block diagram showing another example of semiconductor memory devices according to the prior art;

Fig. 3 is a conceptual diagram showing the status in which the prior art semiconductor memory devices shown in Fig. 1 are incorporated into a test system;

Fig. 4 is a conceptual diagram showing the status in which the prior art semiconductor memory devices shown in Fig. 2 are incorporated into a test system;

Fig. 5 is a schematic block diagram showing a first embodiment of the semiconductor memory device according to the present invention;

Fig. 6 is a conceptual diagram showing the state in which the semiconductor memory devices according to the invention shown in Fig. 5 are mounted in a test system;

Fig. 7 is a schematic block diagram showing a second embodiment of the semiconductor memory device according to the present invention; and

Fig. 8 is a conceptual diagram showing the status in which the semiconductor memory devices according to the invention shown in Fig. 7 are inserted into a test system.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

A first embodiment of the memory device according to the present invention will be described hereinafter with reference to the attached drawings. As an example of a first embodiment, an 8-bit DRAM is written which is configured so that only 4 bits are used in the test operation.

Fig. 5 is a block diagram showing the configuration of the DRAM in accordance with the first embodiment. As shown in Fig. 5, two input and output sections 11a and 11b and two memory cell arrays 12a and 12b are respectively assigned to each of the four blocks 10. Thus, the chip has 8 input and output sections and 8 memory cell arrays in total. Furthermore, in Fig. 5, two input and output sections 11a and 11b are shown at different positions for better understanding.

Each of the memory cell arrays 12a and 12b can store information signals for 512 kbits. Accordingly, each block 10 has a storage capacity of 1 Mbit, and the device has a total storage capacity of 4 Mbits. Furthermore, each block 10 contains a write circuit 17 and a read circuit 18.

The write circuit 17 includes switching switches 13a and 13b for switching the normal mode (N in Fig. 5) to the test mode (T in Fig. 5) or vice versa, and test switches 14a and 14b for switching an on state to an off state or vice versa for the input signals when the test mode is selected.

The reading circuit 18 includes a logic circuit 16a for inputting an output A of the memory cell array 12a and the output B of the memory cell array 12b and outputting an inverted value of the exclusive OR of the two outputs /A and /B, and a logic circuit 16b for inputting an output /A of the memory cell array 12a and the output /B of the memory cell array 12b and outputting a non-inverted value of the exclusive OR of the two outputs /A and /B. Further, the drain of the MOS transistor 15a is connected to a power supply voltage Vcc, and the source of the MOS transistor 15b is connected to the ground. Further, the source of the MOS transistor 15a is connected to the drain of the MOS transistor 15b, so that an output buffer is constructed. In this way, two MOS transistors 15c and 15d are connected to form an output buffer. In the normal mode, the gate electrodes of the MOS transistors 15a to 15d are connected to the outputs A, /A, B and /B of the memory cell arrays via the switches 13c to 13f, respectively. Furthermore, in the test mode, the gate electrodes of the MOS transistors 15a and 15b connected to the logic circuits 16a and 16b, respectively, but the gates of the MOS transistors 15c and 15d are connected to ground.

In the semiconductor memory device described above, in order to write ordinary information signals, first, the changeover switches 13a and 13b of the writing circuit 17 are both set to the normal mode (N). At this time, the test switches 14a and 14b are set to the power-off state. Thus, the information signals input through the input and output section 11a are written into the memory cell array 12a, and the information signals input through the input and output section 11b are written into the memory cell array 12b. Thus, the information signals input through the eight input and output sections can be written into the associated memory cells of the eight memory cell arrays in parallel with each other.

Further, for reading the ordinary information signals, the changeover switches 13c to 13f of the reading circuit 18 are set to the normal mode for reading the information signals from the respective memory cells of the memory cell arrays 12a and 12b, respectively. In this case, when the information signal read from the memory cell array 12a is, for example, "1", due to the fact that the output H is at the H level and the output /A is at the L level, the MOS transistor 15a is turned on and the MOS transistor 15b is turned off. Thus, a signal of Vcc volts (i.e., an H level) is output from the input and output section 11a. On the other hand, when the information signal read from the memory cell array 12a is at "0", a signal of 0 volts (i.e., the L level) is output from the input and output section 11a. In the same manner, the outputs of the memory cell array 12b from the input and output section 11b. As described above, when the information signals are read, the information signals read from the eight memory cell arrays can be output in parallel to each other via the eight input and output sections, respectively.

On the other hand, in the above-described operation test mode of the semiconductor memory device, first, the switching switches 13a to 13f are set to the test mode. Further, at this time, the test switches 14a and 14b are set to the power-off state. Thus, the single input and output section 11a is connected to the memory cell arrays 12a and 12b, respectively, and the input and output section 11b is not connected to the memory cell arrays 12a and 12b. Further, the gate electrodes of the MOS transistors 15a and 15b are connected to the outputs of the logic circuits 16a and 16b, respectively; on the other hand, the gate electrodes of the MOS transistors 15a and 15d are grounded via the switches 13e and 13f. That is, in the operation test mode, only the input and output section 11a is used, and the input and output section 11b is not used. Thus, only four input and output sections of the eight input and output sections in total are used, without using the remaining four input and output sections.

Thereafter, test signals for 512 bits are input in sequence via the input and output section 11b, so that the same test signals are written into the memory cell arrays 12a and 12b simultaneously, respectively.

After all test signals for 512 kbit have been written, these written test signals are read out in sequence. In this case, the test signals written simultaneously to the respective Memory cells of the memory cell arrays 12a and 12b are read out simultaneously. Accordingly, when the semiconductor memory device performs a normal operation, the output signals A of the memory cell array 12a always have an equal level to the output signals B of the memory cell array 12b. In the same way, the output signals /A of the memory cell array 12a always have an equal level to the output signals /B of the memory cell array 12b.

Here, since the logic circuit 16a outputs an inverted value of the exclusive OR when A = B, the H level signal is input to the gate electrode of the MOS transistor 15a to turn on the MOS transistor 15a. Further, since the logic circuit 16b outputs an inverted value of the exclusive OR when /A = /B, the L level signal is input to the gate electrode of the MOS transistor 15b to turn off the MOS transistor 15b.

Therefore, when the DRAM performs a normal operation, signals of Vcc (i.e., the H level) are output from the input and output section 11a with respect to all the read test signals.

On the other hand, in the case where the DRAM does not perform a normal operation; that is, when the writing and reading operations in the memory cell arrays 12a and 12b are not performed normally, there is essentially no possibility that A = B (i.e., /A = /B) can be achieved with respect to all of the test signals of the 512 kbits read from the memory cell arrays 12a and 12b. Therefore, in the case where any L-level signals are output from the input and output section 11a, it is possible to discriminate the device as defective.

As described above, in the case of 8-bit DRAM, due to the fact that only 4 bits are used in the operational test mode, it is possible to increase the number of chips that can be tested simultaneously compared to conventional memory devices.

In the same manner as in Fig. 4, when the test system 71 is used whose number of drivers and comparators is 40 and whose maximum number for simultaneous measurement is 4, it is possible to set the 8 DRAMs simultaneously (i.e., the number corresponding to the maximum number for simultaneous measurement) according to this first embodiment, as shown in Fig. 6. Therefore, the time T(8)' required for the operation test of the 100 chips can be expressed as:

T(8)' - (100 / 8) {k + (512 · 1024 . t) } = 12 . 5 (k + 2¹⁹ t)

Accordingly:

T(8) = (K + T)

This test time is the same as that required by the state of the art 4-bit DRAM 70.

As described above, in the 8-bit DRAM according to the present invention, it is possible to reduce the test time required for the test operation.

A second embodiment of the semiconductor memory device according to the present invention will be described hereinafter with reference to the attached drawings.

As an example of the second embodiment, an 8-bit DRAM constructed so that only 2 bits are used in the operation test will be explained below.

Fig. 7 is a block diagram showing the configuration of the DRAM in accordance with the second embodiment. As shown in Fig. 7, four input and output sections 31a to 31d and four memory cell arrays 32a to 32d are respectively assigned to each of the two blocks 30. Thus, the chip has a total of 8 input and output sections and 8 memory cell arrays. Furthermore, in Fig. 7, the input and output sections 31a to 31d are shown at two different positions for better understanding.

Each of the memory cell arrays 32a to 32d can store information signals for 512 kbit in the same way as in the first embodiment. Accordingly, the device has a total storage capacity of 4 Mbit. Furthermore, each block 30 contains a write circuit 37 and a read circuit 38.

The write circuit 37 includes switching switches 33a to 33d for switching the normal mode (N in Fig. 7) to the test mode (T in Fig. 7) or vice versa, and test switches 34a to 34d for switching an on state to an off state or vice versa for the input signals when the test mode is selected.

The reading circuit 38 includes a logic circuit 36d for inputting four output variables A, B, C and D of the memory cell arrays 32a to 32d and for outputting an inverted value of the exclusive OR operation of the four output variables A to D, and a logic circuit 36 for inputting four output variables /A, /B, /C and /D of the four memory cell arrays 32a to 32d and for outputting a non-inverted value of the exclusive OR of the four outputs /A to /D. Further, the drain electrode of a MOS transistor 35a is connected to a power supply voltage Vcc, and the source electrode of a MOS transistor 35b is connected to ground. Further, the source electrode of the MOS transistor 35a is connected to the drain electrode of the MOS transistor 35b so that an output buffer is constructed. In the same way, the MOS transistors 35c and 35d; 35e and 35f; and 35g and 35h are connected respectively so that an output buffer is constructed. In the normal mode, the gate electrodes of the MOS transistors 35a to 35h are connected to the outputs A, /A, B, /B, C, /C, D and /D of the memory cell arrays 32a to 32d, respectively, via the switching switches 33e to 33a. Further, in the test mode, the gate electrodes of the MOS transistors 35a and 35b are connected to the logic circuits 36a and 36b, respectively, but the gate electrodes of the other MOS transistors 35c to 35h are connected to the ground.

In the semiconductor memory device described above, in order to write ordinary information signals, first, the changeover switches 33a to 33d of the writing circuit 37 are all set to the normal mode (N) in the same manner as in the first embodiment. In addition, the test switches 34a to 34d are set to the power-off state. Accordingly, the information signals input via the 8 input and output sections can be written in parallel to each other into the associated memory cells of the 8 memory cell arrays.

Further, for reading ordinary information signals, the changeover switches 33e to 331 of the reading circuit are set to the normal mode (N in Fig. 7) for reading the information signals from the respective memory cells of the memory cell arrays 32a to 32d in the same manner, respectively as in the first embodiment. In this way, since the MOS transistors 35a to 35h in the reading circuit 38 are turned on or off according to the values of the information signals read, the input and output sections 31a to 31d output a signal of Vcc or 0 volts. As described above, when the information signals are read, the information signals read from the 8 memory cell arrays can be output in parallel to each other through the 8 input and output sections, respectively.

The switching operation of the second embodiment is roughly the same as that in the case of the first embodiment.

In the operation test mode of the above-described semiconductor memory device, first, the switching switches 33a to 331 are set to the test mode (T in Fig. 7). Further, at this time, the test switches 34a to 34d are set to the power-on status. Thus, only the input and output section 31a is used, and the other input and output sections 31b to 31d are not used. Thus, only two of the input and output sections of the 8 input and output sections in total are used, without using the remaining 6 input and output sections.

Thereafter, in the same manner as in the first embodiment, test signals for 512 kbits are inputted in sequence through the input and output sections 31a, and further, these written test signals are read out in sequence through the logic circuits 36a and 36b and the MOS transistors 35a and 35b. In this case, only when the semiconductor device performs a normal operation, a signal of substantially Vcc volt is outputted. If the If operation is not carried out normally, a signal of 0 volts is output.

As described above, in the case of the 8-bit DRAM of this embodiment, since only 2 bits are used in the operational test mode, it is possible to increase the number of chips that can be simultaneously tested compared with the conventional memory devices.

In the same manner as in Fig. 4, when the test system 71 is used, the number of drivers and comparators of which is 40 and the maximum number of simultaneous measurements is 8, it is possible to set the 8 DRAMs in this embodiment simultaneously (i.e., the number is equal to the maximum number of simultaneous measurements) as shown in Fig. 8. Therefore, the time T(8)" required for the operation test for 100 chips can be expressed as

T(8)" - (100 / 8) {k + (512 x 1024 t) } = 12 5 (k + 12¹⁹ t)

Accordingly:

T" (8) = (K + T)

This test time is equal to that required in the prior art for the 4-bit DRAM 70 and in the first embodiment for the 8-bit DRAM 20.

As described above, even in the 8-bit DRAM according to the second embodiment, it is possible to reduce the test time required for the operation test.

Furthermore, in the above-mentioned first and second embodiments, regardless of the fact that the number of bits used in the operation test mode is set to 4 or 2, it is of course possible to set any other value as the number of bits used. For example, it is possible to construct the device such that only one bit is used in the operation test mode.

Furthermore, in the above-mentioned embodiments, regardless of the fact that the 8-bit DRAM is described as an example, the same effect can be obtained with other 16-bit or 18-bit DRAMs in the same manner. Furthermore, the present invention can be applied to various semiconductor memory devices other than the DRAMs in the same manner as described above.

As described above, according to the present invention, it is possible to provide a semiconductor memory device whose operation test can be implemented in a short time, regardless of the number of bits.

The reference signs in the patent claims serve to enhance understanding and do not limit their scope of protection.

Claims (4)

1. Integrated semiconductor circuit comprising: a plurality of memory cell arrays (12a, 12b; 32a-32d); and input and output sections (11a, 11b; 31a-31d) each provided in association with each of the memory cell arrays; marked by an allocation device (17; 37) provided between the memory cell arrays and the input and output sections, for allocating one of the memory cell arrays to one of the input and output sections in an ordinary mode and a plurality of the memory cell arrays to a part of the input and output sections in a test mode. 2. A semiconductor memory device comprising: Memory cell blocks of unit N2 (12a, 12b; 32a-32d), each with memory cell arrays of unit N1, such that N1 and N2 each denote an integer of two or more; and unit (N1 · N2) input and output sections (11a, 11b; 31a-31d) arranged to be associated with each of the memory cell arrays for inputting and outputting signals to and from the memory cell array; marked by a writing circuit (17; 37) arranged for each memory block for inputting information signals to be written into each memory cell array via the respective input and output sections in an ordinary mode, and for writing test signals input to the memory cell arrays of the N1/N3 unit via the input and output sections of the N3 unit respectively into each of the memory cell blocks in the test mode, with N3 being an integer smaller than N1; and a reading circuit (18; 38) arranged for each memory block for outputting information signals read from the memory cell arrays of the unit N1, respectively, via the associated input and output sections in the normal mode, and for outputting a discrimination result for indicating whether signals read from the memory cell arrays of the unit N1/N3, into which the same test signals have been written, are matched with each other, via the same input and output sections of the unit N3 as are used for writing the test signals in the test mode. 3. A semiconductor memory device according to claim 2, characterized in that the write circuit of each of the memory cell blocks includes first switches of the unit N1 (13a, 13b; 33a-33d) connected between the input and output section and the associated memory cell array for switching the ordinary mode to the test mode or vice versa; and second switches of the unit N1 (14a, 14b; 34a-34d) which each connected to a test mode side of each of the first switches of the unit N1 for selecting the memory cell array to be tested. 4. Semiconductor memory device according to claim 2, characterized in that a memory bit width has the value N1 · N2.