DE69215090D1 - Verfahren und System zum Testen eines integrierten Schaltkreises mit Abfragedesign - Google Patents

Verfahren und System zum Testen eines integrierten Schaltkreises mit Abfragedesign

Info

Publication number
DE69215090D1
DE69215090D1 DE69215090T DE69215090T DE69215090D1 DE 69215090 D1 DE69215090 D1 DE 69215090D1 DE 69215090 T DE69215090 T DE 69215090T DE 69215090 T DE69215090 T DE 69215090T DE 69215090 D1 DE69215090 D1 DE 69215090D1
Authority
DE
Germany
Prior art keywords
testing
integrated circuit
query design
query
design
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69215090T
Other languages
English (en)
Other versions
DE69215090T2 (de
Inventor
Ulrich Diebold
Peter Rost
Manfred Schmidt
Otto Torreiter
Rolf Vogt
Klaus Wagner-Drebenstedt
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE69215090D1 publication Critical patent/DE69215090D1/de
Application granted granted Critical
Publication of DE69215090T2 publication Critical patent/DE69215090T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318544—Scanning methods, algorithms and patterns
    • G01R31/318547—Data generators or compressors
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/302—Contactless testing
    • G01R31/305—Contactless testing using electron beams
    • G01R31/307—Contactless testing using electron beams of integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
DE69215090T 1992-08-25 1992-08-25 Verfahren und System zum Testen eines integrierten Schaltkreises mit Abfragedesign Expired - Fee Related DE69215090T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP92114431A EP0584385B1 (de) 1992-08-25 1992-08-25 Verfahren und System zum Testen eines integrierten Schaltkreises mit Abfragedesign

Publications (2)

Publication Number Publication Date
DE69215090D1 true DE69215090D1 (de) 1996-12-12
DE69215090T2 DE69215090T2 (de) 1997-04-30

Family

ID=8209937

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69215090T Expired - Fee Related DE69215090T2 (de) 1992-08-25 1992-08-25 Verfahren und System zum Testen eines integrierten Schaltkreises mit Abfragedesign

Country Status (4)

Country Link
US (1) US5485473A (de)
EP (1) EP0584385B1 (de)
JP (1) JP2823489B2 (de)
DE (1) DE69215090T2 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7137048B2 (en) * 2001-02-02 2006-11-14 Rambus Inc. Method and apparatus for evaluating and optimizing a signaling system
US5574853A (en) * 1994-01-03 1996-11-12 Texas Instruments Incorporated Testing integrated circuit designs on a computer simulation using modified serialized scan patterns
US5726995A (en) * 1994-12-15 1998-03-10 Intel Corporation Method and apparatus for selecting modes of an intergrated circuit
FR2764991B1 (fr) * 1997-06-24 1999-09-03 Sgs Thomson Microelectronics Procede de test fonctionnel et circuit comprenant des moyens de mise en oeuvre du procede
US6484294B1 (en) * 1999-04-23 2002-11-19 Hitachi, Ltd. Semiconductor integrated circuit and method of designing the same
US7490275B2 (en) 2001-02-02 2009-02-10 Rambus Inc. Method and apparatus for evaluating and optimizing a signaling system
US6873939B1 (en) * 2001-02-02 2005-03-29 Rambus Inc. Method and apparatus for evaluating and calibrating a signaling system
US7234092B2 (en) * 2002-06-11 2007-06-19 On-Chip Technologies, Inc. Variable clocked scan test circuitry and method
US7076377B2 (en) * 2003-02-11 2006-07-11 Rambus Inc. Circuit, apparatus and method for capturing a representation of a waveform from a clock-data recovery (CDR) unit
US7009625B2 (en) * 2003-03-11 2006-03-07 Sun Microsystems, Inc. Method of displaying an image of device test data
US9075110B2 (en) * 2010-10-05 2015-07-07 Kyushu Institute Of Technology Fault detection system, acquisition apparatus, fault detection method, program, and non-transitory computer-readable medium
US9465071B2 (en) 2014-03-04 2016-10-11 Mediatek Inc. Method and apparatus for generating featured scan pattern

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4441075A (en) * 1981-07-02 1984-04-03 International Business Machines Corporation Circuit arrangement which permits the testing of each individual chip and interchip connection in a high density packaging structure having a plurality of interconnected chips, without any physical disconnection
US4703260A (en) * 1985-09-23 1987-10-27 International Business Machines Corporation Full chip integrated circuit tester
US4716564A (en) * 1985-11-15 1987-12-29 Tektronix, Inc. Method for test generation
US4745603A (en) * 1986-05-27 1988-05-17 American Telephone And Telegraph Company, At&T Bell Laboratories Code sequence generator for a digital transmission line fault location system
US4996659A (en) * 1986-08-20 1991-02-26 Hitachi, Ltd. Method of diagnosing integrated logic circuit
US4853928A (en) * 1987-08-28 1989-08-01 Hewlett-Packard Company Automatic test generator for logic devices
US5321701A (en) * 1990-12-06 1994-06-14 Teradyne, Inc. Method and apparatus for a minimal memory in-circuit digital tester
US5331570A (en) * 1992-03-27 1994-07-19 Mitsubishi Electric Research Laboratories, Inc. Method for generating test access procedures

Also Published As

Publication number Publication date
JPH06160484A (ja) 1994-06-07
EP0584385A1 (de) 1994-03-02
US5485473A (en) 1996-01-16
DE69215090T2 (de) 1997-04-30
JP2823489B2 (ja) 1998-11-11
EP0584385B1 (de) 1996-11-06

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee