DE69130621T2 - Schneller digitaler Dividierer - Google Patents

Schneller digitaler Dividierer

Info

Publication number
DE69130621T2
DE69130621T2 DE69130621T DE69130621T DE69130621T2 DE 69130621 T2 DE69130621 T2 DE 69130621T2 DE 69130621 T DE69130621 T DE 69130621T DE 69130621 T DE69130621 T DE 69130621T DE 69130621 T2 DE69130621 T2 DE 69130621T2
Authority
DE
Germany
Prior art keywords
digital divider
fast digital
addition operations
multiple addition
performing multiple
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69130621T
Other languages
English (en)
Other versions
DE69130621D1 (de
Inventor
Salim A Shah
Thomas W Lynch
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of DE69130621D1 publication Critical patent/DE69130621D1/de
Application granted granted Critical
Publication of DE69130621T2 publication Critical patent/DE69130621T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/509—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination for multiple operands, e.g. digital integrators
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/535—Dividing only
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/535—Dividing only
    • G06F7/537—Reduction of the number of iteration steps or stages, e.g. using the Sweeny-Robertson-Tocher [SRT] algorithm
    • G06F7/5375—Non restoring calculation, where each digit is either negative, zero or positive, e.g. SRT

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Computing Systems (AREA)
  • Complex Calculations (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Oscillators With Electromechanical Resonators (AREA)
  • Stereophonic System (AREA)
  • Electrotherapy Devices (AREA)
  • Ultra Sonic Daignosis Equipment (AREA)
  • Studio Circuits (AREA)
DE69130621T 1990-04-02 1991-02-20 Schneller digitaler Dividierer Expired - Fee Related DE69130621T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US50535090A 1990-04-02 1990-04-02

Publications (2)

Publication Number Publication Date
DE69130621D1 DE69130621D1 (de) 1999-01-28
DE69130621T2 true DE69130621T2 (de) 1999-09-09

Family

ID=24009973

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69130621T Expired - Fee Related DE69130621T2 (de) 1990-04-02 1991-02-20 Schneller digitaler Dividierer

Country Status (4)

Country Link
EP (1) EP0450751B1 (de)
JP (1) JPH04227536A (de)
AT (1) ATE174697T1 (de)
DE (1) DE69130621T2 (de)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5944772A (en) * 1997-11-07 1999-08-31 International Business Machines Corporation Combined adder and logic unit

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3621218A (en) * 1967-09-29 1971-11-16 Hitachi Ltd High-speed divider utilizing carry save additions
US4084254A (en) * 1977-04-28 1978-04-11 International Business Machines Corporation Divider using carry save adder with nonperforming lookahead
US4320464A (en) * 1980-05-05 1982-03-16 Control Data Corporation Binary divider with carry-save adders
US4503512A (en) * 1982-02-22 1985-03-05 Amdahl Corporation Cellular division circuit

Also Published As

Publication number Publication date
DE69130621D1 (de) 1999-01-28
JPH04227536A (ja) 1992-08-17
EP0450751A3 (en) 1993-05-19
EP0450751A2 (de) 1991-10-09
EP0450751B1 (de) 1998-12-16
ATE174697T1 (de) 1999-01-15

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee