DE69130414D1 - Prozessor und Verfahren zur parallelen Verarbeitung - Google Patents

Prozessor und Verfahren zur parallelen Verarbeitung

Info

Publication number
DE69130414D1
DE69130414D1 DE69130414T DE69130414T DE69130414D1 DE 69130414 D1 DE69130414 D1 DE 69130414D1 DE 69130414 T DE69130414 T DE 69130414T DE 69130414 T DE69130414 T DE 69130414T DE 69130414 D1 DE69130414 D1 DE 69130414D1
Authority
DE
Germany
Prior art keywords
processor
parallel processing
parallel
processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69130414T
Other languages
English (en)
Other versions
DE69130414T2 (de
Inventor
Akira Katsuno
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of DE69130414D1 publication Critical patent/DE69130414D1/de
Application granted granted Critical
Publication of DE69130414T2 publication Critical patent/DE69130414T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G06F9/384—Register renaming
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G06F9/3863—Recovery, e.g. branch miss-prediction, exception handling using multiple copies of the architectural state, e.g. shadow registers

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
DE69130414T 1990-11-20 1991-11-20 Prozessor und Verfahren zur parallelen Verarbeitung Expired - Fee Related DE69130414T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2314607A JPH04184534A (ja) 1990-11-20 1990-11-20 プロセッサ

Publications (2)

Publication Number Publication Date
DE69130414D1 true DE69130414D1 (de) 1998-12-03
DE69130414T2 DE69130414T2 (de) 1999-03-18

Family

ID=18055335

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69130414T Expired - Fee Related DE69130414T2 (de) 1990-11-20 1991-11-20 Prozessor und Verfahren zur parallelen Verarbeitung

Country Status (5)

Country Link
US (1) US5404551A (de)
EP (1) EP0487317B1 (de)
JP (1) JPH04184534A (de)
KR (1) KR960003047B1 (de)
DE (1) DE69130414T2 (de)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4208459A1 (de) * 1992-03-17 1993-09-23 Philips Patentverwaltung Schaltungsanordnung zur verarbeitung von eingabe/ausgabedaten
JPH06242948A (ja) * 1993-02-16 1994-09-02 Fujitsu Ltd パイプライン処理計算機
JP3311462B2 (ja) * 1994-02-23 2002-08-05 富士通株式会社 コンパイル処理装置
US5765016A (en) * 1996-09-12 1998-06-09 Advanced Micro Devices, Inc. Reorder buffer configured to store both speculative and committed register states
JP3599499B2 (ja) * 1996-10-25 2004-12-08 株式会社リコー 中央処理装置
US6343359B1 (en) 1999-05-18 2002-01-29 Ip-First, L.L.C. Result forwarding cache
US7882007B2 (en) * 2000-04-10 2011-02-01 Christopher Keith Platform for market programs and trading programs
US7774246B1 (en) 2000-04-10 2010-08-10 Christopher Keith Automated price setting for paired orders
US8799138B2 (en) * 2000-04-10 2014-08-05 Stikine Technology, Llc Routing control for orders eligible for multiple markets
US7792733B1 (en) 2000-04-10 2010-09-07 Christopher Keith Automated synchronization of orders represented in multiple markets
US7813991B1 (en) 2000-04-10 2010-10-12 Christopher Keith Automated trading negotiation protocols
US8249975B1 (en) 2000-04-10 2012-08-21 Stikine Technology, Llc Automated first look at market events
US7539638B1 (en) 2000-04-10 2009-05-26 Stikine Technology, Llc Representation of order in multiple markets
US8775294B1 (en) 2000-04-10 2014-07-08 Stikine Technology, Llc Automated linked order processing
US8296215B1 (en) * 2000-04-10 2012-10-23 Stikine Technology, Llc Trading system with elfs and umpires
US7908198B1 (en) 2000-04-10 2011-03-15 Stikine Technology, Llc Automated preferences for market participants
US7472087B2 (en) 2000-04-10 2008-12-30 Stikine Technology, Llc Trading program for interacting with market programs on a platform
US6821786B2 (en) * 2002-04-25 2004-11-23 Future Data Inc. Diagnostic test for elemental imbalances
US7580914B2 (en) * 2003-12-24 2009-08-25 Intel Corporation Method and apparatus to improve execution of a stored program

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4430706A (en) * 1980-10-27 1984-02-07 Burroughs Corporation Branch prediction apparatus and method for a data processing system
US4766566A (en) * 1986-08-18 1988-08-23 International Business Machines Corp. Performance enhancement scheme for a RISC type VLSI processor using dual execution units for parallel instruction processing
US5218712A (en) * 1987-07-01 1993-06-08 Digital Equipment Corporation Providing a data processor with a user-mode accessible mode of operations in which the processor performs processing operations without interruption
JPH07120283B2 (ja) * 1988-04-01 1995-12-20 株式会社東芝 マイクロプロセッサ
US5155817A (en) * 1988-04-01 1992-10-13 Kabushiki Kaisha Toshiba Microprocessor
US5006980A (en) * 1988-07-20 1991-04-09 Digital Equipment Corporation Pipelined digital CPU with deadlock resolution
US5019967A (en) * 1988-07-20 1991-05-28 Digital Equipment Corporation Pipeline bubble compression in a computer system
US4980819A (en) * 1988-12-19 1990-12-25 Bull Hn Information Systems Inc. Mechanism for automatically updating multiple unit register file memories in successive cycles for a pipelined processing system
US5155843A (en) * 1990-06-29 1992-10-13 Digital Equipment Corporation Error transition mode for multi-processor system
US5237525A (en) * 1992-06-01 1993-08-17 Motorola, Inc. In a data processor an SRT divider having a negative divisor sticky detection circuit

Also Published As

Publication number Publication date
JPH04184534A (ja) 1992-07-01
KR960003047B1 (ko) 1996-03-04
EP0487317A3 (en) 1993-08-25
US5404551A (en) 1995-04-04
EP0487317B1 (de) 1998-10-28
DE69130414T2 (de) 1999-03-18
EP0487317A2 (de) 1992-05-27
KR920010475A (ko) 1992-06-26

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee