DE69128908T2 - Verfahren zum Durchführen von erlässlichen Befehlen in einem Rechner - Google Patents

Verfahren zum Durchführen von erlässlichen Befehlen in einem Rechner

Info

Publication number
DE69128908T2
DE69128908T2 DE69128908T DE69128908T DE69128908T2 DE 69128908 T2 DE69128908 T2 DE 69128908T2 DE 69128908 T DE69128908 T DE 69128908T DE 69128908 T DE69128908 T DE 69128908T DE 69128908 T2 DE69128908 T2 DE 69128908T2
Authority
DE
Germany
Prior art keywords
executing
computer
mandatory commands
mandatory
commands
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69128908T
Other languages
English (en)
Other versions
DE69128908D1 (de
Inventor
Daryl K Odnert
Dale C Morris
Michael J Mahon
Jerome C Huck
Ruby B Lee
William R Bryg
Stephen G Burger
Vivek S Pendharker
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hewlett Packard Development Co LP
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Application granted granted Critical
Publication of DE69128908D1 publication Critical patent/DE69128908D1/de
Publication of DE69128908T2 publication Critical patent/DE69128908T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G06F9/3865—Recovery, e.g. branch miss-prediction, exception handling using deferred exception handling, e.g. exception flags

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
DE69128908T 1990-10-31 1991-10-22 Verfahren zum Durchführen von erlässlichen Befehlen in einem Rechner Expired - Fee Related DE69128908T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/606,711 US5278985A (en) 1990-10-31 1990-10-31 Software method for implementing dismissible instructions on a computer

Publications (2)

Publication Number Publication Date
DE69128908D1 DE69128908D1 (de) 1998-03-19
DE69128908T2 true DE69128908T2 (de) 1998-07-30

Family

ID=24429144

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69128908T Expired - Fee Related DE69128908T2 (de) 1990-10-31 1991-10-22 Verfahren zum Durchführen von erlässlichen Befehlen in einem Rechner

Country Status (4)

Country Link
US (1) US5278985A (de)
EP (1) EP0484033B1 (de)
JP (1) JP3179536B2 (de)
DE (1) DE69128908T2 (de)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5802337A (en) * 1995-12-29 1998-09-01 Intel Corporation Method and apparatus for executing load instructions speculatively
US5778233A (en) * 1996-10-11 1998-07-07 International Business Machines Corporation Method and apparatus for enabling global compiler optimizations in the presence of exception handlers within a computer program
US6253317B1 (en) * 1997-01-09 2001-06-26 Sun Microsystems, Inc. Method and apparatus for providing and handling traps
US6044221A (en) * 1997-05-09 2000-03-28 Intel Corporation Optimizing code based on resource sensitive hoisting and sinking
US5999736A (en) * 1997-05-09 1999-12-07 Intel Corporation Optimizing code by exploiting speculation and predication with a cost-benefit data flow analysis based on path profiling information
US5915117A (en) * 1997-10-13 1999-06-22 Institute For The Development Of Emerging Architectures, L.L.C. Computer architecture for the deferral of exceptions on speculative instructions
US6170083B1 (en) 1997-11-12 2001-01-02 Intel Corporation Method for performing dynamic optimization of computer code
US6427204B1 (en) 1999-06-25 2002-07-30 International Business Machines Corporation Method for just in-time delivery of instructions in a data processing system
US6425090B1 (en) 1999-06-25 2002-07-23 International Business Machines Corporation Method for just-in-time delivery of load data utilizing alternating time intervals
US6393553B1 (en) 1999-06-25 2002-05-21 International Business Machines Corporation Acknowledgement mechanism for just-in-time delivery of load data
US6397320B1 (en) 1999-06-25 2002-05-28 International Business Machines Corporation Method for just-in-time delivery of load data via cycle of dependency
US6430683B1 (en) * 1999-06-25 2002-08-06 International Business Machines Corporation Processor and method for just-in-time delivery of load data via time dependency field
US6505277B1 (en) 1999-06-25 2003-01-07 International Business Machines Corporation Method for just-in-time delivery of load data by intervening caches
US6829700B2 (en) * 2000-12-29 2004-12-07 Stmicroelectronics, Inc. Circuit and method for supporting misaligned accesses in the presence of speculative load instructions
US7930707B2 (en) * 2006-05-10 2011-04-19 Oracle International Corp. Optimizing code motion with delayed exception handling

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4074353A (en) * 1976-05-24 1978-02-14 Honeywell Information Systems Inc. Trap mechanism for a data processing system
US4080650A (en) * 1976-07-28 1978-03-21 Bell Telephone Laboratories, Incorporated Facilitating return from an on-line debugging program to a target program breakpoint
US4498136A (en) * 1982-12-15 1985-02-05 Ibm Corporation Interrupt processor
US5034880A (en) * 1988-12-22 1991-07-23 Wang Laboratories, Inc. Apparatus and method for executing a conditional branch instruction

Also Published As

Publication number Publication date
EP0484033A3 (en) 1993-06-09
US5278985A (en) 1994-01-11
DE69128908D1 (de) 1998-03-19
JPH04266125A (ja) 1992-09-22
EP0484033B1 (de) 1998-02-11
EP0484033A2 (de) 1992-05-06
JP3179536B2 (ja) 2001-06-25

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: HEWLETT-PACKARD CO. (N.D.GES.D.STAATES DELAWARE),

8327 Change in the person/name/address of the patent owner

Owner name: HEWLETT-PACKARD DEVELOPMENT CO., L.P., HOUSTON, TE

8339 Ceased/non-payment of the annual fee