DE69127056D1 - Verfahren zum Betreiben einer virtuellen Speicheranordnung - Google Patents

Verfahren zum Betreiben einer virtuellen Speicheranordnung

Info

Publication number
DE69127056D1
DE69127056D1 DE69127056T DE69127056T DE69127056D1 DE 69127056 D1 DE69127056 D1 DE 69127056D1 DE 69127056 T DE69127056 T DE 69127056T DE 69127056 T DE69127056 T DE 69127056T DE 69127056 D1 DE69127056 D1 DE 69127056D1
Authority
DE
Germany
Prior art keywords
operating
virtual memory
memory arrangement
arrangement
virtual
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69127056T
Other languages
English (en)
Other versions
DE69127056T2 (de
Inventor
George Allt
John Richard Eaton
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Services Ltd
Original Assignee
Fujitsu Services Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Services Ltd filed Critical Fujitsu Services Ltd
Publication of DE69127056D1 publication Critical patent/DE69127056D1/de
Application granted granted Critical
Publication of DE69127056T2 publication Critical patent/DE69127056T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
    • G06F12/1063—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache the data cache being concurrently virtually addressed

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
DE69127056T 1990-11-13 1991-10-10 Verfahren zum Betreiben einer virtuellen Speicheranordnung Expired - Fee Related DE69127056T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB909024692A GB9024692D0 (en) 1990-11-13 1990-11-13 Virtual memory system

Publications (2)

Publication Number Publication Date
DE69127056D1 true DE69127056D1 (de) 1997-09-04
DE69127056T2 DE69127056T2 (de) 1998-01-29

Family

ID=10685318

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69127056T Expired - Fee Related DE69127056T2 (de) 1990-11-13 1991-10-10 Verfahren zum Betreiben einer virtuellen Speicheranordnung

Country Status (5)

Country Link
EP (1) EP0486154B1 (de)
AU (1) AU8778791A (de)
DE (1) DE69127056T2 (de)
GB (1) GB9024692D0 (de)
ZA (1) ZA918263B (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6336180B1 (en) 1997-04-30 2002-01-01 Canon Kabushiki Kaisha Method, apparatus and system for managing virtual memory with virtual-physical mapping
AUPO648397A0 (en) 1997-04-30 1997-05-22 Canon Information Systems Research Australia Pty Ltd Improvements in multiprocessor architecture operation
US6414687B1 (en) 1997-04-30 2002-07-02 Canon Kabushiki Kaisha Register setting-micro programming system
US6061749A (en) 1997-04-30 2000-05-09 Canon Kabushiki Kaisha Transformation of a first dataword received from a FIFO into an input register and subsequent dataword from the FIFO into a normalized output dataword
US6707463B1 (en) 1997-04-30 2004-03-16 Canon Kabushiki Kaisha Data normalization technique
US6246396B1 (en) 1997-04-30 2001-06-12 Canon Kabushiki Kaisha Cached color conversion method and apparatus
AUPO647997A0 (en) 1997-04-30 1997-05-22 Canon Information Systems Research Australia Pty Ltd Memory controller architecture
US8775740B2 (en) * 2004-08-30 2014-07-08 Texas Instruments Incorporated System and method for high performance, power efficient store buffer forwarding

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4797814A (en) * 1986-05-01 1989-01-10 International Business Machines Corporation Variable address mode cache
JPH01159747A (ja) * 1987-10-02 1989-06-22 Computer Consoles Inc 仮想アドレス方式総合キャッシュおよびその駆動方法

Also Published As

Publication number Publication date
ZA918263B (en) 1992-07-29
EP0486154A2 (de) 1992-05-20
EP0486154A3 (en) 1992-07-08
EP0486154B1 (de) 1997-07-30
AU8778791A (en) 1992-05-14
DE69127056T2 (de) 1998-01-29
GB9024692D0 (en) 1991-01-02

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee