DE69119636D1 - Semiconductor memory circuit - Google Patents

Semiconductor memory circuit

Info

Publication number
DE69119636D1
DE69119636D1 DE69119636T DE69119636T DE69119636D1 DE 69119636 D1 DE69119636 D1 DE 69119636D1 DE 69119636 T DE69119636 T DE 69119636T DE 69119636 T DE69119636 T DE 69119636T DE 69119636 D1 DE69119636 D1 DE 69119636D1
Authority
DE
Germany
Prior art keywords
semiconductor memory
memory circuit
circuit
semiconductor
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69119636T
Other languages
German (de)
Other versions
DE69119636T2 (en
Inventor
Hiroyuki Takahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Application granted granted Critical
Publication of DE69119636D1 publication Critical patent/DE69119636D1/en
Publication of DE69119636T2 publication Critical patent/DE69119636T2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048Data bus control circuits, e.g. precharging, presetting, equalising
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419Read-write [R-W] circuits
DE69119636T 1990-03-27 1991-03-27 Semiconductor memory circuit Expired - Fee Related DE69119636T2 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2078112A JP2550743B2 (en) 1990-03-27 1990-03-27 Semiconductor memory circuit

Publications (2)

Publication Number Publication Date
DE69119636D1 true DE69119636D1 (en) 1996-06-27
DE69119636T2 DE69119636T2 (en) 1997-01-23

Family

ID=13652804

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69119636T Expired - Fee Related DE69119636T2 (en) 1990-03-27 1991-03-27 Semiconductor memory circuit

Country Status (4)

Country Link
US (1) US5199000A (en)
EP (1) EP0449282B1 (en)
JP (1) JP2550743B2 (en)
DE (1) DE69119636T2 (en)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2817490B2 (en) * 1992-01-16 1998-10-30 日本電気株式会社 Static type semiconductor memory reading circuit
JP3181759B2 (en) * 1993-06-10 2001-07-03 富士通株式会社 Semiconductor storage device
JP3068389B2 (en) * 1993-09-29 2000-07-24 日本電気株式会社 Semiconductor storage device
FR2725103B1 (en) * 1994-09-23 1996-12-27 Alcatel Mobile Comm France ENERGY SAVING IN A SYSTEM INCLUDING A PORTABLE RADIOTELEPHONE CONNECTED TO A PERIPHERAL DEVICE
JP3181479B2 (en) * 1994-12-15 2001-07-03 沖電気工業株式会社 Semiconductor storage device
US5907251A (en) * 1996-11-22 1999-05-25 International Business Machines Corp. Low voltage swing capacitive bus driver device
FR2756409B1 (en) * 1996-11-28 1999-01-15 Sgs Thomson Microelectronics MEMORY READING CIRCUIT
ITRM20010298A1 (en) * 2001-05-31 2002-12-02 Micron Technology Inc USER CONTROL INTERFACE WITH PROGRAMMABLE DECODER.
US8448587B2 (en) * 2010-01-26 2013-05-28 Cnh Canada, Ltd. Row unit bounce monitoring system

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5833635B2 (en) * 1979-12-25 1983-07-21 富士通株式会社 semiconductor storage device
JPS613390A (en) * 1984-06-15 1986-01-09 Hitachi Ltd Memory device
US4636988A (en) * 1985-01-07 1987-01-13 Thomson Components-Mostek Corporation CMOS memory arrangement with reduced data line compacitance
JP2598412B2 (en) * 1987-07-10 1997-04-09 株式会社日立製作所 Semiconductor storage device
JPH0766945B2 (en) * 1988-09-06 1995-07-19 株式会社東芝 Static memory

Also Published As

Publication number Publication date
US5199000A (en) 1993-03-30
EP0449282B1 (en) 1996-05-22
DE69119636T2 (en) 1997-01-23
EP0449282A3 (en) 1993-06-16
JPH03278395A (en) 1991-12-10
EP0449282A2 (en) 1991-10-02
JP2550743B2 (en) 1996-11-06

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee