DE69025812D1 - Verfahren und Gerät zur automatischen Durchführung von Prüfmustererzeugung - Google Patents

Verfahren und Gerät zur automatischen Durchführung von Prüfmustererzeugung

Info

Publication number
DE69025812D1
DE69025812D1 DE69025812T DE69025812T DE69025812D1 DE 69025812 D1 DE69025812 D1 DE 69025812D1 DE 69025812 T DE69025812 T DE 69025812T DE 69025812 T DE69025812 T DE 69025812T DE 69025812 D1 DE69025812 D1 DE 69025812D1
Authority
DE
Germany
Prior art keywords
test samples
automatic execution
execution
automatic
samples
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69025812T
Other languages
English (en)
Other versions
DE69025812T2 (de
Inventor
Toshinori Hosokawa
Akira Motohara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Application granted granted Critical
Publication of DE69025812D1 publication Critical patent/DE69025812D1/de
Publication of DE69025812T2 publication Critical patent/DE69025812T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318583—Design for test
    • G01R31/318586—Design for test with partial scan or non-scannable parts
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318544—Scanning methods, algorithms and patterns

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
DE69025812T 1989-07-12 1990-07-11 Verfahren und Gerät zur automatischen Durchführung von Prüfmustererzeugung Expired - Fee Related DE69025812T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18109089 1989-07-12

Publications (2)

Publication Number Publication Date
DE69025812D1 true DE69025812D1 (de) 1996-04-18
DE69025812T2 DE69025812T2 (de) 1996-10-17

Family

ID=16094651

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69025812T Expired - Fee Related DE69025812T2 (de) 1989-07-12 1990-07-11 Verfahren und Gerät zur automatischen Durchführung von Prüfmustererzeugung

Country Status (4)

Country Link
US (1) US5319647A (de)
EP (1) EP0408018B1 (de)
JP (1) JP2616165B2 (de)
DE (1) DE69025812T2 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3265614B2 (ja) * 1991-04-16 2002-03-11 松下電器産業株式会社 検査系列生成方法
US5737341A (en) * 1993-07-01 1998-04-07 Matsushita Electric Industrial Co., Ltd. Method of generating test sequence and apparatus for generating test sequence
US5513118A (en) * 1993-08-25 1996-04-30 Nec Usa, Inc. High level synthesis for partial scan testing
JP3212228B2 (ja) * 1994-10-17 2001-09-25 富士通株式会社 試験プログラム作成装置における試験プログラム自動作成方法
DE69822694T2 (de) * 1997-04-25 2004-08-12 Matsushita Electric Industrial Co., Ltd., Kadoma Verfahren zum prüfgerechten Entwurf, Verfahren zur Prüfsequenzerzeugung und integrierte Halbleiterschaltung
US6651197B1 (en) * 1999-05-20 2003-11-18 Silicon Graphics, Inc. Method for determining the optimum locations for scan latches in a partial-scan IC built in self test system
US7404110B1 (en) 2004-12-01 2008-07-22 Advanced Micro Devices, Inc. Method and system for self-assembling instruction opcodes for a custom random functional test of a microprocessor
US7254509B1 (en) 2004-12-01 2007-08-07 Advanced Micro Devices, Inc. Method and system for testing a memory of a microprocessor
JP4757345B1 (ja) * 2010-03-30 2011-08-24 明和抜型株式会社 面版の位置合わせ装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3713097A (en) * 1971-05-14 1973-01-23 Ibm Test bit pattern generator for pattern recognition machines
US4754215A (en) * 1985-11-06 1988-06-28 Nec Corporation Self-diagnosable integrated circuit device capable of testing sequential circuit elements
US4947395A (en) * 1989-02-10 1990-08-07 Ncr Corporation Bus executed scan testing method and apparatus
US5043986A (en) * 1989-05-18 1991-08-27 At&T Bell Laboratories Method and integrated circuit adapted for partial scan testability

Also Published As

Publication number Publication date
DE69025812T2 (de) 1996-10-17
EP0408018B1 (de) 1996-03-13
EP0408018A3 (en) 1992-01-08
JPH03129438A (ja) 1991-06-03
JP2616165B2 (ja) 1997-06-04
US5319647A (en) 1994-06-07
EP0408018A2 (de) 1991-01-16

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee