DE69014276T2 - Image detector with a large storage capacity per pixel. - Google Patents

Description

The present invention relates to charge transfer photosensitive semiconductor devices intended to form image detectors and comprising at least one row of photodetector points. The invention relates in particular to a new structure of the photodetector points which enables a significant improvement in the storage capacity of these photodetector points.

Fig. 1 schematically shows the conventional architecture of a charge-coupled device (CCD) organized to form a surface image detector. The image detector comprises a photosensitive surface SP divided into a plurality of picture element points or pixels P1 to P16, each of which comprises an element detector or photosensitive element zone D1 to D16. The element detectors are arranged in rows and columns and in the non-limiting example of Fig. 1, only four rows L1 to L4 and C1 to C4 of element detectors have been shown for simplicity; however, the image detector may of course comprise a higher or lower number of rows and columns.

According to a conventional arrangement, the photosensitive surface SP is extended in the direction of the columns C1 to C4 by a charge transfer memory M which forms four additional lines L'1 to L'4. The memory M is in turn followed in a conventional manner by a charge transfer read register RL. The memory M is in a conventional manner connected to the reading register via analog gates Pa1 to Pa4. The memory M is formed in the same way as the sensitive surface SP, ie it is also photosensitive, and in order to prevent it from generating charges under the effect of lighting to which the photosensitive surface SP may be exposed, the entire zone corresponding to the memory M (but also the zone corresponding to the analog gates and the reading register) is shielded in a conventional manner by a screen (not shown) (eg made of aluminium) which is opaque to the useful radiation to which the photosensitive surface SP is exposed.

The operation of such a device is well known: - If the photosensitive surface SP is exposed to useful radiation (in particular light) for a time called the integration time TI, then charges are generated and stored at the level of each pixel. At the end of the integration time TI, for each pixel, the charges stored at that point are transferred to a storage compartment M1 - M16, each storage compartment corresponding to a given pixel P1 to P16.

This transfer is carried out towards the columns C1 at C4: if we take the example of the first column C1, the charges contained in the thirteenth pixel P13 are transferred to the thirteenth memory compartment M13, passing successively through the first, fifth and ninth memory compartments, while the charges initially contained in the first, fifth and ninth pixels P1, P5, P9 are transferred in a similar way to the first and fifth and ninth memory compartments M1, M5 and M9, respectively. At the same time, similar operations are carried out at the level of the columns C2, C3, C4. This is done in a conventional way by applying transfer signals ST1, ST2, ST3 to the element points P1 to P16 and the memory zones M1 to M16. These transfer signals have different phases, so that potential barriers and wells are created that allow the transfer of charges to the columns C1 to C4, ie to a transfer direction ST that carries the charges from the photosensitive surface SP to a compartment CS1 to CS4 of the read register RL. The transfer mode can be in two, three, four or more phases; in the example shown in Fig. 1, this transfer is carried out in three-phase mode, ie each detector point P1 to P16 has three electrodes E1, E2, E3 which follow one another in the direction of the columns C1 to C4 and to which the transfer signals ST1, ST2, ST3 with different phases are applied.

- When the charges have been transferred to a storage zone M1 to M16, a new integration period TI begins and new charges can be generated and stored at the level of each of the element points P1 to P16. During this new integration period TI, all the charges stored in the storage zones M1 to M16 are transferred line by line to the storage compartments CS1 to CS4 of the read register RL: for this purpose, the transfer signals ST1, ST2, ST3 are applied only to the storage zones M1 to M16 in synchronism with the offset control signals SC1, SC2 applied to the read register RL; under the action of the transfer signals, the charges stored in the thirteenth, fourteenth, fifteenth and sixteenth storage zones < these storage zones forming a row L'4 closest to the read register RL) are transferred to the compartments CS1 and CS2, CS3, CS4 of the read register, respectively, while the charges contained in the other storage zones are transferred to storage zones of the row following the read register RL. The offset control signals SC1, SC2 are then applied to the read register, which transfers the charges contained in the compartments CS1 to CS4 to a read circuit CL. Once the read register is emptied, the previous operations are repeated, i.e. the charges contained in the storage zones of the row closest to the read register are transferred to the register; all charges that have accumulated during the previous integration period TI must be evacuated from the storage zones M1 to M16 when the last integration period TI ends.

The structure and operation summarized above are well known and widely used. However, attempts are generally made to refine the characteristics and, in certain applications, efforts are particularly made to increase the charge storage capacity at the level of each pixel and to reduce as much as possible the dark current per pixel for these CCD image detectors.

It is known to cool the CCD image detectors in order to reduce the dark current. However, this method is difficult to implement.

Another method that allows a significant reduction in the dark current of the CCD image detectors is to make them work in a mode called "MPP mode" (multi-pinned phase).

Operation in MPP mode is particularly applicable in the case of buried channel type CCD devices. In this mode, the polarity of the buried channel is inverted at the substrate/insulating layer interface, i.e. generally at the silicon/silicon oxide interface. Inversion at the Si/SiO2 interface results in an accumulation of holes which neutralizes the thermal generation of charges in this region. Since the dark current is essentially a current generated in the interface region, it is greatly reduced in this mode. An explanation of operation in MPP mode can be found in the article "Charge-Coupled Device Pinning Technologies" by James Janesick, Tom Elliott, George Fraschetti, Stewart Collings, published in the journal SPIE, Vol. 1071, Optical Sensors and Electronic Photography (1989)/153.

Fig. 2 illustrates an example of a structure with three phases, ie three transmission signals with different phases, and it illustrates the potentials to be applied for operation in MPP mode. Fig. 2a is to be read together with Fig. 2, it illustrates potential profiles that form potential wells, intended to store the charges generated during the integration period TI; as is usual for charge transfer devices, the positive potentials increase downwards.

In Fig. 2, two pixels P'1, P'2 are shown in section, which with respect to Fig. 1 may correspond for example to a sectional view in the direction of columns C1 to C4 and would show two consecutive pixels such as pixels P1, P5. In the example, pixels P'1, P'2 are formed on a semiconductor substrate S made of silicon, for example p-doped. Substrate S is covered with an electrically insulating layer EI made of SiO₂. Since the MPP structure described is of the three-phase type, electrically insulating layer El carries three electrodes EC1, EC2, EC3 per pixel; these three electrodes are intended to receive transmission signals (not shown) with different phases. Under the insulating layer EI, an n-doped layer is intended in a conventional manner to form a buried channel CE which promotes charge transfer.

In MPP mode, during the integration period TI mentioned above, all the electrodes of a pixel are brought to a negative potential -VTI (generally in the order of -10 volts) to the substrate. Since during the integration period TI all the electrodes EC1 to EC3 are at the same negative potential, doping differences have been introduced into the buried channel CE in such a way that two adjacent pixels in the substrate S are separated by a potential barrier BP1, BP2, BP3, thus forming a storage potential well PP1, PP2 for the charges for each pixel. The height HB represents the difference between the potential wells and the potential barriers and symbolizes the amount of charges that can be stored per potential well, i.e. per pixel.

As already mentioned above, the MPP operating mode is particularly interesting in that it allows a significant reduction of the dark current 10 generated by each pixel. Dark current in case of conventional operation, the so-called "multiphase operation" is of the order of 700.10-12 Amperes/cm2 at ambient temperature, while the dark current Io in MPP operating mode goes up to 25.10-12 Amperes/cm2 at the same ambient temperature.

The disadvantage of the MPP mode, however, is that it significantly reduces the charge storage capacity of the pixel and consequently reduces the usage dynamics of the image detector at high illumination levels.

The object of the invention is to provide a solution to this problem of the dynamic use of CCD image detectors at high illumination levels. It is particularly applicable (but not exclusively) to CCD image detectors operating in the MPP mode described above.

It should be noted that the invention is applicable in the case of CCD sensors having a non-photosensitive space between the pixel rows or even between their columns (for example in the context of a spectroradiometry type application).

According to the definition of claim 1, the invention relates to a photosensitive device with charge transfer with a plurality of photosensitive points or pixels, each pixel having a photosensitive element zone under which a potential well is formed which is intended for storing charges which are generated by exposing the photosensitive element zone to useful radiation, and the surface of the storage potential well is larger than the surface of the photosensitive element zone, the two surfaces being viewed in substantially parallel planes. Specific embodiments are defined in the subclaims.

The features and advantages of the invention will become more apparent from the following description, given by way of example, with reference to the accompanying drawings, in which

- Fig. 1, already described, shows the general organization of a CCD detector of known type;

- the previously described Fig. 2 and 2a illustrating the structure and operating mode of light-sensitive detectors operating in MPP mode;

- Fig. 3 is a sectional view for schematically illustrating an image detector device according to the invention;

- Fig. 3a, 3b, 3c Potential profiles associated with the structure of Fig. 3;

- Fig. 4 illustrating signals to be applied to the device shown in Fig. 3.

Fig. 3 is a schematic sectional view of several successive picture element points or pixels of an image detector of the charge transfer type according to the invention. These pixels PX1, PX2, PX3 are arranged in the direction of columns such as the columns C1 to C4 shown in Fig. 1, i.e. in the transfer direction ST of the charges to a read register (not shown).

To simplify Fig. 3 and the description, the image detector or photosensitive device 10 according to the invention is represented only by the three pixels PX1 to PX3. The photosensitive device comprises a substrate 11 made of silicon, for example p-doped. The substrate 11 has, near its surface, an N-doped layer 12 intended to form a buried channel. Above the buried channel 12, an electrically insulating layer 13, for example made of SiO₂, carries successive electrodes forming a succession of transmission stages ET1, ET2. In the non-limiting example of the description, each stage ET1, ET2 comprises four electrodes E1, E2, E3, E4 intended to receive transmission signals (not shown) with different phases, whereby the mode of charge transfer takes place in four phases.

Each pixel PX1, PX2, PX3 comprises a photosensitive element zone Z1, Z2, Z3 and a potential well PI1, PI2, PI3 (Fig. 3a) designed to store charges generated by the pixel during the integration period.

According to a feature of the invention, the storage potential wells PI1, PI2, PI3 have a larger surface than the surface of the light-sensitive element zones Z1, Z2, Z3, which results in an increase in the storage capacity for charges at the level of each pixel compared to the prior art.

To this end, in the non-limiting example of the description, each pixel has two successive transfer stages capable of forming a single potential well, while the surface of the photosensitive element zone of the same pixel has, in this example, a surface limited to that of a single electrode, namely the electrode E2 of the stage ET2 in the non-limiting example described.

Of course, each pixel PX to PX3 could have more than two stages ET1, ET2; it is important that the surface of the storage potential well PI1, P12, PI3 of a pixel is larger than the surface of the photosensitive element zone Z1 to Z3 of the same pixel, these two surfaces being of course considered in two substantially parallel planes. With two or more transfer stages for a pixel, the result of the invention can also be obtained with operation in a mode with two, three, five or more phases.

In the described non-limiting example, in which all electrodes E1 to E4 are transparent to the useful radiation (shown by arrows RU) in such a way that their entire surface is photosensitive, a an opaque screen 20 is placed between them and all the electrodes, with the exception of one electrode per pixel, which represents the photosensitive element zone of the pixel, namely the electrode E2 in the non-limiting example described. For this purpose, the screen has openings 21 whose dimensions are well below the dimensions of the potential wells PI1 to PI3 and whose surface determines the surface of the photosensitive zones.

The following are given, by way of non-limiting example, orders of magnitude of the dimensions of photosensitive element zones Z1 to Z3 and of the storage potential wells PI1 to PI3: if it is assumed that these wells and zones have the same dimension, for example in the direction of the pixel rows, i.e. in a direction perpendicular to the plane of the figure, then the photosensitive zones Z1 to Z3 can have a dimension d1 of the order of 20 micrometers in a direction parallel to the plane of the figure, and the potential wells PI1 to PI3 can have a dimension d2 of the order of 150 micrometers.

In the case of operation in MPP mode, in which all the electrodes E1 to E4 of all the stages ET1, ET2 are brought to a negative potential with respect to the substrate 11 during the integration period TI, the potential wells PI1 to PI3 are formed between potential barriers BP1, BP2, BP3, BP4 (see Fig. 2a) obtained by localized doping differences of the semiconductor material in the buried channel 12, namely by N-doped zones 14; these zones 14 therefore have the same conductivity type as the buried channel 12, which is N-doped, but they are less heavily doped than the latter.

According to a characteristic of the invention, the zones 14 are not necessarily implemented in the ratio of one to one transmission stage ET1, ET2 as in the prior art, since one and the same pixel can have several consecutive stages; consequently, the zones 14 required for operation in MPP mode specific doses are only realized under the two electrodes that delimit the pixel.

Fig. 3a illustrates potential profiles created in the structure of Fig. 3 during the charge integration period TI; as is common in charge transfer devices, the positive potentials increase downward. Figs. 3a and 3b illustrate potential profiles created in the structure of Fig. 3 in a charge transfer phase.

The storage potential wells PI1 to PI3 shown in Fig. 3a are those that exist under each pixel during the integration period TI, i.e. the period during which the photosensitive element surfaces Z1 to Z3 are illuminated. In the image detector according to the invention, the charges generated by the illumination of the photosensitive element zone Z1 to Z3 of each pixel PX1 to PX3 are stored in this pixel until the end of the integration period TI, since the potential well in which the charges are stored has a larger dimension than the photosensitive element zone Z1 to Z3 that generated these charges. After the integration period TI, a first or second and third charge quantity Q1, Q2, Q3 is stored in the first or second and third potential well PI1, PI2, PI3; These charges are intended for transmission in the direction shown by the arrow marked ST.

It should be noted that the charge quantities Q1 to Q3 are each divided during transfer into as many parts or packets as there are stages ET1, ET2 to form a pixel, regardless of the number of phases applied to each stage. For example, in the case shown in Fig. 3, where each pixel PX1 to PX3 is formed from two stages ET1, ET2, each charge quantity Q1, Q2 and Q3 is divided into two parts A, B, as shown in Fig. 3b, as soon as the transfer signals ST1 to ST4 are applied to the electrodes E1 to E4.

Fig. 4 is a timing chart showing the phase relationship between the transmission signals ST1 to ST4 applied to the electrodes E1 to E4 of Fig. 3.

Lines a, b, c and d of Fig. 4 show the transmission signals ST1 and ST2, ST3, ST4 respectively.

A time t0 corresponds to the beginning of the integration period TI. During the entire duration of the integration period TI, all the transmission signals ST1 to ST4 are in the low state or in the 0 state, which in the case of operation in MPP mode corresponds to a negative voltage of the order of less than 10 volts with respect to a reference voltage VR; the reference voltage VR is the voltage of the substrate 11. During operation in MPP mode, it is thus possible to reverse the polarity of the buried channel 12 shown in Fig. 3.

A time t1 corresponds to the end of the integration period TI and the beginning of a phase of transfer of quantities of charge Q1, Q2, Q3 for evacuating these charges outside the photosensitive zone. At time t1, the first and second transfer signals ST1, ST2 are in state 0, while the third and fourth transfer signals ST3, ST4 have passed into state 1, which, in the non-limiting example described, corresponds essentially to a potential of 8 positive volts with respect to the reference voltage VR.

At time t2, the first transmission signal ST1 goes into state 1, which corresponds to a potential of the order of 8 volts with respect to the reference voltage VR; the second transmission signal ST2 is in state 0, the third and fourth transmission signals ST3, ST4 are in state 1.

At time t3, the first transmission signal ST1 is in state 1; the second transmission signal ST2 is in state 0; the third transmission signal ST3 is from State 1 to state 0; the fourth transmission signal ST4 is in state 1.

At time t4, the first transmission signal ST1 is in state 1; the second transmission signal ST2 transitions from state 0 to state 1; the third transmission signal is in state 0; the fourth transmission signal is in state 1.

At time t5, the first and second transmission signals ST1, ST2 are in state 1; the third transmission signal ST3 is in state 0; the fourth transmission signal ST4 transitions from state 1 to state 0.

At time t6, the first and second transmission signals ST1, ST2 are in state 1; the third transmission signal ST3 transitions from state 0 to state 1; the fourth transmission signal ST4 is in state 0.

At time t7, the first transmission signal ST1 changes from state 1 to state 0; the second and third transmission signals ST2, ST3 are in state 1; the fourth transmission signal ST4 is in state 0.

At time t8, the first transmission signal ST1 is in state 0; the second and third transmission signals ST2, ST3 are in state 1; the fourth transmission signal ST4 changes to state 1.

At time t9, the first transmission signal ST1 is in state 0; the second transmission signal ST2 changes from state 1 to state 0; the third and fourth transmission signals ST3, ST4 are in state 1.

At time t10, the first transmission signal ST1 changes from state 0 to state 1; the second transmission signal ST2 is in state 0; the third transmission signal ST3 is in state 1; the fourth transmission signal ST4 is in state 1.

This shows a complete cycle of the first transmission signal, whose cycle time TC lies, for example, between time t2 and time t10; the four transmission signals are square-wave signals with cyclic voltage at the same cycle time.

Referring again to Fig. 3, 3a, 3b, 3c, the application of the transfer signals ST1, ST2, ST3, ST4 to the electrodes E1, E2, E3, E4 modifies the potential wells that were present under these different electrodes during the integration period TI. Indeed, from the time t1 at which these transfer signals are applied to the electrodes, each pixel PX1 to PX3 has two potential wells PIA, PIB (shown in Fig. 3b) each having a quantity of charge QA and QB, respectively, the sum of which forms the quantity of charge Q1 to Q3 that was stored in a single storage potential well PI1, PI2, PI3 (shown in Fig. 3a) until the end of the integration period TI; In the example of Fig. 3b, the potential wells PIA, PIB are formed for each pixel under the third and fourth electrode of each stage ET1, ET2.

Fig. 3c illustrates the profiles of potentials obtained at the time t3 as shown in Fig. 4. With respect to the time t1, the first transmission signal is in state 1, while the third transmission signal ST3 has passed to state 0: it follows that the potential wells PIA, PIB have shifted in the transmission direction ST and are located under the fourth and first electrode of each stage ET1, ET2.

Any modification of the phase of the transmission signals ST1 to ST4 therefore results in a shift of the charges QA, QB in the transmission direction, as is conventional.

Of course, the transfer of these charges into a read register must make it possible to recover the entire quantity of charge Q1, Q2, Q3 which, after initial storage in a pixel, has been separated into the same potential well, possibly into as many packets QA, QB as there are stages ET1, ET2 to form a pixel. When the charges QA, QB initially contained in the first pixel PX1, for example, are transferred into a read register (not shown), the stage of the read register which first received the charge QA, for example, maintains the same position so that subsequent transfer pulses transfer the charge QB to the same stage and produce the sum QA + QB to obtain the initial charge Q1.

This need to perform an accumulation of charge packets depending on the number of levels contained in a pixel represents an additional complication which is negligible compared to the considerable increase in the charge storage capacity obtained.

Claims (4)

1. A charge transfer photosensitive device, comprising: - a plurality of light-sensitive points or pixels (PX1, PX2, PX3) arranged in rows (L1, L2, L3, L4) and columns (C1, C2, C3, C4), - a storage device (M) with charge transfer and - a read register (RL) with charge transfer, wherein each pixel has several electrodes (E1, E2, E3, E4) which follow one another along a transfer direction (ST) of the charges in the direction of the columns so that a sequence of transfer stages (ET1, ET2) is formed , wherein a part of the electrodes of each pixel forms a photosensitive element zone, under which a storage potential well (PI1, PI2, PI3) is formed, which is intended to store the charges generated by exposing the photosensitive element zone to a useful radiation during an integration period, where the surface of the storage potential well is larger than the surface of the photosensitive element zone, wherein the electrodes of each pixel form at least two transfer stages under which the storage potential well is formed, whereby the storage potential wells (PI1 to PI3) in the transmission direction (ST) are only delimited between two potential barriers, regardless of the number of transmission stages (ET1, ET2) that the pixel (PX1 to PX3) has. 2. Photosensitive device according to claim 1, in which the transfer of the charges is ensured by means of a buried channel (12), characterized in that each storage potential well (PI1 to PI3) is delimited between two potential barriers obtained by a difference in the doping (N-) in the buried channel (12). 3. Photosensitive device according to one of the preceding claims, characterized in that it is of the buried channel (12) type and operates in a mode called "MMP mode" in which the polarity of the buried channel (12) is reversed during irradiation by the useful radiation. 4. Photosensitive device according to one of the preceding claims, characterized in that it has a screen (20) that is opaque to the useful radiation, the screen (20) being placed between the useful radiation and at least one pixel (PX1 to PX3), the screen (20) having at least one opening (21) whose surface delimits the surface of the photosensitive element zone (Z1 to Z3) of the pixel.