DE68923683T2 - Control device and method for a liquid crystal display panel. - Google Patents

Description

BACKGROUND OF THE INVENTION Field of the invention

The invention relates generally to devices and methods for driving liquid crystal display panels, and more particularly to an apparatus and method for driving an active matrix liquid crystal color display panel using a low frequency clock signal. More particularly, the invention relates to a structure of a line drive memory circuit for a liquid crystal display panel and a driving method thereof for applying a color signal to a row of signal electrodes in the liquid crystal display panel in response to a high speed line sequential system.

Description of the relevant state of the art

Display devices using liquid crystals can be driven with low voltage and, accordingly, are used for applications requiring low power consumption. As an example of such applications, there are liquid crystal display panels having a matrix arrangement of liquid crystal pixels which are to be driven in sequence by applying a video signal to each liquid crystal pixel to display an image.

Fig. 1A to 1C show schematically a structure of a conventional active matrix liquid crystal color display panel.

Referring to Fig. 1A, pixels P₁₁, P₁₂, ... P1(N-1), P1N, ... PM(N-1), PMN (pixels are generically denoted by the reference symbol P) are arranged in a matrix of M rows and N columns of a display panel (i.e., an active matrix liquid crystal color display panel) 1 to construct a display screen (hereinafter referred to as a screen) 2. A thin film transistor (hereinafter referred to as a TFT) not shown is provided at each pixel P in one-to-one correspondence.

As shown in Fig. 1B, each pixel P comprises a TFT Tr, a capacitor CA and a liquid crystal element LE. The gate of the TFT Tr is connected to a scanning line (i.e., a gate line) 1x, and its source is connected to a source line 1y. The capacitor GA collects the signals transmitted from the source line 1y through the TFT Tr. The liquid crystal element LE transmits or blocks light depending on the signal potential from the source line 1y or the capacitor CA. A color filter (not shown) is arranged on the liquid crystal element LE, and a desired color display is obtained by the color filter depending on the transmission/blocking state of the liquid crystal element LE.

The gates of the TFTs of the respective rows are connected to the corresponding scanning lines (gate lines) 1x1, 1x2, 1x3, ... 1xm. A scanning driver 4 activates the scanning lines 1x1 to 1xM in sequence. This causes the screen 2 to be scanned in the vertical direction.

The sources of the TFTS of the respective columns are connected to the corresponding source lines 1y1, 1y2, ..., 1yn. A color signal is output from a source driver 3 (in Fig. 1C shown) to each of the source lines 1y1 to 1y. A plurality of pixels P connected in common to a source line 1y form a pixel line b1, r2, r3, b4, ..., r(N-1), gN (a pixel line is generically indicated by the reference symbol Y), with an order of colors being given from left to right on the screen 2. The letters b, r, g represent pixels having colors corresponding to the color video signals B (blue), R (red), G (green), and the numbers appended to these letters, 1, 2, 3, etc., represent the arrangement order.

In the following description, a scanning line is generally indicated by reference numerals 1x, and a source line is generally indicated by reference numerals 1y.

Referring to Fig. 1C, the source driver circuit (hereinafter referred to as source driver) 3 comprises: a shift register 3a having output terminals Q1 to QN corresponding to the number N of source lines 1y; an analog switch 3b having switching elements S1 to SN provided so as to correspond to the output terminals Q1 to QN with a unique relationship; and an analog sample-and-hold circuit 3c.

The shift register 3a shifts the output signal in the direction from the output terminal Q1 to the output terminal QN to turn on the switching elements S1 to SN one by one in the direction indicated by the arrow y, whereby the color video signals B, R, G applied to the switching elements S1 to SN are applied in sequence to the analog sample-hold circuit 3c.

The analog sample-and-hold circuit 3c holds the color video signals recorded in one horizontal period for the screen 2. signals B, R, G and outputs these signals individually to the corresponding pixel rows Y via the source lines 1y in the subsequent horizontal period, and at the same time it receives the color signals B, R, G for the subsequent horizontal period in parallel.

However, in the structure described above, when the number of pixels in the screen 2 is increased to increase the size of the panel 1 and to improve the image quality, and when the frequency of the clock pulses GK is increased due to the requirement of high-speed scanning, the linearity of the analog sample-and-hold circuit 3c deteriorates and the power consumption increases, making it difficult to meet these conditions.

Under these circumstances, it has been proposed to use a method in which the screen 2 is divided into blocks and the divided blocks having a plurality of pixel columns are driven by respective source drivers in order to achieve high-speed scanning by means of low-speed source drivers and to reduce the size of the driving circuit. Such a method is disclosed, for example, in document EP-A-0 287 055.

Fig. 2 is a block diagram showing an electrical structure of a conventional liquid crystal driving circuit. The liquid crystal driving circuit 21 comprises a plurality of source drivers 5 to 8 arranged in peripheral areas of the panel 2 and a plurality of line memory circuits 9 to 14 which supply color video signals R, G, B to the respective source drivers 5 to 8. Each of the line memory circuits 9 to 14 includes an A/D converter, a memory, a multiplexer, a latch, a D/A converter and the like, as will be described later.

The screen 2 is constructed according to a multiplex matrix system. More specifically, the source lines 1y are alternately connected to the upper and lower source drivers 5, 7; 6, 8, respectively, and each pixel row Y is divided in the horizontal direction into two regions, namely a first half region (driven by the source drivers 5, 6) and a second half region (driven by the source drivers 7, 8). As a result, the screen 2 consists of four regions, namely the regions corresponding to the pixel rows Y1 to Y4, respectively.

The plurality of source drivers 5 to 8 are arranged around the screen in correspondence with the divided pixel lines Y1 to Y4. The color video signals R, G, and B applied through the lines 11, 12, 13 are processed by sequential operations such as analog-to-digital (A/D) conversion, writing, reading, latching, and digital-to-analog (D/A) conversion in the six line memory circuits 9 to 14. Thereafter, the processed signals are supplied according to an alternating signal sampling operation of the source drivers 5 to 8.

However, in the liquid crystal driving circuit 21 described above, two line memories are required for each of the color signals R, G, B, which means that a total of six line memories are required. In addition, for each line memory, as shown in the block diagram of Fig. 3, the circuit must comprise an amplifying circuit 9a for the input color signal (e.g., B), an A/D converter 9b for digitally converting the input color signal, a buffer circuit 9c, a memory 9d for storing the digital data from the buffer circuit 9c, a write address generating circuit 9e and a read address generating circuit 9f for generating read/write addresses for the memory 9d, a multiplexer 9h for switching read/write operations for the memory 9d at a predetermined timing. Position and for supplying the write address or the read address to the memory 9d, a latch stage 9i for temporarily storing the data read out from the memory 9d, a D/A converter 9j for converting the temporarily stored digital data into an analog signal and a buffer 9k present between the source driver and the D/A converter 9j. The switching between the write/read operations of the memory 9d is carried out under the control of a line memory control circuit 99 via the address multiplexer. In addition, the line memory control circuit 99 carries out the operation control (such as the control of the timing of the address generation) of the write address generation circuit 9e and the read address generation circuit 9f.

In addition to these line memory circuits 9 to 14 having the various components, delay circuits and the like, not shown, must be further provided in order to overcome mismatch between the input order of the color signals B, R, G to the line memory circuits 9 to 14 and the color order (of the color filter arrangement) b, r, g, etc. in a pixel line Y given in the screen 2, and to change the order of the data read out from the memory 9d depending on the order of the arrangement in the pixel lines. More specifically, also in the multiplex matrix system, each of the source drivers 5 to 8 has the same structure as shown in Fig. 1C, and receives and holds a color signal for one color in turn in response to a clock signal CK. On the other hand, each of the line memories 9 to 14 transmits signals to the two source drivers. The signal from a line memory to the source driver (5 or 6) of the first half-range and that to the source driver (7 or 8) of the second half-range are read alternately, and the order in which the signals from the respective line memories 9 to 14 supplied from the source drivers 5 to 8 coincide with the color order of the pixel lines y. Thus, for the output range of each of the line memories 9 to 14, a delay circuit or the like is required. Accordingly, each of the source drivers 5 to 8 controls only 1/4 of the columns (160 columns in the figure) of the screen 2. As a result, each of the line memories 9 to 14 can drive the liquid crystal display panel at an operating speed which is 1/2 of that in the case of one memory for each color, and each of the source drivers 5 to 8 can drive the display panel at an operating speed which is 1/4 of that in the case of one memory for each color. However, the structure of the device is large in size and complicated.

SUMMARY OF THE INVENTION

The invention attempts to provide a liquid crystal driver circuit with simplified circuit construction and excellent linearity.

The invention also seeks to provide a circuit for operating a liquid crystal display panel in the multiplex matrix system which does not require the application of a high frequency clock signal.

The invention also seeks to provide a circuit for operating a liquid crystal display panel according to a high-speed line sequence system with color filters in a triangular arrangement in response to a low-frequency clock signal with low power consumption.

The invention also seeks to provide a method for operating a liquid crystal display panel according to a multiplex matrix system to a low frequency clock signal at low energy consumption.

The invention also seeks to provide a method of operating a liquid crystal display panel according to a multiplex matrix system with color filters in a triangular arrangement using a low frequency clock signal.

A circuit for operating a liquid crystal color display panel according to an embodiment of the invention includes a plurality of driver means for driving source lines and a plurality of first memory means for storing a plurality of color video signals R, G, B to be displayed and for outputting the color video signals R, G, B in an order required by the driver means.

According to one aspect of the invention, there is provided a method of operating a display device as claimed in claim 1.

According to another aspect of the invention, there is provided an apparatus according to claim 6.

Each of the first storage means includes: a plurality of analog-to-digital (A/D) converters for A/D-converting each color of the video signals within one horizontal period; switching means for supplying the digitized data according to a writing order; at least one pair of second storage means for storing the digitized data and outputting the same; data reading means for dividing the data within one horizontal period into two areas, ie, a first half area and a second half area, and for alternately reading the divided data for the first half area and the second half area from the second memory device; a plurality of latches for temporarily storing the data read from the data reading device; and digital-to-analog (D/A) converters for D/A conversion of the data supplied by the latches.

A line memory circuit for driving a liquid crystal display panel according to another embodiment of the invention includes: means for supplying two kinds of video signals from a video signal for one horizontal period simultaneously to a first gate line (a scanning line) and to a second gate line which forms a pair with the first gate line (the scanning line); and means for storing the two kinds of video signals thus formed by dividing these signals into at least eight groups corresponding to the first gate line, the second gate line, odd-numbered source lines and even-numbered source lines for the first and second gate lines, the source lines of the first half region, and the source lines of the second half region.

This line memory circuit further includes: means for alternately reading pixel data to be transferred from the memory means to the source lines of the first half region for the first gate line and pixel data to be transferred to the source lines of the second half region, and reading out the pixel data for the second gate line in the same order as for the first gate line after the reading operation for the first line is completed; means for transferring the pixel data supplied from the reading means to the source drivers provided for the at least two groups of the first half region and the second half region of the source lines, respectively; and signal lines, which are arranged so that they do not intersect each other to transmit the output signals of the source drivers to the source lines of the liquid crystal display panel.

In the circuit for driving a liquid crystal display panel according to an embodiment of the invention, color video signals R, G, B for one horizontal period in the first storage means are converted into digital data by the A/D converter. The converted digital data are output to the second storage means of the pair by the switching means depending on the writing order, and these data are stored together in the second storage means.

At the same time, the content stored in the second storage means for the previous horizontal period is divided into the first half and the second half of a horizontal period, and these divisions are alternately read by the data reading means. The read data are converted into the color video signals R, G, B as analog signals by the D/A converters and input to the associated driving means. The plurality of driving means appropriately take in the data of the first half and that of the second half as they are alternately output, and drive the liquid crystal elements.

In a line memory circuit according to another embodiment of the invention, two kinds of signals are simultaneously supplied to the first line and the second line of the gate lines (the scanning lines) from the video signals for one horizontal period, and the data of the two kinds of video signals thus supplied are written into the memory device. Then, the video signal data corresponding to one gate line is stored for 1/2 horizontal period is read from the memory device and sent to the source drivers acting as pixel drive devices. Thus, the liquid crystal display panel can be operated according to the high-speed line sequence system.

In addition, when the pixel data is read out from the memory device, the video signal data corresponding to a gate line is divided into a first half and a second half of the source lines, and the divided data is read out alternately, whereby the video signals can be supplied alternately to the source drivers driving the first half and the second half of the source lines. This makes it possible to reduce the clock frequency that determines the operating speed of the source drivers to 1/2 and to operate the source drivers according to the high-speed line sequence system at the same clock frequency as the conventional system. Accordingly, the linear characteristic of the source drivers can be improved and the power consumption can be reduced.

Although there is a positional difference corresponding to 1.5 pixels between the even-numbered gate lines and odd-numbered gate lines in triangular array color filters, it is possible to cope with this difference by shifting the phase of the sampling clock by 1.5 clocks when converting an analog video signal into a digital signal.

The foregoing and other features, aspects and advantages of the invention will become more apparent from the following detailed description of the invention when taken in conjunction with the accompanying drawings.

SHORT DESCRIPTION OF THE DRAWINGS

Fig. 1 is a block diagram showing a structure of a conventional liquid crystal display panel.

Fig. 2 is a block diagram showing the electrical structure of a conventional liquid crystal driving circuit.

Fig. 3 is a block diagram showing the electrical structure of a line memory circuit for one color in the conventional circuit.

Fig. 4 is a block diagram showing the electrical structure of a liquid crystal driving circuit according to an embodiment of the invention.

Fig. 5 is a block diagram showing the electrical structure of a line memory circuit used in the embodiment.

Fig. 6 is a timing chart for explaining the reading operation in the embodiment.

Fig. 7 is a timing chart for explaining the writing operation in the embodiment.

Fig. 8 is an illustration showing a scan order and polarity reversals for gate lines in a dual speed line sequence system.

Fig. 9 shows a scanning order and polarity reversals for gate lines in an interlaced system.

Fig. 10 shows a scanning order and polarity reversals for gate lines in a high-speed line sequence system.

Fig. 11 shows schematically the structure of a liquid crystal display panel.

Fig. 12 shows an arrangement of color filters in the liquid crystal display panel of Fig. 11.

Fig. 13 is a diagram showing an example of the structure of source drivers for driving the liquid crystal display panel shown in Fig. 12.

Fig. 14 shows a specific structure of a line memory circuit that produces video signals for the high-speed line sequence system according to another embodiment of the invention.

Fig. 15 is a block diagram showing a structure for providing two sets of video signal data for odd-numbered gate lines and even-numbered gate lines from video signals for one horizontal period in the line memory circuit shown in Fig. 14.

Fig. 16 is a timing diagram showing the operation of the A/D converters and the 3-state buffers shown in Fig. 15.

Fig. 17 is a block diagram showing an example of a specific construction of a data signal train converting circuit in the line memory circuit shown in Fig. 14.

Fig. 18 is a timing chart illustrating the operation of the data signal train converting circuit shown in Fig. 17.

Fig. 19A is a timing chart showing the process of writing data trains obtained from the data train conversion circuit into memories.

Fig. 19B is a schematic diagram showing the process of writing data into each memory and showing writing areas in each memory.

Fig. 20A is a timing chart showing the process of reading data from the memories shown in Fig. 14.

Fig. 20B is a schematic diagram showing an operation according to the timing diagram of Fig. 20A for the areas of the memories.

Fig. 21 shows an example of the structure of the polarity changeover circuit in the line memory circuit shown in Fig. 14.

Fig. 22 is a timing chart showing the operation of the polarity changing circuit shown in Fig. 21.

Fig. 23 is a block diagram showing an example of a structure for converting a data signal train in the line memory circuit shown in Fig. 14 into video signals for the three colors R, G, B.

Fig. 24 is a timing chart showing the operation of the latches and the D/A converters shown in Fig. 23 and also showing the process of sampling the output signals of the D/A converters by the Fig. 14 shows the source driver.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Fig. 4 schematically shows the electrical structure of a liquid crystal driver circuit according to an embodiment of the invention. According to Fig. 4, the liquid crystal driver circuit 31 comprises: source drivers 33, 34, 35, 36 for driving a display panel 32 which is divided into, for example, four areas, and a pair of line memory circuits 37, 38 for supplying color video signals R, G, B to the source drivers 33 to 36.

The source drivers 33 to 36 are arranged on the periphery of the display panel 32 in the upper left, upper right, lower left and lower right parts in the figure.

The line memory circuit 37 supplies the color video signals R, G; B to the source drivers 33, 35, while the line memory circuit 38 supplies the color video signals R, G, B to the source drivers 35, 36.

Deviating from the prior art, the liquid crystal driver circuit 31 is constructed using only two line memory circuits 37, 38.

Fig. 4 shows, as an example, a case where the number of pixel columns (source lines) in the horizontal direction of the screen (horizontal direction in the figure) of the display panel (hereinafter referred to simply as panel) 32 is 640. The 640 pixel columns are driven by the pair of line memory circuits 37, 38, and accordingly, the number of pixel columns for one line memory circuit is 320. The panel 32 is thus composed of a multiplex matrix system as in the case of Fig. 2.

The upper left, first source driver 33 and the upper right, third source driver 35 are connected together to lines l1b, l1r, l1g as output lines of the first line memory circuit 37. The lower left, second source driver 34 and the lower right, fourth source driver 36 are connected together to lines l2b, l2r, l2g as output lines of the second line memory circuit 38.

These four source drivers 33 to 36 are supplied with clock signals. For example, the upper left first source driver 33 is supplied with a clock signal of 0° phase. The lower left second source driver 34 is supplied with one of 90° phase; the upper right third source driver 35 is supplied with one of 180° phase; and the lower right fourth source driver 36 is supplied with one of 270° phase. Accordingly, the above-mentioned source drivers 33 to 36 are activated in a circular manner in the order of the upper left driver, the lower left driver, the upper right driver and the lower right driver so that the video signals B, R, G are received by the corresponding line memory circuits 37, 38.

The panel 32 has a predetermined color order of BGRB, etc., from the left side of the screen, for example, by means of color filters not shown. Accordingly, the color arrangement set for each pixel row Y from the left side of the screen is b1, g2, r3, b4, ... g638, r639, b640. These 640 pixel columns b1 to b640 are divided into two halves in the center of the screen, and the pixel columns b1, g2, r3, ..., b319, 9320 in the first half of a horizontal scanning period for the screen are alternately driven by the first and second source drivers 33 and 34 on the left side of the screen, while the pixel columns r321, b322, g323, ..., r639, b640 in the second half are alternately controlled by the third and fourth source drivers 35 and 36 on the right side of the screen.

The pair of line memory circuits 37, 38 supplying the color video signals R, G, B to the first to fourth source drivers 33 to 36 differ only in the order of the color signals supplied to the corresponding source drivers and also in the clock phases for activation, and they operate in the same manner. The pickup of each signal for the three colors among the color video signals R, B, G in the first to fourth source drivers 33 to 36 is carried out with a delay of one clock and is round tripped for three clocks. The operation of this embodiment will be described as typifying the first line memory circuit 37 in the upper part of the screen and the driver circuit 31a shown by the dashed lines in Fig. 4 and constituted by the first and third source drivers 33 and 35.

The order of supplying the respective color signals (R, B, G), that is, the order of reading out the signals from the first line memory circuit 37 to the first and third source drivers 33 and 35 on the top of the screen in the driver circuit 31a must agree with the order of color arrangement of the pixel line y as determined by the color images as stated above. Accordingly, as shown, the color signals are supplied in the order of BRGB etc. to the left first source driver 33, and the color signals are supplied in the order of RGBR etc. to the right third source driver 35. On the other hand, the order of receiving the video signals (R, G, B) by the first line memory 37 is the same as that for the first source driver 33, that is, the order is the order BRG, etc., and this order is used as the order for writing the color signals into the first line memory circuit 37 as will be described later.

Fig. 5 is a block diagram showing the electrical structure of the line memory circuit 37 of this embodiment. The first and second line memory circuits 37 and 38 shown in Fig. 4 have the same structure. Hereinafter, only the first line memory circuit 37 will be described as typical. The letters b, r, g as appended to the reference numerals correspond to the color signals B, R, G, and in the case of general indications, only the reference numerals without the letters b, r, g are used.

The first line memory circuit 37 comprises: A/D converters 39b, 39r, 39g for A/D converting the respective color video signals B, R, G supplied through line amplifiers not shown; and 3-state buffers 40b, 40r, 40g for on/off controlling the digital data of the respective colors supplied from the A/D converters 39 depending on the write order for the memories, which will be described later.

The line memory circuit 37 further comprises: 3-state buffers 41, 42 for supplying write data supplied from the above-mentioned 3-state buffer 40 to a pair of memories 43, 44 when a write operation is carried out; and a data multiplexer 45 for supplying the color signals Bd, Rd, Gd in the memory on the read side within the pair of memories 43, 44 capable of read/write to a subsequent data latch circuit 46.

The line memory circuit 37 further includes the following:

Data latches 46b, 46r, 46g for latching data for the color signals as supplied from the data multiplexer 45 according to the reading order; D/A converters 47b, 47r, 47g for converting the data latched by the data latch 46 into analog signals; amplifiers (not shown) which amplify the levels of the analog-converted color signals B, R, G and supply the output signals to the source drivers (as shown in Fig. 4); and an address multiplexer 49 for selectively instructing a read/write operation and addressing the memories 43, 44 with a predetermined synchronization.

The line memory circuit 37 further includes: a write address generating circuit 50 for generating a write address when writing data (in a write cycle), a read address generating circuit 51 for generating an address for the memory to be read when reading data (in a read cycle), and a line memory control circuit 52 for controlling the operation of these circuit blocks.

The operation of the line memory circuit 37 will be described below. The number of horizontal pixels as related to the line memory circuit 37 is assumed to be N. Digital data corresponding to one pixel line is written into a memory 43 or 44. Meanwhile, the line memory circuit 37 supplies color video signals to both the first-half source driver 33 and the second-half source driver 35. If the memory area of a memory 43 or 44 is assumed to correspond to one pixel line, it is necessary to divide the memory area into a first half and a second half. The boundary address between the first and second halves is obtained as follows:

2x ≥ N/2

That means

x ≥ log2 (N/2).

This value x is provisionally referred to as a switch bit. The write address generating circuit 50 generates a write address A1 for writing the digital data of the first half period (H/2) of a horizontal period (H) in the order of 0, 1, ..., j (j < 2x) depending on the switch bit, and generates a write address A2 for writing the digital data of the second half period (H/2) in the order of 2x + 0, 2x + 1, ..., 2x + j. Thus, the data to be transferred to the source driver 33 for the first half is written in the area H with the addresses 0 to j > 2x of the memory 43 or 44, while the data to be supplied to the source driver 35 for the second half is written in the memory area A2 with the addresses 2x and higher. As a result, if it is assumed that the address has (x + 1) bits, switching between the areas A1 and A2 can be easily carried out by entering "0" in the address area A1 for the first half and entering "1" in the address area A2 for the second half.

Since each pixel line Y includes 640 pixel columns, N = 320. In this case, x = 8. Accordingly, the first half of the data of the 320 color signals B, R, G of the first horizontal period HI is written into the addresses A1 (0 to j (j = 159)) of one of the memories 43, 44 of the pair, for example, the memory 43, and the second half of the same is written into the addresses A2 (28 to 28 + j) of the same memory 43. This writing operation is carried out according to the writing addresses generated by the writing address generating circuit controlled by the line memory control circuit 52.

In the next horizontal period H2, the read/write operations of the memories 43, 44 are switched. Accordingly, the data is written into the addresses A1, A2 of the other memory 44, and at the same time, the data written into the memory 43 in the previous horizontal period H1 is read out based on the read addresses specified by the read address generation circuit 51. The generation of the addresses and the switching of the operations are carried out by the line memory control circuit 52.

More specifically, the line memory control circuit 52 switches the read/write operations of the pair of memories 43, 44 for every horizontal period H, and controls the address generating circuits 50, 51 and the multiplexer 49 so that a write address and a read address are generated while the above-mentioned first half/second half switching bit X (X = 8 in this embodiment) is alternately switched for the write address generating circuit 50 and the read address generating circuit 51.

Accordingly, as for the reading of the data, the data for the first and second halves are alternately read out in one horizontal period Hx from the memory (e.g., the memory 43) in which the data was written in the previous horizontal period HX-1 while the address changes according to 0, 28, 1, 28 + 1, 2, etc., and in the next horizontal period HX+1, the writing/reading for the two memories 43 and 44 is switched so that the data for the first and second halves are alternately read out from the other memory 44 while the address changes according to 0, 28, 1, 28 + 1, etc. The writing of data is carried out in the same manner.

Accordingly, the read/write operations for the memories 43, 44 for the invention are switched for every horizontal period H, and while data is being read out from one memory, data is written into the other memory. Further, one horizontal period H is divided into first and second halves, and write/read operations are performed for these first and second halves alternately. This structure simplifies the electrical structure of the liquid crystal driving circuit 31 and enables high-speed operation.

To achieve the above-described operation, the first line memory circuit 37 has the three-state write buffers 41, 42 on the write input side of the memory pair 43, 44 and the data multiplexer 45 on the read output side, so that the read/write operations of data are controlled by the line memory control circuit 52.

For example, if it is assumed that the memory 43 is in a write cycle and the memory 44 is in a read cycle in a horizontal period H1, the second write buffer 42 connected to the second data line 12 is turned on, and the digital data for the color video signals B, R, G obtained by A/D conversion are applied to the data line 12 and input to the memory 43. On the other hand, the second input terminal a2 of the data multiplexer 45 assumes high impedance with respect to the data line 12, so that input of the above-mentioned digital data is prohibited.

On the other hand, the first write buffer 41 connected to the first data line 11 assumes high impedance, and the first input terminal a1 of the data multiplexer 45 is turned on. As a result, the digital data from the A/D Converter 39 does not pass the data onto the data line l1. Instead, the data read from the memory 44 is passed onto the first data line l1 and passed via the data multiplexer 45 to the data latch stage 46b, 46r, 46g of the next stage.

In the next horizontal period H2, the read/write cycles of the memories 43, 44 are reversed so that a read operation is performed in the memory 43 and a write operation is performed in the memory 44. In this case, the output of the first write buffer 41 and the second input terminal a2 of the data multiplexer 45 are turned on, and the output of the second write buffer 42 and the first input terminal a2 of the data multiplexer 45 become high impedance. The digital data from the A/D converter 39 is supplied through the first data line 12 and written into the memory 44. On the other hand, data is read out from the memory 43 and input from the second data line 12 to the data latches 46b, 46r, 46g of the next stage through the data multiplexer 45. In this way, write/read operations for the digital data for the color video signals B, R, G are carried out alternately.

The A/D converters 39b, 39r, 39g and the D/A converters 46b, 46r, 46g used in the line memory circuit 37 (similarly in the line memory circuit 38 in Fig. 4) convert data in response to the clock signal φc applied to the line memory control circuit 52. The A/D converters 39b, 39r, 39g convert the analog color video signals B, R, G into digital data and output them. The D/A converters 47b, 47r, 47g convert the digital data of the color video signals B, R, G supplied from the latches 46b, 46r, 46g into analog signals and supply them to the lines l1b, l1r, l1g.

Since the respective color signals B, R, G are simultaneously converted into digital data by the A/D converter circuits 39b, 39r, 39g, the 3-state buffers 40b, 40r, 40g of the next stage are sequentially activated one by one depending on the writing order, so that the digital data for one color is output in order and written into the memory 43 or 44. The digital data read out from the memory 43 or 44 passing through the data multiplexer 45 are input in parallel to the data latches 46b, 46r, 46g, and they are divided into three colors in response to the latch pulses applied at a timing corresponding to the reading order.

With respect to a color, since a data is latched once for three clocks, the same data is converted into analog data for three clocks, whereby three-times oversampling occurs. As a result of the three-times oversampling, the frequency band for the sampling clock can be made to be outside the video signal frequency band, which makes it easier to design filters for eliminating sampling clock noise provided in video signal amplifiers (not shown) in the input stage of each A/D converter 39 (39b, 39r, 39g) and in the stage following each D/A converter 47 (47b, 47r, 47g).

Since the order of supplying the color video signals B, R, G to the first and third source drivers 33 and 35 arranged on the left and right sides of the liquid crystal driving circuit 31a on the top of the screen 32 coincides with the color order specified by the color filters (not shown) provided on the screen, as stated above, the left first source driver 33 has the order B-R-G and the right second source driver 35 has the order R-G-B.

On the other hand, the order in which the color video signals R, G, B are taken in by the line memory circuit 37 is the same as the acceptance order B-R-G of the first source driver 33 as described later, and this order is the order for the writing operation into the memory 43 or 44. However, the order of outputting the taken in color video signals to the pixel line Y (the source drivers 33, 35) is the order b1-r321,-r3-g323-g5-b325-b7, etc. when the output of data to the first source driver 33 for the first half and that to the second source driver 35 for the second half are alternately performed as shown in Fig. 4. In this case, it is necessary to output the color video signals for the same color for the second half and the first half sequentially from the line memory circuit 37, and accordingly there is not enough time for switching the color video signals.

Therefore, as for the reading order, data is read alternately in the order of the second source driver 35 and the first source driver 33, which means the reverse order with respect to the first and second halves in data reading. Accordingly, the order of reading data is r312-b1-g323-r3-b325-g5, etc., and the respective source drivers 33, 35 can pick up the color signals of the same color at equal intervals, providing sufficient time for switching the color video signals B, R, G in the line memory circuit 37. As a result, the first line memory circuit 37 takes the color video signals in the order BRG into the first and second memories 43 and 44 and reads the data from the first and second memories 43, 44 in the order R(second half)-B(first half)-G(second half)-R(first half)-B(second half)-G(first half) etc. to store the color video signals B, R, G in that order as required for the first and second source drivers 33 and 35.

6 and 7 are timing charts showing the operation of the line memory circuit according to this embodiment. As described above, the screen 2 according to this embodiment is divided into upper and lower regions which are controlled by the first and second line memory circuits 37 and 38, respectively. These two line memory circuits 37 and 38 operate in the same manner, and these circuits differ from each other only in the phases of the supplied operation clock signals and the acceptance order for the respective colors in the source drivers. Therefore, Figs. 6 and 7 show the timing for the read operation and that for the write operation only for the first memory circuit 37.

Fig. 6(a) represents the timing of a clock signal ΦC applied to the first line memory circuit 37, and Fig. 6(b) represents the timing of a source driver clock signal applied to the first and third source drivers 33 and 35.

Fig. 6(c) represents the waveform of a read address signal supplied from the read address generating circuit 51 shown in Fig. 5. As described above, according to this embodiment, the data of the color video signals R, G, B for one horizontal period are divided into first and second halves, and the data of the second half is stored in the memory 43 or 44 from address 28, that is, from address 256, while the data for the first half is stored therein from address 0. Accordingly, the read address generating circuit 51 alternately supplies addresses under in which the data for the first and second halves are stored. In reading the data, since the data of the same color is read out at equal intervals as in the order of R(second half)-B(first half)-G(second half)-R(first half)-B(second half)-G(first half), the data latch signals φR, φG, φB corresponding to the respective colors in the color video signals R, G, B are separately supplied from the line memory control circuit 52 to the data latches 46b, 46r, 46g for each pulse of the clock signal φC. In response to the latch pulses, the data read in accordance with the read address signal shown in Fig. 6(c) is latched by the corresponding data latch 46. At this time, since the first pixel column r321 in the second half of the screen 2 as shown in Fig. 4 corresponds to the color video signal R(256) and the first pixel column b1 in the first half corresponds to the color video signal B(0), the data latch signals φB, φR, φG are supplied in the order of B data latch signal φB - R data latch signal φR - G data latch signal φG. Fig. 6(d), (f), (h) represent the timing of the data latch signals thus prepared corresponding to the respective colors.

Fig. 6(e) represents the timing at which a data of the color video signal B is sequentially latched in response to the B data latch signal ΦB, and Fig. 6(g) represents the timing at which a data of the color video signal R is sequentially latched. Similarly, Fig. 6(i) represents the timing at which data of the color video signal G is sequentially latched. The latch signals ΦB, ΦR, ΦG for latching the data of the respective colors have a rotation of three clocks for the clock signal ΦC shown in Fig. 6(a), and a data is latched once for three clocks into a latch circuit 46b, 46r, 46g.

The buffered data are supplied to the D/A converters 47b, 47r and 47g of the following stage, where they are converted into analog signals. Then, these analog signals are sequentially received by the first and second source drivers 33 and 35 at the timing of the source driver clock φS and sampled and held there. Thereafter, the respective color signals are supplied from the source drivers 33, 35 to the source lines at a predetermined timing (e.g., at the timing of the horizontal synchronizing signal), and the pixel p connected to the activated scanning line (gate line) lx is lit.

Fig. 7(a) represents, similarly to Fig. 6(a), the timing of the clock signal ΦC applied to the first line memory circuit 37. In synchronization with the timing of the clock signal ΦC, the respective A/D converters 39b, 39r, 39g convert the color video signals R, G, B into digital data in the same order as the arrangement order of pixels (the color order). Fig. 7(b), (c), (d) represent the timing of output signals corresponding to the digitized data for the respective color. The time t0 defines the time of the start of a horizontal period.

Fig. 7(e) represents the timing of a write address signal output from the write address generating circuit 50. The address multiplexer 49 supplies write signals ΨB, ΨR, ΨG for the respective colors in synchronization with the clock signal ΦC as shown in Figs. 7(f), (h), (j). In response to the B data write signal ΨB in Fig. 7(f), the 3-state buffer 40b outputs the data for the color video signal B as digitized by the A/D converter 39b as shown in Fig. 7(g). In response to the R data write signal ΨR in Fig. 7(h), the 3-state buffer 40r outputs the data for the color video signal R as shown in Fig. 7(h). it has been digitized by the A/D converter 30r as shown in Fig. 7(i). The same applies to the output of the data to the color video signal G as shown in Figs. 7(j) and (k). Since the respective data write signals ΨB, ΨR, ΨG are generated at a cycle of three clocks (ΦC) to determine the timing for sequentially writing the color video signals R, G, B, the data for the respective colors are sequentially written in the order of the color video signals BRGB, etc., starting from the first address of the memory 43 or 44, simultaneously with the start of one horizontal period.

In the above-described configuration, since the source drivers 33 to 36 are activated in the order of the source driver 33, the source driver 34, the source driver 35, and the source driver 36, the respective source drivers 33 to 36 can operate in response to a low-frequency clock signal φS. In addition, only one pair of line memory circuits 37, 38 is provided, and the data of the respective color signals are latched and outputted at a frequency equal to 1/3 of that of the line memory clock φC in the respective line memory circuits 37, 38, making it possible to operate a liquid crystal display panel at high speed using low-speed source drivers. Furthermore, since there is only a pair of line memory circuits and each line memory circuit can process three colors, it is possible to obtain a small and inexpensive liquid crystal driving circuit with a simple structure.

In the structure described above, it is assumed that the same arrangement of colors applies to the respective scanning lines (gate lines) and that the color filters (pixels) are arranged in a matrix of rows and columns. As for the scanning order of the scanning lines (gate lines), it has not been specifically determined whether it is an interlaced system or a non-interlaced system. In the structure described above, since the scanning order is determined by the scanning drivers 4 (as shown in Fig. 1A), either system is applicable to the structure of the line memory circuits 37, 38.

However, when the color filters are arranged in a triangular arrangement, it is necessary to consider the timing of reading data and the like depending on the scanning system for the scanning lines. This point is specifically described below.

In general, AC driving is required to drive liquid crystals. Therefore, the polarity of the signal applied to the liquid crystal is inverted every predetermined cycle. More specifically, when a liquid crystal display panel is to be driven, the gate lines (i.e., the signal lines for selecting a line to which the liquid crystal elements in the liquid crystal display panel are connected; scanning lines) are scanned in order so that all the gate lines can be scanned within one field. In this case, the polarity of the video signal is inverted every one horizontal period depending on the scanning of the gate lines. When there are so many gate lines that they cannot be scanned within the period of a field, two systems are conventionally used to scan all the gate lines in the given period of a frame, which are called the double-line scanning system and the interlaced system.

In the double-speed line sequence system, pairs of two gate lines are scanned, and these pairs of gate lines are alternately selected for each field, as shown in Fig. 8. In field A, the pair of gate lines g1, g2 are scanned simultaneously, and the pair of gate lines g3, g4 are also scanned simultaneously. Similarly, the pair of gate lines g5, g6 are scanned, and the pair of gate lines g7, g8 are scanned. In this case, a positive signal is applied to each liquid crystal pixel in the gate lines g1, g2; a negative signal is applied to each liquid crystal pixel in the gate lines g3, g4; and a positive signal is applied to each liquid crystal pixel in the gate lines g5, g6. In the next field B, the gate lines g2, g3 forming a pair are scanned and the gate lines g4, g5 forming a pair are scanned. In the field B, a negative signal is applied to each liquid crystal pixel of the gate lines g2, g3 and a positive signal is applied to each liquid crystal pixel of the gate lines g4, g5. Similarly, in the fields G, D, E, pairs of gate lines are selected and scanned sequentially. In this double-speed line sequence system, the polarity of the signal for the liquid crystal pixels connected to a gate line is switched every two fields (i.e., for one frame). One horizontal period (1H) is the period in which all the liquid crystal pixels connected to a gate line are driven, and this period corresponds to one horizontal scanning period of a display device in an ordinary scanning system. One field corresponds to a frequency of 60 Hz. This double-speed line sequence system shows excellent response to moving images because all gate lines can be scanned within the period of one field.

However, in the above-described double-speed line sequential system, respective pairs of two gate lines, i.e., odd-numbered gate lines and even-numbered gate lines, are simultaneously scanned, and accordingly, when the color filters of a color liquid crystal display panel have a triangular arrangement, correction for the triangular arrangement cannot be carried out, resulting in deterioration of the horizontal resolution.

The above-mentioned triangular arrangement is a color arrangement of the color filters in which different colors, i.e. color filters for R, G, B, are arranged at the respective vertices of an arbitrary equilateral triangle consisting of pixels of the liquid crystal display panel.

In the interlaced system, the gate lines are alternately scanned in each field, and all the gate lines are scanned within two fields. More specifically, in this interlaced system, the odd-numbered gate lines g1, g3, g5, g7 are scanned in field A, and the even-numbered gate lines g2, g4, g6, g8 are scanned in the next field B. When the color filters of the liquid crystal display panel are arranged in a triangular arrangement and the signal electrodes for applying a signal potential to the pixels are arranged in a zigzag shape, the odd-numbered gate lines and the even-numbered gate lines are shifted from each other by 1.5 pixels. Accordingly, the odd-numbered gate lines and the even-numbered gate lines cannot be driven at the same timing. However, in this system with interlaced scanning, only odd-numbered gate lines or even-numbered gate lines are scanned in each field, which is why if the temporal control position is set with a period difference of 1.5 pixels for each field, a correction can be made with regard to the triangular arrangement of the colour filters, which makes it possible to improve the horizontal resolution.

However, in the interlaced system, since only half of all gate lines are scanned in a field, the gate lines that are not scanned retain the image information supplied in the previous field until it is renewed with the scanning in the next field. Accordingly, since each pixel maintains image information for one frame, the response to moving images is degraded.

Furthermore, in both the double-speed progressive scan system and the interlaced scan system, the cycle of polarity reversal of signals required for AC operation of a liquid crystal display panel corresponds to two frames, i.e., 15 Hz, as shown in Figs. 8 and 9, and accordingly flickering tends to occur.

The above-described disadvantages of the double-speed scanning system and the interlaced system in terms of correction of the triangular arrangement, response to moving pictures and occurrence of flicker can be overcome in the high-speed scanning system. In this high-speed scanning system, two gate lines are scanned in one horizontal period. However, the two gate lines are not scanned simultaneously, but one of the gate lines is scanned in a half period of a horizontal period and the other gate line is scanned in the remaining half period, thereby scanning the two gate lines within one horizontal period. Accordingly, the high-speed scanning system differs from the high-speed scanning system. from the double-speed line sequence system in this respect.

More specifically, as shown in Fig. 10, in the high-speed scanning system, the pair of gate lines g1 and g2 are selected, and the gate line g1 is scanned in the first half period of a horizontal period and the gate line g2 is scanned in the remaining half period. Since the gate lines are scanned individually in this high-speed scanning system, correction for a triangular arrangement can be made, and since two gate lines are scanned within one horizontal period, all the gate lines can be scanned within one field period, which improves the response to moving pictures. In addition, since the gate lines are scanned individually, it is possible to invert the polarity of the video signal when the scanning in 1/2 horizontal periods, i.e., the scanning of one gate line, is completed. Accordingly, the cycle for polarity inversion of the signal required for AC driving of the liquid crystal display panel can be made to coincide with one frame, i.e., 30 Hz, to achieve high-speed operation, making it possible to suppress flickering in the liquid crystal display panel. Accordingly, as shown in Fig. 10, the polarity of the signal for the gate lines can be inverted for each of the frames A, B, C, D, E, and the polarity inversion cycle of the signal corresponds to one frame.

However, in this high-speed line-sequencing system, it is necessary to drive the liquid crystal display panel by supplying a video signal corresponding to the pixels connected to a gate line to the source drivers within half a horizontal period.

More specifically, the applied video signal cannot be supplied to the source drivers as it is, and it is necessary to perform processing such as time compression of a video signal for one horizontal period into a video signal for half a horizontal period.

In addition, in order to correct a triangular arrangement of color images, the timing of applying a video signal to the odd-numbered gate lines must be shifted from the timing of the even-numbered gate lines by 1.5 pixel periods, and accordingly, even if video signals for two gate lines are generated from a video signal for one gate line, these two types of video signals cannot be directly applied to the source drivers and some signal processing is required. Furthermore, since one gate line is scanned within a half horizontal period and the signal potential for this gate line must be transmitted to each liquid crystal pixel, it is necessary to drive the source drivers which transmit the signal potential to each pixel at a clock frequency twice that of the conventional sequential system or the interlaced system, resulting in deterioration of the linear characteristic or increase in power consumption.

Therefore, a line memory circuit for driving a liquid crystal display panel according to another embodiment of the invention has the structure described below.

First, before explaining the specific structure of this embodiment, the operation of the line memory circuit for driving a liquid crystal display panel according to the invention will be described theoretically. Color filters of the liquid crystal display panel have a triangular arrangement and the signal electrodes of the liquid crystal pixels are arranged in a zigzag shape in the liquid crystal display panel, the arrangements of the pixels of the odd-numbered gate lines and those of the even-numbered gate lines are shifted by 1.5 pixels. Accordingly, when a video signal for one horizontal period is subjected to analog-to-digital (A/D) conversion in such a manner as to generate digital video signals for two gate lines, it is necessary to set a difference corresponding to 1.5 pixels between the clock timing for carrying out the A/D conversion for odd-numbered gate lines and that for even-numbered lines. In practice, since the video signal is A/D-converted for one clock for one pixel of the liquid crystal display panel, a difference of 1.5 clocks is generated between the clocks applied to the A/D converter for the odd-numbered gate lines and those applied to the even-numbered gate lines.

The respective color signals R (red), G (green) and B (blue) of the video signals are divided for two gate lines, i.e., an odd-numbered line and an even-numbered line, and A/D conversion is carried out in parallel for one horizontal period for the respective two lines while maintaining the above-mentioned time difference corresponding to 1.5 clocks.

The 3-state buffers are provided in the stage following the A/D converters, which correspond to the respective colors R, G, B of the video signals. The operation timings of these 3-state buffers are controlled, whereby the data output timings for the respective colors R, G, B, as supplied from the A/D converters are controlled so that the video data for the respective colors R, G, B are output at in the same arrangement order as the order of the color filters in the liquid crystal display panel.

By the above operation, video data for one horizontal period are formed with respect to odd-numbered gate lines as well as those with respect to even-numbered gate lines. The data signal train corresponding to one horizontal period thus formed is divided into the two groups for the odd-numbered gate lines and the even-numbered gate lines, and accordingly, in a structure in which video data is directly written into the two memories, i.e., one for the odd-numbered gate lines and the other for the even-numbered gate lines, a data read operation is carried out in 1/2 horizontal period from only one of the memories, resulting in deterioration of the memory access efficiency and making it necessary to read the video data from the memory in half the time required for writing data (time corresponding to one horizontal period). Therefore, in order to efficiently access the memories not only when writing data but also when reading data, data train conversion is carried out before video signal data is written into the memories.

More specifically, the data trains divided into the two groups of odd-numbered lines and even-numbered lines are further divided into video data corresponding to odd-numbered source lines and video data corresponding to even-numbered source lines. The video signals supplied to the source drivers become pixel data trains in which the video data for the pixels of the odd-numbered source lines and those of the even-numbered source lines appear alternately. Accordingly, When the above-mentioned data train conversion is carried out, the reading of video data for odd-numbered source lines and the reading of video data for even-numbered source lines are alternately carried out. In view of this fact, the two memories are provided, that is, one for storing the video data for the odd-numbered source lines and the other for storing the video data for the even-numbered source lines. In the case of a structure for the above-mentioned data train conversion, the data reading operations from these two memories are alternately carried out. Accordingly, the memory access efficiency is improved and it is possible to read out data simultaneously with the writing of data.

The video signals could not be used to drive a liquid crystal display panel to display an image if they were not continuously processed. For this reason, another pair of memories is provided, i.e., one memory for storing the video data for the odd-numbered source lines and another for storing the video data for the even-numbered source lines, as described above, so that a write operation is performed in one pair among the pairs of memories while a read operation is performed in the other pair among the pairs. Accordingly, for these two pairs of memories, a switchover operation between the write operation and the read operation is performed for one horizontal period. By means of this switchover structure, while video data is being written into one pair of the pairs of memories, data is read out from the other pair of memories, whereby the video signals can be continuously processed.

As for the addresses for writing a data signal train into the memories, assuming that the number of pixels for one horizontal period (ie the number of liquid crystal pixels connected to one gate line) is N, in order to facilitate the separation and switching between the first and second halves of the source lines for the same memory and between the odd and even gate lines, the switching bit X for switching between the first and second halves of the source lines is as follows:

X ≥ log2 (N/4),

and for the bit Y for switching between the even and odd gate lines:

Y = X + 1.

As for the video data after the conversion of the data trains, the video data for the odd-numbered gate lines and those for the even-numbered gate lines are alternately written into the corresponding memories. More specifically, in the conversion of the data trains, the data for the odd-numbered gate lines and those for the even-numbered gate lines are alternately written with respect to, for example, odd-numbered source lines, and similarly, the video data for the odd-numbered gate lines and those for the even-numbered lines are alternately written with respect to the even-numbered source lines. Accordingly, the bit Y for switching between the odd-numbered and even-numbered gate lines is alternately reset and set repeatedly every 1/2 horizontal period, so that the write address is incremented by one. As a result, the area of the memory into which the video data for the odd-numbered gate lines are written for 1/2 horizontal period corresponds to the reset value of the switch bit y, and the video data for the even-numbered gate lines are stored at the address for which the switch bit Y is set, i.e., in the second half area of the memory.

The switching bit X for switching between the first and second halves of the respective source lines is reset and set for the first half of the horizontal period and for the second half of the horizontal period. Accordingly, the writing positions in the memory may be different depending on the first half of the horizontal period and the second half thereof. As a result, the memory area of a pair of memories is divided into eight areas, i.e., areas corresponding to the respective two gate lines, areas corresponding to the first and second halves of the odd-numbered source lines, and areas corresponding to the first and second halves of the even-numbered source lines, and the corresponding video data is written into each of these eight areas.

When reading the video data from the memories, the order of arrangement of the read data must match the order of the video signals supplied to the source drivers, and accordingly the toggle bit X for switching between the first and second half of the source lines is repeatedly and alternately reset and set for every 1/2 horizontal period so that the read address is incremented by one. The toggle bit Y for switching between the odd and even gate lines is reset or set for the first 1/2 horizontal period and the second 1/2 horizontal period depending on the field. More specifically, in a certain field, the toggle bit Y is reset in the first 1/2 horizontal period and set in the second 1/2 horizontal period. In another field, the toggle bit Y is set in the first 1/2 horizontal period and reset in the second 1/2 horizontal period.

The video data read out from the memories depending on the above-mentioned read address is a digital signal, and on the other hand, the video signal applied to the source drivers is in the form of an analog signal. Accordingly, the read video data must be converted from a digital signal to an analog signal, and prior to this D/A conversion, digital polarity switching is carried out.

In a digital polarity switching stage, an inversion or non-inversion of the bit value of the data is carried out in response to a polarity switching signal, and the video signal passed through the digital polarity switching stage is converted from digital to analog data, whereby the polarity of the video signal changes.

In the prior art, the structure for switching the video signal polarity is such that an analog video signal is input to an inverting amplifier and a non-inverting amplifier, and the output signals of the respective amplifiers are switched and outputted using an analog switch in response to the polarity switching signal. Accordingly, in the case of the conventional structure for switching the polarity in analog form, three components, namely the inverting amplifier, the non-inverting amplifier and the analog switch, are required, which increases the circuit size.

On the other hand, in the digital polarity switching circuit according to the embodiment of the invention, the inversion and non-inversion of the bit value of the video data can be carried out selectively in response to the switching signal by using an exclusive-OR gate (Ex-OR) or the like, and only one amplifier is required after the D/A conversion. Accordingly, it is not necessary to provide two kinds of amplifiers such as an inverting amplifier and a non-inverting amplifier, and in the case of constructing a digital processing by A/D converting the video signal, such a polarity switching circuit can be realized with a small number of components.

The video data that has passed through the digital polarity switching stage must be subjected to D/A conversion to obtain video signals for the respective colors R, G, B. For this purpose, the latches in the pre-stage to the D/A converters are operated depending on the color order of the read data signal train, whereby the data for the respective colors are fed to the corresponding D/A converters, in which the data are converted into respective analog video data. The analog video signals thus obtained are video signals for the high-speed line sequence system, and a video signal corresponding to a gate line can be fed to the source driver within 1/2 horizontal period.

In the construction described above, the analog video signals for the three colors R, B, G are converted into digital video data using the A/D converters provided for the corresponding three colors, and after the video signals for the three colors R, G, B are converted into a data signal train, a desired digital processing is performed on the signal train by setting the operating timings of the 3-state buffers in the subsequent stage to the respective A/D converters. Thereafter, the data signal train is separated into digital video data for the respective colors by setting the operating timings of the latch stages, which are supplied to the D/A converters provided for the respective colors R, G, B, so that this digital video data is converted into analog video signals.

With the structure described above, the digital processing circuit sections between the 3-state buffers and the latches can process the data of the respective colors together without dividing this data, which makes it possible to reduce the number of components.

Next, another embodiment of the invention will be described in detail with reference to the drawings. This embodiment is related to a case as shown in Fig. 11, in which the number of pixels of a liquid crystal display panel 147 in the horizontal direction is 640 in total for all three colors R, G, B, the number of pixels in the vertical direction is 480, and the arrangement of color filters in this liquid crystal display panel is a triangular arrangement as shown in Fig. 12. Further, four source drivers 143, 144, 145 and 146 are provided for driving the liquid crystal display panel 147, corresponding to four groups consisting of an odd-numbered source line group, an even-numbered source line group and groups for the first and second half regions of the respective source lines in the liquid crystal display panel.

More specifically, as shown in Fig. 11, the source driver 143 applies video signals to the odd-numbered source lines of the first half region, and the source driver 144 applies video signals to the odd-numbered source lines of the second half region. The source driver 145 applies video signals to the even-numbered source lines of the first half region, and the source driver 146 applies video signals to the even-numbered source lines of the second half region. In this case, the number of source lines is 640 as stated above, and the respective source lines are consecutively are designated by the numbers 1 to 640 in the same manner as in Fig. 4. In addition, in the structure of Fig. 11, the letters B, G, R on the liquid crystal display panel 147 represent the colors of the pixels, and the numbers indicated under the respective letters B, G, B represent the numbers assigned to the source lines. The scanning drivers for driving the gate lines are not shown in the figure.

As described above, the number of source lines of the liquid crystal display panel 147 is 640, which corresponds to the number of pixels in the horizontal direction, and the number of gate lines is 480, which corresponds to the number of pixels in the vertical direction. The source lines are arranged in a zigzag shape in the liquid crystal display panel 147 as shown in Fig. 12 because the color filters are arranged in a triangular shape, and one source line drives liquid crystal pixels of the same color in the respective gate lines.

In addition, as clearly shown in Fig. 11, the signal output terminals of the source drivers 143 to 146 are connected to the source lines of the liquid crystal display panel 147 in such a manner that the connections do not overlap each other.

As clearly shown in Fig. 12, the arrangement of the pixels 148 of the liquid crystal display panel 147 is offset by 1.5 pixels between odd-numbered gate lines and even-numbered gate lines.

Each of the source drivers 143 to 146 for driving the respective source lines of the liquid crystal display panel 147 has the structure shown in Fig. 13.

Referring to Fig. 13, a source driver comprises: a shift register 149 activated in response to a start pulse φ3 to shift a selection enable signal from the output terminal by one in response to a clock φ4; analog switches 150-1 to 150-m for transmitting respective video signals V1 to V3 in response to the select enable signals from the shift register 149; and an analog sample-hold circuit 151 for sampling and holding the video signals applied through the analog switches 150 (150-1 to 150-m) and supplying the held video signals to the corresponding source lines when the signals for all the source lines are latched.

The analog switches 150 are sequentially turned on in response to the selection enable signals from the shift register 149 to transmit the corresponding video signals to the analog sample-and-hold circuit 151. The video signals V1 to V3 correspond to the video signals of the respective colors R, G, B, and these video signals for the respective colors are transmitted in parallel. Accordingly, in this structure, when the video signal R is transmitted to the analog sample-and-hold circuit 151, the video signals of the remaining colors are not transmitted. Accordingly, only the video signal for one color, i.e., the video signal for one pixel, is transmitted to the analog sample-and-hold circuit 151 via the analog switch 150 at a time.

Further, the shift register 149 has a structure of 160 stages (m = 160) to drive 1/4 of the 640 pixels of one line, i.e., one gate line of the liquid crystal display panel. The analog sample-hold circuit 151 samples and holds the signals transmitted through the analog switches 150 while supplying the signals to the source lines.

Fig. 14 shows a special structure of the line memory circuit 142 (as shown in Fig. 11) for supplying the video signals to the respective source drivers 143 to 146. Referring to Fig. 14, the line memory circuit 142 comprises: a block 100 for preparing video signals for two lines for an odd-numbered gate line and an even-numbered gate line (ie, two gate lines) from the video signals VB, VR, VG for one horizontal period; a data signal train converting circuit 113 for preparing a data signal train in which the video signals for the two gate lines as output from the block 100 are selectively arranged as the video signal for the even-numbered source lines and the video signal for the odd-numbered source lines; a memory block 200 for dividing the video signal data for the odd-numbered source lines and the video signal data for the even-numbered source lines from the data signal train converting circuit 113 into video signal data for the first-half source lines and video signal data for the second-half source lines, dividing the data into a total of eight groups (odd-numbered gate line group, even-numbered gate line group, odd-numbered source lines, even-numbered source lines, first-half source lines and second-half source lines) and storing these data in these eight groups, and alternately reading out the video signal data for the first-half source lines and the second-half source lines with respect to a gate line; polarity switching circuits 127, 128 for switching the polarities of the signals of the video signal data from the memory block 200 according to an odd-numbered gate line and an even-numbered gate line; and a block 300 for receiving the video signal data from the polarity switching circuits 127, 128 and for creating three separate signal trains of video signal data for the respective colors R, G, B from one signal train of video signal data.

The block 100 which produces the video signal data for two gate lines comprises A/D converters 101 to 106 for sampling the respective analog video signals VG, VR, VB at predetermined timings and converting them into digital signals; and 3-state buffers 107 to 112 for receiving the respective output signals of the A/D converters 101 to 106 at predetermined timings to output them. The A/D converters 101 to 103 produce video signal data corresponding to one gate line (e.g., an odd-numbered gate line), and the A/D converters 104 to 106 produce video signal data corresponding to the other gate line (e.g., an even-numbered gate line). The group of buffers 107 to 109 and the group of buffers 110 to 112 have different timings for inputting and outputting signals, and in these buffers, three trains of video signal data (corresponding to the signal data for R, G, B) are converted into one train of data signal.

The memory block 200 comprises a total of four line memories 118, 119, 120 and 121, that is, a pair of two memories, one for storing video signal data to be supplied to odd-numbered source lines and the other for storing video signal data to be supplied to even-numbered source lines, and another pair of similar memories for simultaneously performing a write operation and a read operation in the memories. The memories 118, 119 operate as a pair, and the memories 120, 121 operate as a pair. Accordingly, data is read from the memories 120, 121 while data is written into the memories 118, 119. Video data to be supplied to the odd-numbered source lines, for example, is written into the memories 118, 120, and video signal data to be supplied to the even-numbered source lines, for example, is written into the memories 118, 120. B. are to be supplied to the even-numbered source lines, are stored in the memories 119, 121.

Between the data signal train conversion circuit 113 and the memories 118, 120, there are 3-state buffers 114, 115 for receiving the output data signal train of the data signal train conversion circuit 113, as well as a data bus multiplexer 125 for selectively transmitting one of the output signals of the buffers 114, 115 to one of the memories 118, 120 and for connecting the output bus of the memory into which no data is written to the polarity switching circuit 127. Between the memories 119, 121 and the data signal train conversion circuit 113, there are 3-state buffers 116, 117 for transmitting the output signal of the data signal train conversion circuit 113, as well as a data bus multiplexer 126 for to connect data write lines from the buffers 116, 117 to the memories 119, 121 and to connect data read lines from the memories 119, 121 to the polarity switching stage 128.

The output of the 3-state buffer 114 is transmitted to the memory 118 and the output of the 3-state buffer 115 is transmitted to the memory 120. The output of the 3-state buffer 116 is transmitted to the memory 119 and the output of the 3-state buffer 117 is transmitted to the memory 121. The data bus multiplexer 125 transmits the output of the memory 120 to the polarity switching stage 128 while data is being written from the buffer 114 to the memory 118. Similarly, the data bus multiplexer 126 transfers the output signals of the memory 121 to the polarity switching circuit 128, while the output signals of the buffer 116 are written into, for example, the memory 119. The above-described structure makes it possible to prevent the occurrence of a conflict situation between a data write operation and a data read operation on the data bus.

For each of the memories 118 to 121, there is a write address generating circuit 123 for generating write addresses, a read address generating circuit 124 for generating read addresses for the memories 118 to 121, and an address bus switching circuit 122 for selectively transmitting the address signals from the write address generating circuit 123 and the read address generating circuit 124 to the memories 118, 119 and the memories 120, 121 depending on the read operation and the write operation of the respective memories.

The address bus switching circuit 122 transmits the output signal of the address generating circuit 123 to the memories 118, 119 while they are executing a write operation, and at the same time it transmits the addresses from the read address generating circuit 124 to the memories 120, 121. Accordingly, the address bus switching circuit 122 transmits the read addresses from the read address generating circuit 124 to the memory that is executing a read operation, and it transmits the write addresses from the write address generating circuit 123 to the memory that is executing a write operation.

The block 300 comprises latches 129 to 134, which consist of D flip-flops, for example, for converting a data signal train from the polarity switching stages 127, 128 into three signal trains of video signals (ie the respective video signals for R, G, B), and D/A converters 135 to 140 for converting the respective output signals of the latches 129 to 134 into analog signals, which is done with predetermined timing. The group of latches 129 to 131 and that of latches 132 to 134 have different storage times, and each group carries out a storage process for a data signal train from each of the polarity switching stages 127, 128 with predetermined timing. , thereby storing only the video signal data of the corresponding colors. More specifically, the latches 129, 132 store the video signal data B, the latches 130, 133 store the video signal data R, and the latches 131, 134 store the video signal data G.

In order to control the operation timing of each block, a control circuit 141 is provided which starts the operation in response to a line memory start signal φs1, the operation timing being determined in response to a line memory clock signal φc1, and supplies various control signals at a predetermined timing. The operation of each circuit block will be described below. In the following, only the operation of one circuit will be described, i.e., the operation for an even-numbered or an odd-numbered gate line and a pair of memories, for the sake of simplicity of explanation.

First, referring to Figs. 15 and 16, a description will be given of the operation for creating digital video data for the even and odd gate lines from the video signal for one horizontal period. Fig. 15 shows a structure for creating video signal data corresponding to one gate line.

Fig. 15 shows A/D converters 152-154 which perform A/D conversion in response to a line memory clock φ2, and 3-state buffers 155-157 which input and output the data at different timings. The 3-state buffer 155 inputs and outputs data in response to a control signal (gate signal) GB, the buffer 156 inputs and outputs data in response to a control signal GR, and the buffer 157 inputs and outputs data in response to a control signal GG.

The respective analog video signals VB, VR, VG are The signals are sampled in the A/D converters 152 to 154 at the next rise of the line memory clock φ2, and these signals are output as digital video data at the next fall of the clock φ2. The respective 3-state buffers 155 to 157 output the signals supplied thereto when the respective control signals GB, GR, GG become L level. The control signals GB, GR, GG form three-phase non-overlapping clocks synchronized with the clock signal φ2 as shown in (e), (f), (g) in Fig. 16, and accordingly the data signal trains output from the buffers 155 to 157 have the same order as the color arrangement of the color filters of the liquid crystal display panel.

Although the A/D converters 152 to 154 provided corresponding to the respective colors R, G, B are operated in response to the same clock, the clock phase for the odd-numbered gate lines differs from that for the even-numbered gate lines by 180° for the reasons described below. In the above construction, the video signal data for one pixel in the horizontal direction of the liquid crystal display panel is sampled and output at one clock of the A/D converters. On the other hand, in the case of color images having a triangular arrangement, the arrangement of the pixels in the odd-numbered gate lines is shifted from that in the even-numbered gate lines by 1.5 pixels. This shift of 1.5 pixels causes a delay of 1.5 clock cycles with respect to the clock signal φ2. This difference of 1.5 clock cycles corresponds to a value obtained by adding a clock phase of 180° to the delay of one clock cycle, and the delay of 1 clock cycle corresponds to a clock phase of 360°, ie, 0°. Accordingly, it is only necessary to delay the clock phase of the corresponding A/D converter by 180° with respect to odd and even gate lines. Accordingly, the activation timings of the buffers 155 to 157 differ, ie, the buffers 107 to 109 in Fig. 19, and those of the buffers 110 to 112 are spaced from each other by half of the line memory clock φ2. Since the video signal data of one color is outputted on a line memory clock φ2 from the buffers 155 to 157, a signal train of composite data is supplied to the data signal train conversion circuit 113 as shown in Fig. 16(k). Thus, by providing one digital signal train, it becomes possible to perform high-speed digital processing simultaneously for all three colors, and the number of circuit components can be reduced.

The digital video data trains for the odd-numbered and even-numbered gate lines generated from the buffers 107 to 109 and 110 to 112 are supplied to the data train converting circuit 113, and they are converted into a digital data train to be supplied to the odd-numbered source lines and a digital data train to be supplied to the even-numbered source lines. The specific structure and operation of the data train converting circuit 113 will be described below with reference to Figs. 17 and 18.

As shown in Fig. 17, the digital data signal train conversion circuit 113 comprises: a latch circuit 158 formed by, for example, a D flip-flop, which receives the video data signal train for the odd-numbered gate lines; a latch circuit 159 formed by, for example, a D flip-flop, which receives the video signal data for the even-numbered gate lines; a digital bus switching circuit 160 which receives the signals from the latch circuits 158, 159 and selects a transmission line in response to a selection signal SEB; and a latch circuit 161 formed by, for example, a D flip-flop, which latches the signal from the digital bus switching circuit 160.

A data signal train to be applied to the odd-numbered source lines is output from the latch circuit 161, and a digital data signal train to be applied to the even-numbered source lines is output from the digital bus switching circuit 160 directly through another data bus. The latch circuits 158, 159 and 161 perform a latching operation in response to the line memory clock φ2. The selection signal SEL applied to the digital bus switching circuit 160 has a cycle twice as long as that of the line memory clock φ2. The operation will be described below.

As shown in Fig. 18, the output timing of the digital data signal train for an odd-numbered gate line differs from that for an even-numbered gate line by 1.5 clocks (see Fig. 18(b) and (c)). The digital data signal train for an odd-numbered gate line and that for an even-numbered gate line, whose phases are shifted by 1.5 clocks from each other, are supplied to the latches 158, 159, respectively, and are latched at the same line storage clock φ2. Since the latches 158, 159 are composed of D flip-flops, the data signal trains are output from these latches 158, 159 with a delay of 1 clock (as shown in Fig. (d), (e)). The data signal trains whose phases have a delay of 1 clock are switched in response to the selection signal SEL in the digital bus switching circuit 160. More specifically, by switching the input/output connection lines in the digital bus switching circuit 160, the digital data signal train to be applied to the odd-numbered source lines and the data signal train to be applied to the even-numbered source lines are output from the digital bus switching circuit 160 as shown in (g), (h) of Fig. 18.

The digital data for the even-numbered gate lines and those for the odd-numbered gate lines appear alternately in the respective data signal trains. Since the output signal from the digital bus switching circuit 160 has a phase delayed by 1 clock as shown in Fig. 18, it is necessary to perform a write operation of the digital data directly into the memories with a delay of 1 clock, and it is also necessary to generate a write address for the memories with a delay of 1 clock. Accordingly, when the above-mentioned structure is used, there is a disadvantage that the circuit size is increased.

Accordingly, in order to write the data into the memories, without making correction for such clock delays, the digital data signal train having the phase advanced by 1 clock among the data signal trains output from the digital bus switching circuit 160 (i.e., the digital data signal train to be applied to the odd-numbered source lines in Figs. 17 and 18) is again stored in the latch circuit 161 formed by the D flip-flop, and the transmission thereof is delayed by 1 clock, whereby the timing of the video data signal train to be applied to the even-numbered source lines and the timing of the video data signal train to be applied to the odd-numbered source lines can be made to coincide. As a result, the writing operation for the digital data in the memories (for the digital data for the odd-numbered and even-numbered source lines) can be carried out simultaneously, and the writing addresses for the memories can be generated by a writing address generating circuit so as to be assigned to the respective memories, making it possible to reduce the number of components. Next, data writing and reading operations in the memory block 200 will be described.

Since the video signals must be processed sequentially, There are two odd-numbered source line memories and two even-numbered source line memories, so that each memory switches between reading and writing for one horizontal period. The capacity of each of the memories (118 to 121) can be estimated by considering the write and read addresses, the source line first half/second half switching bit X, and the odd-numbered gate line/even-numbered gate line switching bit Y. Assuming that the number of pixels for one horizontal period is 640 as stated above and that there are four source drivers, the source line first half/second half switching bit X is obtained as follows:

X ≥; log2; (N/4) = log2 (160).

Accordingly, X = 8. On the other hand, the odd gate line/even gate line switching bit Y has the value given below because after processing the data for all source lines (640), the subsequent gate line is scanned and a capacity for storing the data of all source lines as an address area for each gate line is required.

Y = X + 1 = 8 + 1 = 9.

Accordingly, the storage capacity of a memory is 1024 words, which is calculated according to 2(Y+1). The length of each of these words is determined by the resolutions of the A/D converters and the D/A converters.

The switching between the writing and reading operations for the memories 118 and 121 is carried out for one horizontal period. The writing and reading of data are selectively controlled by the 3-state buffers 114 to 117, which are present in the pre-stages of the respective memories, as well as by the data bus multiplexers 125 and 126, which are present in the read lines the memories 118 to 121 are present to perform selective switching between writing and reading operations of data for the memories 118 to 121 and to avoid collisions between reading and writing of data.

More specifically, in a data write operation to the memories 118 and 119, the 3-state buffers 114 and 116 included in the pre-stages of the memories 118 and 119 are activated, and the video data signal train from the data signal train conversion circuit 113 is written into the memories 118 and 119. Conversely, in a data read operation from the memories 118 and 119, the 3-state buffers 114 and 116 in the respective pre-stages are disabled so that the data read out from the memories 118 and 119 do not collide with the data from the data signal train conversion circuit 113.

The data bus multiplexers 125, 126 provided in the subsequent stages of the memories (i.e., the subsequent stages of the read lines) always select the data bus connected to the memory while reading from the memories 118 to 121, and connect the selected data bus to the polarity switching stages 127, 128 in the subsequent stages. Accordingly, the switching control signal φW applied to the data bus multiplexers 125, 126 becomes a control signal synchronized with the write/read control signal RW applied to the memories 118 to 121, and the connecting lines for the data bus are selectively switched for each horizontal period.

The write address for specifying a write position in the memory as supplied from the write address generating circuit 123 is incremented by one depending on the output timing of the data from the data signal train converting circuit 113, as shown in Fig. 19A, while the reset and setting the odd gate line/even gate line toggle bit Y. Similarly, the first half/second half source line toggle bit X is reset in the first 1/2 horizontal period and set in the second 1/2 horizontal period. When the X toggle bit is toggled, the less significant address (the address without the X and Y toggle bits) is reset.

More specifically, the write addresses in the first 1/2 horizontal period are 0, 2Y + 0, 1, 2Y + 1, . .., N/4 - 1, 2Y + N/4 - 1, and those in the second 1/2 horizontal period are 2X + 0, 2X + 2Y + 0, 2X + 1, 2X + 2Y + 1 ..., 2X + N/4 - 1, 2X + 2Y + N/4 - 1. As described above, when the number N of pixels for one horizontal period is 640, the write addresses generated in the first 1/2 horizontal period are 0, 512, 1, 513, ..., 159, 671, and the write addresses generated in the second 1/2 horizontal period are 156, 768, 157, 769, ..., 415, 927, as shown in Fig. 19A. Further, as shown in Fig. 19A, in both the video signal train for the odd-numbered source lines and the video data signal train for the even-numbered source lines, the video signal data for the odd-numbered gate line appears as the video signal for the even-numbered gate line alternately, and the write addresses for the respective data are switched by the switch bits X and Y. As a result, as shown in Fig. 19B, the video signal data is alternately written into the areas A1 and B1 of the memory in the first 1/2 horizontal period, and the video signal data is alternately written into the areas A2 and B2 of the memory in the second 1/2 horizontal period. In Fig. 19B, the area A is an area in which the digital video signal data for the even-numbered gate lines is stored, and the area B is an area in which the digital video signal data for the odd-numbered gate lines are stored. Accordingly, each of the memories for the odd-numbered and even-numbered source lines has four division areas, and accordingly, the video signal data is stored in a manner in which there is division into a total of eight areas.

The addresses for reading the digital data from the memories 118 to 121 are generated by the read address generating circuit 124, and they are transmitted to the memory in which a read operation is being carried out via the address bus switching circuit 122. The read address generated by the read address generating circuit 124 is incremented by one while the switching bit X for the first half/second half of the source line is alternately and repeatedly reset and set as shown in Fig. 20A. When the odd-numbered gate lines are selected in the first 1/2 horizontal period, the switching bit Y for the odd-numbered/even-numbered gate line is reset. When the even-numbered gate line is selected in the second 1/2 horizontal period, the switching bit Y for the odd-numbered, even-numbered gate line is set. Accordingly, when reading data, when the odd-numbered gate lines are selected, the toggle bit Y is reset, and when the even-numbered gate lines are selected, the toggle bit Y is set.

If the color order of the arrangement of the color filters in the liquid crystal display panel is B, G, R, ..., the data are stored in the memories in this order. Accordingly, the color order of the video signal data read out by the above-mentioned read addresses is B(0), R(256) R(1), G(257), G(2), B(258), etc. for the odd-numbered source lines, and the color order of the data read out for the even-numbered source lines is G(0), B(256), B(1), R(257), R(2), G(258), etc., where the numbers in parentheses represent the addresses. Accordingly, when the digital video data signal train thus read is converted into analog video signals by D/A conversion, signals of the same color follow one another, and there is no tolerance in selecting the signals and selectively transmitting the signals to the source drivers for driving the liquid crystal display panel.

Therefore, when reading the data, the switching bit X for the first half/second half of the source line is repeatedly set and reset, opposite to the case of writing data, incrementing by one. More specifically, when the source drivers take in data starting with the data of the second half of the source line, the color order of the digital video data for the odd-numbered source lines is R, B, G, R, B, G, while that for the even-numbered source lines is B, G, R, B, G, R. This arrangement is the same as the color arrangement of the color filters of the liquid crystal display panel, making it possible to easily distribute the signals to the source drivers.

Specifically, when the video signal data is supplied to the odd-numbered gate lines in the first 1/2 horizontal period, the read addresses are 2X + 0, 0, 2X + 1, 1, ..., 2X + N/4 - 1, N/4 - 1, and when the digital video data is supplied to the even-numbered gate lines in the second 1/2 horizontal period, the read addresses are 2Y + 2X + 0, 2Y + 0, 2Y + 2X + 1, 2Y + 1, ..., 2Y + 2X + N/4 - 2, 2Y + N/4 - 1.

In practice, if the values given above apply, the read addresses in the first 1/2 horizontal period are 256, 0, 257, 1, ..., 415, 159, and the read addresses in the second 1/2 horizontal period are 768, 512, 769, 513, ..., 927, 671, as shown in Fig. 20A. Accordingly, as shown in Fig. 20B, when even-numbered gate lines are selected, the data is alternately read out from the memory for the odd-numbered source lines in the order of the regions A2, A1. When the odd-numbered gate lines are selected, the data is alternately read out in the order of the regions B2, B1. The same applies to the memory for the even-numbered source lines, and the data is alternately read out in the order of the regions A2', A1' or in the order of the regions B2', B1', in the manner shown in Fig. 20B(b).

Accordingly, the read addresses and the write addresses may be common to both the memory for the odd-numbered source lines and the memory for the even-numbered source lines. Accordingly, only by providing an address generating circuit for reading and writing and assigning the addresses from the address generating circuit only by means of the address bus switching circuit 122, it is possible to write and read video signal data. As for the digital video signal data read through the data bus multiplexers 125, 126, their respective bit values are inverted in the digital polarity switching circuits 127, 128. An example of a specific structure of each of the digital polarity switching circuits 127, 128 is shown in Fig. 21.

According to Fig. 21, the digital polarity switching circuit comprises eight Ex-OR gates 162-1 to 162-8. The structure shown in Fig. 21 is such that the digital video signal data comprises eight bits, that is, the digital data for one pixel has a width of eight bits. A polarity switching signal PC is output from a control circuit 141 is applied to one input of each of the Ex-ODEP gates 162-1 to 162-8. Normally, the Ex-OR gates output a high level (H) signal when the bit values at their two inputs do not agree with each other, and output a low level (L) signal when the bit values at both inputs agree. Accordingly, when the polarity switching signal PC is at L level, each of the Ex-OR gates 162-1 to 162-8 allows the input digital video signal data to pass through it, and when the polarity switching signal PC is at H level, each of the gates inverts the bit value of the digital video data input thereto and outputs the inverted value. The level of the polarity switching signal PC is switched depending on the first 1/2 horizontal period and the second 1/2 horizontal period, as shown in Fig. 22. In other words, the cycle of the polarity switching signal PC is one horizontal period. Accordingly, the polarities of the signals differ by 180 degrees depending on the first 1/2 horizontal period and the second 1/2 horizontal period. Accordingly, the signal polarities for the odd-numbered gate lines and the even-numbered gate lines can be reversed, and signal switching in the high-speed line sequence system can be achieved. The signal that has passed through the polarity switching circuits 127, 128 is a digital video data signal train. In order to supply the digital video data signal train to the respective D/A converters 135 to 140 provided corresponding to the colors R, G, B, the digital data signal train is transferred to the latch circuits 129 to 134 formed by D flip-flops, where it is latched at different timings and converted into three parallel digital video signal data signal trains corresponding to the respective colors R, G, B. Since the operation in the path for generating the video signal to be transmitted to the odd-numbered source lines and that in the path for generating the video signal to be transmitted to the Since the video signals to be transmitted via even-numbered source lines coincide with each other, only the operation for one path will be described below with reference to Figs. 23 and 24.

Fig. 23 shows a latch stage 163 formed by a D flip-flop for storing the signal B, a latch stage 164 formed by a D flip-flop for storing the signal R and a latch stage 165 formed by a D flip-flop for storing the signal G. The latch stages 163 to 165 each contain A/D converters 166 to 168 to convert their output signals into analog signals. The latch stage 163 carries out a storing operation in response to a latch control signal LB, the latch stage 164 carries out a storing operation in response to a latch control signal LR, and the latch stage 165 carries out a storing operation in response to a latch control signal LG. These control signals LB, LR, LG constitute clock signals having three different phases which do not overlap each other, and the cycle of each of the clock signals LB, LR, LG is one which is three times longer than that of the line memory clock φ2. First, assume that the composite data signal train output from the data polarity switching stage is in the order of R, B, G, R... as shown in Fig. 24(b).

In this case, the latch circuit 164 performs a latch operation in response to the control signal LR, and then the latch circuits 165 and 163 perform latch operations in this order. Since each of the latch circuits 163 to 165 performs a latch operation for three line memory clocks φ2, the data retention period of each of the latch circuits 163 to 165 is a period of three line memory clocks φ2. The output signals of the respective D/A converters 135 to 140 (166 to 168) are supplied to the corresponding Source drivers 143 to 146. Among the source drivers 143 to 146 shown in Fig. 11, the source drivers 143 and 145 connected to the first-half source lines operate on the same clock, and the source drivers 144 and 146 connected to the second-half source lines operate on the same clock. Accordingly, as for the odd-numbered source lines, the second-half source drivers and the first-half source drivers take in data alternately, and similarly, the source drivers 145 and 146 connected to the even-numbered source lines take in data alternately.

The data output from the respective D/A converters 135 to 140 to the clock signals φ4 for driving the source drivers 143 to 146 are sampled and held in the sample-hold circuits 151 of the corresponding source drivers. At this time, as shown in Fig. 24(j), (k), each of the cycles of the clocks φ4 for the source drivers has a value twice as long as that of the line memory clock 42, and each of the source drivers can operate at the same operating speed as in the double-speed line sequential system or the interlaced system. More specifically, as shown in Figs. 13 and 24, in the source drivers connected to the odd-numbered source lines, first the source driver for driving the source lines of the second half operates and samples the signal R (R321), and then the source driver for driving the source lines of the first half operates and samples the signal B (B1). Then, the signals G323, R3, B325, G5 are sampled in sequence. This sampling is carried out by turning on the analog switches 150 (150-1 to 150-m) included in the respective source drivers in sequence. Accordingly, even if the output signals of the D/A converters 166 to 168 (135 to 140) are supplied simultaneously, the three signal lines are arranged in parallel and they are sequentially connected to the analog switches, and therefore only the video signal corresponding to one of the three output signals is sampled in the analog sample-hold circuit 151. The analog sample-hold circuit 151 transfers the data to the corresponding source line after completion of all the sample-hold operations for the signals supplied thereto in connection with a gate line. Accordingly, it becomes possible to drive a liquid crystal display panel according to the high-speed line-scanning system by driving the respective source drivers at the same speed as in the conventional double-speed line-scanning system and the interlaced system. The manner of dividing the areas of the display panel and the number of source drivers are not limited to what is described in the above embodiments.

Accordingly, a liquid crystal display panel according to the invention can be driven with only one line memory circuit for three colors, and accordingly it is possible to provide an inexpensive liquid crystal driving device with a simplified structure with low power consumption.

In addition, at least one pair of memories is used in such a manner that video data is written into one of the memories and read from the other memory, and the read video data is alternately transferred to source drivers for driving a first half of the liquid crystal display panel and to source drivers for driving the second half thereof. Accordingly, it is possible to obtain a liquid crystal driving device with excellent linearity which drives a liquid crystal display panel at high speed in a corresponding manner even when when operating with low frequency clocks.

Furthermore, according to the invention, the storage area is divided into areas for even gate lines, odd gate lines, odd source lines, even source lines, first half source lines and second half source lines, and color video data converted into a data signal is stored in each of the areas and read sequentially according to a predetermined order. Accordingly, a liquid crystal display panel can be operated according to the high-speed line scanning system while the source drivers for driving the liquid crystal display panel are operated at the same speed as in the conventional double-speed line scanning system or the conventional interlaced system. Accordingly, it is possible to improve the horizontal resolution and the moving picture response and to suppress the occurrence of flicker, and this liquid crystal display panel with high picture quality for a large screen can be operated with a reduced number of components.

Although the invention has been described and illustrated in detail, it is to be clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, since the scope of the invention is limited only by the terms of the appended claims.

Claims (24)

1. A method for operating a display device (32; 147) having a matrix of color pixels (148) arranged to be driven by respective driver lines (S), the driver lines being divided into a first and a second group of driver lines, characterized in that parallel signals (VB, VR, VG) representing respective color components of an image to be displayed are converted into serial data, the data are stored in a memory (43, 44; 118, 119, 120, 121), the data are read out of the memory in sequence, and the successively read data are alternately fed to the first and second driver line groups. 2. The method of claim 1, wherein the driver lines comprise a plurality of source lines, each of which is connected to color pixels of a column, and the display device (32) comprises a plurality of gate lines, each of which is connected to the color pixels of a row, wherein a first (33) and a second (35) source driver for driving a first half and a second half of odd-numbered source lines, respectively, and a third (34) and a fourth (36) source driver for driving a first half and a second half of even-numbered source lines, respectively, are provided on the periphery of the display panel (32), wherein the step of converting parallel signals into serial data comprises the following: - generating a first digital data signal train for the odd-numbered source lines and a second digital data signal train (Fig. 7(1)) for the even-numbered source lines, if first these parallel color signals (VB, VR, VG) received comprising three analog color signals, wherein the first digital data signal train comprises digital color signals for the three colors arranged in the color order of the odd-numbered source lines, and the second digital data signal train comprises digital color signals of the three colors arranged in the color order of the even-numbered source lines; - wherein the storing step comprises - Writing the first and second digital data signal trains into a first and second storage element of the memory (43, 44) depending on an address sequence, - wherein the first and the second memory element each belong to an address range of a first half and an address range of a second half, respectively; - wherein the reading step comprises alternately reading the first half region and the second half region from the first and second storage elements, respectively, and generating a third digital data signal train and a fourth digital data signal train; - and the applying step comprises converting the third and fourth digital data signal trains into second and third analog color signals (VB, VR, VG) of the three colors in parallel, transmitting the second analog color signals to the first and second source drivers and transmitting the third analog color signals to the third and fourth source drivers; and - the first and second source drivers are alternately activated, and the third and fourth source drivers are alternately activated, thereby holding the second analog signal in the first and second source drivers and the third analog color signal in the third and fourth source drivers. 3. The method of claim 1, wherein the color pixels (148) are arranged in a triangular arrangement, the display device (147) includes a plurality of gate lines (g), each of which is connected to the pixels of a row, and the driver lines comprise a plurality of source lines (S) for transmitting signals to the plurality of pixels, the display device including at its periphery a first source driver (143) for driving the source lines of a first half of the odd-numbered source lines, a second source driver (144) for driving the source lines of a second half of the odd-numbered source lines, a third source driver (145) for driving the source lines of a second half of the even-numbered source lines, and a fourth source driver (146) for driving the source lines of a second half of the even-numbered source lines, the pixels of the same color being connected to a source line, and the converting step comprising: - converting the first parallel color signals comprising three analog color signals (VB, VR, VG) to create a first digital data signal train (Fig. 18(b)) of color signals to be transmitted to the pixels of a first gate line and a second digital data signal train (Fig. 18(c)) of color signals to be transmitted to the pixels of a second gate line forming a pair with the first gate line, wherein the first digital data signal train and the second digital data signal train have different phases corresponding to 1.5 pixels and wherein the first and second digital data signal trains comprise digital color signals of the three colors arranged in the same order as the color order of the pixels along a gate line; and - the difference in phases between the first and the second digital data signal train is corrected so that the difference corresponds to one pixel; - wherein a third digital data signal train (Fig. 18(g)) to be transmitted to the odd-numbered source lines and a fourth digital data signal train (Fig. 18(h)) of color signals applied to the even-numbered source lines among the first and second digital data signal trains with the corrected phases, the third and fourth digital data signal trains comprising such data signal trains in which the data for the first gate line and the data for the second gate line are alternately arranged, the third digital data signal train comprising a digital color signal train arranged in an order following the color order of the odd-numbered source lines, and the fourth digital data signal train comprising a digital color signal train arranged in an order following the color order of the even-numbered source lines; and - wherein the phase of the third digital data signal train and that of the fourth digital signal train coincide with each other; wherein the storing step comprises: - writing the third digital data signal train into a first storage element (118, 120) and the fourth digital data signal train into a second storage element (119, 121) of the memory, the first and second storage elements having a first (A₁), a second (A₂), a third (A₃) and a fourth (A₄) storage area according to an address order, the writing step comprising the steps of writing the supplied digital data in an alternating manner into the first and third storage areas of the first and second storage elements in a first half period of a horizontal scanning period (Fig. 19(a)) and writing the supplied data in an alternating manner into the second and fourth storage areas in the second half period of the one horizontal scanning period (Fig. 19B(b)); - wherein the reading step comprises reading the data from the first storage element to generate a fifth digital data train (Fig. 20A(c)) and simultaneously reading the data from the second storage element to produce a sixth digital data signal train (Fig. 20A(d)), wherein the reading step comprises the steps of reading the data alternately from the first and second storage areas of the first and second storage elements in the first half period of the one horizontal scanning period (Fig. 20B(a)) and reading the data alternately from the third and fourth storage areas thereof in the second half period of the one horizontal scanning period (Fig. 20B(b)), wherein the fifth digital data signal train comprises a digital color signal train of the three colors arranged in a sequence following the color order of the odd-numbered source lines, and the sixth digital data signal train comprises a digital color signal train of the three colors arranged in a sequence following the color order of the even-numbered source lines; and the applying step comprises: - creating a second analog color signal with three color signals (VB, VR, VG) in parallel from the sixth digital data signal train and transmitting it to the third and fourth source drivers, wherein the step of creating the second analog color signal includes a step of successively and periodically activating three latch devices (163, 164, 165) arranged in parallel to simultaneously receive the fifth digital data signal train, and wherein the step of creating the third analog color signal includes a step of successively and periodically activating a further three latch devices (163, 164, 165) arranged in parallel to simultaneously receive the sixth digital data signal train; and - the first and second source drivers are alternately activated to maintain the second analogue colour signal, and the third and fourth source drivers are alternately activated to maintain the third analogue colour signal whereby two adjacent gate lines are activated within one horizontal scanning period. 4. A method according to claim 3, further comprising the step of inverting the polarities of the first and sixth digital data signal trains (Fig. 20A(c), (d)) such that the polarities of the data in the first half period and the second half period of the one horizontal scanning period are inversely related (Fig. 22). 5. Method according to one of the preceding claims, wherein the display device (32; 147) is a liquid crystal color display device. 6. Device for operating a display device (32; 147) with a matrix of color pixels (148) arranged so that they are controlled by respective driver lines (S), the driver lines being divided into a first and a second driver line group, characterized by: - a device (39, 40; 101 to 116, 107 to 112, 113) for converting parallel signals (VB, VR, VG) representing respective color components of an image to be displayed into serial data; - a device (43, 44, 49, 50; 118 to 121, 122, 123) for storing the serial data; - means (45, 49, 51, 52; 122; 124, 125, 126) for reading the data in sequence from the storage means; and - means (46, 47, 33 to 36, 129 to 134, 135 to 140, 143 to 146) for alternately supplying the read data to the first and second driver line groups. 7. Device according to claim 6, wherein the color pixels in the matrix of rows and columns are arranged according to a predetermined color order and the driver lines comprise a plurality of source lines, each of which is connected to a column of color pixels of the same color, the plurality of source lines being divided into at least a first and a second group, the first and second groups each being further divided into a first and a second subgroup, the means for applying the read signal to the driver lines comprising: - means for transmitting a signal to each of the plurality of source lines, the signal transmitting means comprising first source driver means (33, 35) and second source driver means (34, 36) provided to correspond to the first and second groups of source lines, respectively, and the first and second source driver means each including a first driver (33, 34) corresponding to the first subgroup and a second driver (35, 36) corresponding to the second subgroup, the first driver and the second driver being alternately activated to store a color signal respectively supplied thereto; - wherein the device comprises a first signal supply device (37) and a second signal supply device (38) for supplying color signals to the corresponding source driver devices; - wherein the first and second signal supply devices each include the following - firstly, the conversion device (39b, 39r, 39g, 40b, 40r, 40g, 41, 42) for receiving the parallel colour signals, which are analog signals, and for converting them into a digital data signal train with a colour sequence which corresponds to the colour sequence as determined by the source lines of the corresponding group; - the storage device (43, 44, 49, 50) for successively storing the output signal of the conversion device according to an address, wherein the storage device includes a first area for storing data to be transmitted to the first subgroup and a second storage area for storing data to be transmitted to the second subgroup; - the means (49, 51) for sequentially reading the stored data from the storage means, wherein the reading means includes an alternate reading means for alternately reading the data from the first area and the second area; and - an analog conversion device (46b, 46r, 46g, 47b, 47r, 479, l1b, l1r, l19) for converting a data signal train read by the reading device into analog signals and for transmitting them to the associated source driver device, this analog conversion device comprising a second conversion device (46b, 46r, 46g, 47b, 47r, 47g, l1b, l1r, l1g) for converting the read data signal train into parallel, analog color signals and for outputting them. 8. The device of claim 7, wherein the plurality of source lines comprise odd-numbered source lines forming the first group and even-numbered source lines forming the second group, and comprise first-half source lines forming each of the first subgroups and second-half source lines forming each of the second subgroups, - wherein the alternate reading means includes means (51, 49) for alternately reading data from the second area and the first area of the storage means. 9. Device according to one of claims 7 or 8, wherein the storage means comprises at least a first (43) and a second (44) memory, each of which has a capacity sufficient to store the data to be transmitted to a pixel line, the device further comprising - means (45, 52) for controlling the operation of the memory means for reading data from the first or second memory while data is being written into the other memory. 10. Device according to one of claims 7 to 9, in which the first conversion device includes: - a plurality of A/D conversion devices (39b, 39r, 39g) corresponding to the plurality of types of analog color signals, each supplied in parallel, for converting the corresponding analog color signals into digital signals; - a plurality of buffer devices (40b, 40r, 40g) for receiving the output signals of the respective A/D conversion devices at a predetermined time position and for outputting the same, the plurality of buffer devices being activated sequentially and periodically in accordance with an order following the color order of the source lines of the respective groups; and - means (41, 42) for receiving the output signals of the plurality of buffer means, for converting them into a digital data signal train and for supplying the data signal train to the storage means. 11. Device according to one of claims 7 to 10, in which the second storage device includes - a plurality of latch means (46b, 46r, 46g) provided in parallel for storing the digital data read by the reading means at different timings, the plurality of latch means being means for outputting the plurality of types of color signals in parallel and successively and periodically according to the order of reception of the color signals by the associated Source driver device can be activated to store and output the supplied data; - D/A conversion devices (47b, 47r, 479) for converting the output signals of the corresponding latch device into analog signals; and - means (l1b, l1r, 119) for transmitting the output signals of the associated D/A converter means in parallel manner to an associated source driver means. 12. The device according to claim 6, wherein the color pixels are arranged according to a predetermined color order and the drive lines comprise a plurality of source lines (S) for transmitting signal potentials to the plurality of pixels, the device comprising: a plurality of gate lines (g) provided in a direction intersecting the plurality of source lines for transmitting a signal that activates a row of the plurality of pixels, pixels of the same color being connected to a source line, and the plurality of source lines being assigned numbers that increase continuously so that the plurality of source lines are divided into a group of odd-numbered source lines, a group of even-numbered source lines, a group of first-half source lines and a group of second-half source lines, the means for applying read data to the drive lines comprising: - first and second source driver means (143, 144, 145, 146) corresponding to the group of odd-numbered source lines and the group of even-numbered source lines, respectively, the first and second source driver means each including a first source driver (143, 145) for transmitting a signal to the source lines of the first half and a second source driver (144, 146) for transmitting a signal to the source lines of the second half, which are alternately activated, and the first and the second source driver means each comprise means (149, 150, 151) for temporarily storing signals supplied thereto in an order corresponding to the order of the color arrangement of the corresponding source line groups and for transmitting the stored signals to the source lines of the corresponding groups at a predetermined time position, the conversion means comprising the following: - means (101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113) for receiving an analog video signal corresponding to a line of the plurality of pixels and for generating a digital data signal train to be displayed in the pixels connected to the first line and a second line forming a pair with the first line, the generation being carried out from the video signal received for a line, which includes the parallel video signals (VB, VR, VG) of the three colors, the storage device comprising the following: - means (114, 115, 116, 117, 118, 120, 121, 123, 141) for receiving the output signal of the generation which generates the data signal train and for storing the received video signal data by dividing it into groups of signal data to be transmitted to the first row, the second row, the group of odd-numbered source lines, the group of even-numbered source lines, the group of first-half source lines and the group of second-half source lines; - wherein the reading device comprises means (124, 141) for serially reading the data to be transmitted to the pixels of the first line among the data stored in the memory device in a predetermined order, followed by serially reading the data to be transmitted to the pixels of the second line in the predetermined order; and - the device further comprises means (129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140) for temporarily storing of the data signal train supplied by the reading device with a predetermined time position, for converting the same into parallel, analog color signals and for transmitting these color signals to the first and second source driver devices, wherein the transmission device includes a first latch conversion device for temporarily storing the data to be transmitted to the odd-numbered source lines within the read data signal train and for converting the same, and a second latch conversion device for temporarily storing the data to be transmitted to the even-numbered source lines and for converting the same. 13. The device of claim 12, wherein the display device comprises color filters with a triangular arrangement, the pixels of the respective adjacent gate lines being offset by 1.5 pixels, the means for generating the digital data signal train comprising: - a first generating device (101, 102, 103, 107, 108, 109) for receiving the three different color signals in parallel and for generating the color signals to be transmitted to the pixels of the first gate line in the form of the digital signal train, said first generating device comprising a device (107, 108, 109) for generating serial digital data corresponding to the three different color signals in an order corresponding to the color order of the pixels connected to the first gate line, and - includes a second generating device (104, 105, 106, 110, 111, 112) which is activated at a time position complementary to the activation of the first generating device in order to generate a digital data signal train having an arrangement of the three color signals with the same order as the color order of the pixels connected to the second gate line. 14. The apparatus of claim 13, wherein the means for generating the digital data signal train further comprises: - a first data signal train converting means (158, 160, 161) for receiving the output signals of the first and second generating means and for generating a first data signal train consisting of digital data to be transmitted to the odd-numbered source lines, and a second data signal train converting means (159, 160) for generating a second data signal train from digital data to be transmitted to the even-numbered source lines; - wherein the first and second data signal trains each contain a data signal train in which the data to be transmitted to the pixels of the first gate line and the data to be transmitted to the pixels of the second gate line are arranged alternately. 15. Device according to one of claims 13 or 14, in which the first generating device comprises: - first, second and third A/D conversion means (101, 102, 103; 152, 153, 154) provided corresponding to the parallel, analog color signals for the three colors, in order to convert the corresponding color signals into digital signals in response to clock signals; - first to third buffer means (107, 108, 109), respectively corresponding to said first to third A/D conversion means, for selectively passing the output signals of the associated A/D conversion means, said first to third buffer means being successively and periodically activated to thereby generate a digital data signal train arranged in an order following the color order of the pixels of said first line; - a fourth, fifth and sixth A/D converter (104, 105, 106) each of which corresponds to the parallel analogue colour signals which correspond to three colors in order to convert the corresponding color signals into digital signals in response to inverted signals of the clock signals; and - fourth, fifth and sixth buffer means (110, 111, 112) corresponding to the fourth to sixth A/D conversion means, respectively, for selectively passing the output signals of the corresponding A/D conversion means, the fourth to sixth buffer means being successively and periodically activated to thereby generate a digital color data signal train arranged in an order following the color order of the pixels of the second gate line; and the digital data signal train from the first to third buffer means is generated at a timing different by 1.5 pixel periods from that of the digital data signal train from the fourth to sixth buffer means. 16. The apparatus of claim 13, wherein the digital data signal train from the first generating means has a phase that is 1.5 pixels ahead of that of the digital data signal train from the second generating means, the means for generating the digital data signal train further comprising: - a first latch device (158) for storing and outputting the digital signal train from the first generating device in response to a clock signal; - a second latch device (159) for storing and outputting the digital data signal train from the second generating device in response to the clock signal; - signal train conversion means (160) receiving the output signals of the first and second generating means, exchanging the respective output signals of the first and second generating means in response to a selection signal and generating a data signal train consisting of data to be applied to the odd-numbered source lines and a data signal train to be transmitted to the even-numbered source lines; and - a third latch device (161) for storing and outputting the digital data signal train for the odd-numbered source lines from the signal train conversion device in response to the clock signal. 17. Apparatus according to claim 14, wherein the storage device comprises: - a first storage device (118, 120) for storing digital data for the odd-numbered source lines, wherein this first storage device has a storage area for a first half and a storage area for a second half; - a second storage device (119, 121) for storing digital data for the even-numbered source lines, wherein the second storage device has a second storage area for a first half and a storage area for a second half; - a first writing device (122, 123, 144) for alternately writing the output signal of the first data signal train conversion device into the storage area of the first half (A) and the storage area of the second half (B) of the first storage device; and - a second writing device (122, 123, 141) for alternately writing the output signal of the second data signal train converting device into the storage area of the first half and the storage area of the second half of the second storage device; - wherein the first and second writing means jointly comprise means (123) for generating an address specifying the destination for data to be written into the corresponding storage means and for writing the data into the corresponding storage means according to the same address as simultaneously specified by the Write address generating device is supplied. 18. The apparatus of claim 17, wherein each of the memory areas of the first half (A) and the second half (B) of each of the first and second memory devices is further divided into a first (A₁, B₁) and a second (A₂, B₂) sub-memory area and - the write address generating means (123) generates addresses so that data is alternately written into the first sub-memory area (A₁) of the first half memory area and the first sub-memory area (B₁) of the second half memory area within a period of the first half of a horizontal scanning period in which a gate line is activated, and generates the address so that the data is alternately written into the second sub-memory area (A₂) of the first half memory area and the second sub-memory area (B₂) of the second half memory area within a period of the second half of the one horizontal scanning period. 19. Device according to one of claims 13 to 16, in which the reading device comprises: - a first reading device (118, 120, 124, 141) for alternately reading data to be transferred to the source lines of the first half of the odd-numbered source line group of the first row and the data to be transferred to the source lines of the second half of the odd-numbered source line group of the first row from the memory device, and for alternately reading, after reading the data for the first row, the data to be transferred to the source lines of the first half of the odd-numbered source line group of the second row and the data to be transferred to the source lines of the second half of the odd-numbered source line group of the second row; and - a second reading device (119, 121, 124, 141) for alternately reading data to be transferred to the source lines of the first half of the even-numbered source line group of the first row and the data to be transferred to the source lines of the second half of the even-numbered source line group of the first row from the memory device, and for alternately reading, after reading the data for the first row, the data to be transferred to the source lines of the first half of the even-numbered source line group of the second row and the data to be transferred to the source lines of the second half of the even-numbered source line group of the second row, - wherein the data signal trains read by the first and second reading devices have the same color sequence as the color sequence of the pixels of the corresponding gate lines. 20. Device according to claim 18, in which the reading device comprises: - a first reading device (124, 141) for reading data from the first storage device (118, 120), this first reading device alternately reading data of the first sub-area (A₁) of the storage area of the first half of the first storage device and data of the second sub-area (A₂) thereof in the first half period of the one horizontal period, and alternately reading data of the first sub-area (B₁) of the area of the second half of the first storage device and data of the second sub-area (B₂) thereof in the second half period of the one horizontal period; and - a second reading device (124, 141) for successively reading data from the first storage device (119, 121), the second reading device alternately reading data from the first (A₁') and the second (A₂') sub-storage area of the storage area of the first half of the second storage means in the first half period of the one horizontal period, and alternately reads data of the first (B₁') and second (B₂') sub-storage areas of the second half storage area of the second storage means in the second half period of the one horizontal period; - wherein the first and second reading devices have a read address generating device (124) in common and - the first and second reading devices read the data with the same time position corresponding to the same address from the reading address generating device. 21. Apparatus according to any one of claims 12 to 20, further comprising means (127, 128) for receiving the data signal train from the reading means and for reversing the polarity of the data each time it has received pixel data for a gate line. 22. Apparatus according to claim 21, wherein the inverting means comprises means (161-1 to 161-8) for inverting each bit value of the received data. 23. The apparatus of claim 20, wherein the means for transmitting the signal to the source driver means comprises: - first, second and third latch devices (129, 130, 131) connected in parallel to one another for storing and outputting the output signal of the first reading device (118, 120) at different timings, the first to third latch devices being activated successively and periodically to store the supplied signal depending on the color sequence of the source lines driven by the first source driver device (143, 144); - a first, second and third D/A converter (135, 136, 137) for converting the output signals of the corresponding latch device into analog signals and for transmitting them in parallel to the first source driver device; - fourth, fifth and sixth latch means (132, 133, 134) provided in parallel to one another for storing and outputting the output signal of the second data reading means (119, 121) at different timings, the fourth to sixth latch means being activated successively and periodically to store the supplied data in accordance with the color sequence of the even-numbered source lines; and - fourth, fifth and sixth D/A conversion means (138, 139, 140) for converting the output signals of the corresponding latch means into analog signals and for transmitting them in parallel to the second source driver means (145, 146). 24. Device according to one of claims 12 to 16, in which the storage device comprises: - a first pair of storage elements (118, 119) for storing data for the group of odd-numbered source lines and data for the group of even-numbered source lines, and - a second pair of memory elements (120, 121) in which a data read operation is carried out when a data write operation is carried out in the first pair of memory elements, wherein the data write operation is carried out when a data read operation is carried out in the first pair of memory elements.