DE62658T1 - STACK STORAGE FOR A DATA PROCESSING SYSTEM. - Google Patents

Claims (6)

t'ipi.-lPH II. K Λ HL E-: R Π931 \.-Ol "- ·. R ί ·? Ϊιο r ^ sn my reference: 2956 / EPC October 15, 1982 EP 81902882.0 NCR Corporation, World Headquarters, Dayton, OHIO 454-79 ( V.St.A.) Stack for a data processor '0 claims 1. Data processor of the specified type (10), characterized by a plurality of Control registers (18, 26, 28) including one Fetch control register and an execution control register (28), each of said plurality control registers (18, 26, 28) of a corresponding one of the plurality of stages of the data processor is assigned, said plurality of control registers (18, 26, 28) such for receiving a Control memory address is connected that said control memory address is associated with one Microinstruction through each of the plurality of stages _{g5 of} the data processor follows, and a stack (30), the one device for storing (303) a plurality of information units, a counter device (304) generated by a large number of input control signals (PUSH, POP) for address generation is controlled, operationally with said device for storing (303) for addressing said storage device (303) and operationally connected to said storage device Apparatus for storing (303) comprises associated register devices (301, 302) which are operative are connected to said execution control register (28) and operationally to said one Fetch control registers (18) are connected for storing the last one in said device for storing (303) entered information unit, whereby the last information unit for said fetch control register (118) is made immediately available. 2. data processor according to claim 1, characterized in that said device for storage (303) comprises a RAM memory which is used for storing a plurality of information units operated on a last-in-first-out basis. 3. Data processor according to claim 1, characterized in that said Re- O ₀ register devices (301, 302) a multiplexer (301) with a first and second input, said first input operationally connected to an output of said storage device (303) and said second input operationally connected to said execution control register (28) connected, and comprising a counter / register (302), operationally with said multiplexer (301) for receiving said last information unit is connected and operatively connected to said device (303) for transmitting said last information unit to be stored in said device (303) and further operatively connected to said fetch control register (18) for restoring of the last information units mentioned in the fetch control register. 4-. A data processor according to claim 1, characterized in that said counter means (304) comprises a first counter that is operationally connected to said device for storing (303) and by a plurality of input control signals for addressing said device for storing (303) is controlled when a reading of said device for storing (303) by commanding one of said plurality of input control signals and a second Counter operatively connected to said storage device (303) and controlled by said Controlled variety of input control signals ert is for addressing said device for storing (303) "if a write to said storage apparatus through one of said plurality of input control signals be _or is foal. 5. Data processor according to claim 3 »characterized in that said counter / register further responsive to a control signal (INCREMENT), said information unit being stored will. 6. Data processor according to claim 1, characterized in that the plurality of Stages of the data processor an execution stage with a large number of execution registers (22) 5 having said register device (502) is operatively connected to the plurality of execution registers (22). 7- data processor according to any preceding claim, characterized in that said operational connection between the said register devices (301, 302) and said execution control register (28) Having adder (40). 15th