DE60239201D1 - Verfahren zur verwendung eines l2-verzeichnisses, um spekulatives laden in einem mehrprozessorsystem zu ermöglichen - Google Patents

Verfahren zur verwendung eines l2-verzeichnisses, um spekulatives laden in einem mehrprozessorsystem zu ermöglichen

Info

Publication number
DE60239201D1
DE60239201D1 DE60239201T DE60239201T DE60239201D1 DE 60239201 D1 DE60239201 D1 DE 60239201D1 DE 60239201 T DE60239201 T DE 60239201T DE 60239201 T DE60239201 T DE 60239201T DE 60239201 D1 DE60239201 D1 DE 60239201D1
Authority
DE
Germany
Prior art keywords
cache
affected
speculative load
load operations
caches
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60239201T
Other languages
English (en)
Inventor
Shailender Chaudhry
Marc Tremblay
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oracle America Inc
Original Assignee
Oracle America Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oracle America Inc filed Critical Oracle America Inc
Application granted granted Critical
Publication of DE60239201D1 publication Critical patent/DE60239201D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G06F12/0822—Copy directories
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G06F12/0828—Cache consistency protocols using directory methods with concurrent directory accessing, i.e. handling multiple concurrent coherency transactions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/3834—Maintaining memory consistency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Hardware Redundancy (AREA)
  • Multi Processors (AREA)
DE60239201T 2001-06-26 2002-06-26 Verfahren zur verwendung eines l2-verzeichnisses, um spekulatives laden in einem mehrprozessorsystem zu ermöglichen Expired - Lifetime DE60239201D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US30119701P 2001-06-26 2001-06-26
PCT/US2002/022159 WO2003001383A2 (en) 2001-06-26 2002-06-26 Using an l2 directory to facilitate speculative loads in a multiprocessor system

Publications (1)

Publication Number Publication Date
DE60239201D1 true DE60239201D1 (de) 2011-03-31

Family

ID=23162362

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60239201T Expired - Lifetime DE60239201D1 (de) 2001-06-26 2002-06-26 Verfahren zur verwendung eines l2-verzeichnisses, um spekulatives laden in einem mehrprozessorsystem zu ermöglichen

Country Status (8)

Country Link
US (1) US6721855B2 (de)
EP (1) EP1399823B1 (de)
JP (1) JP4050226B2 (de)
KR (1) KR100704089B1 (de)
AT (1) ATE498866T1 (de)
AU (1) AU2002349805A1 (de)
DE (1) DE60239201D1 (de)
WO (1) WO2003001383A2 (de)

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6668308B2 (en) * 2000-06-10 2003-12-23 Hewlett-Packard Development Company, L.P. Scalable architecture based on single-chip multiprocessing
US6990559B2 (en) * 2002-10-03 2006-01-24 Hewlett-Packard Development Company, L.P. Mechanism for resolving ambiguous invalidates in a computer system
JP3988144B2 (ja) 2004-02-23 2007-10-10 日本電気株式会社 ベクトル処理装置、及び、追い越し制御回路
US7769950B2 (en) * 2004-03-24 2010-08-03 Qualcomm Incorporated Cached memory system and cache controller for embedded digital signal processor
US7484045B2 (en) 2004-03-30 2009-01-27 Intel Corporation Store performance in strongly-ordered microprocessor architecture
US7277989B2 (en) 2004-06-22 2007-10-02 Sun Microsystems, Inc. Selectively performing fetches for store operations during speculative execution
US7290116B1 (en) 2004-06-30 2007-10-30 Sun Microsystems, Inc. Level 2 cache index hashing to avoid hot spots
US7519796B1 (en) 2004-06-30 2009-04-14 Sun Microsystems, Inc. Efficient utilization of a store buffer using counters
US7571284B1 (en) * 2004-06-30 2009-08-04 Sun Microsystems, Inc. Out-of-order memory transactions in a fine-grain multithreaded/multi-core processor
US7366829B1 (en) 2004-06-30 2008-04-29 Sun Microsystems, Inc. TLB tag parity checking without CAM read
US7543132B1 (en) 2004-06-30 2009-06-02 Sun Microsystems, Inc. Optimizing hardware TLB reload performance in a highly-threaded processor with multiple page sizes
US9727468B2 (en) * 2004-09-09 2017-08-08 Intel Corporation Resolving multi-core shared cache access conflicts
US7984248B2 (en) * 2004-12-29 2011-07-19 Intel Corporation Transaction based shared data operations in a multiprocessor environment
US7523266B2 (en) 2006-02-06 2009-04-21 Sun Microsystems, Inc. Method and apparatus for enforcing memory reference ordering requirements at the L1 cache level
US20070186056A1 (en) * 2006-02-07 2007-08-09 Bratin Saha Hardware acceleration for a software transactional memory system
US8838906B2 (en) * 2010-01-08 2014-09-16 International Business Machines Corporation Evict on write, a management strategy for a prefetch unit and/or first level cache in a multiprocessor system with speculative execution
JP5471428B2 (ja) * 2009-12-25 2014-04-16 富士通株式会社 情報処理装置およびキャッシュメモリ制御装置
US9507647B2 (en) 2010-01-08 2016-11-29 Globalfoundries Inc. Cache as point of coherence in multiprocessor system
US8825944B2 (en) 2011-05-23 2014-09-02 International Business Machines Corporation Populating strides of tracks to demote from a first cache to a second cache
US8825953B2 (en) 2012-01-17 2014-09-02 International Business Machines Corporation Demoting tracks from a first cache to a second cache by using a stride number ordering of strides in the second cache to consolidate strides in the second cache
US9021201B2 (en) 2012-01-17 2015-04-28 International Business Machines Corporation Demoting partial tracks from a first cache to a second cache
US8825957B2 (en) 2012-01-17 2014-09-02 International Business Machines Corporation Demoting tracks from a first cache to a second cache by using an occupancy of valid tracks in strides in the second cache to consolidate strides in the second cache
US8966178B2 (en) 2012-01-17 2015-02-24 International Business Machines Corporation Populating a first stride of tracks from a first cache to write to a second stride in a second cache
JP5949330B2 (ja) * 2012-08-29 2016-07-06 株式会社リコー 情報処理装置、情報処理方法
US9405690B2 (en) * 2013-08-07 2016-08-02 Oracle International Corporation Method for storing modified instruction data in a shared cache
CN103744800B (zh) * 2013-12-30 2016-09-14 龙芯中科技术有限公司 面向重放机制的缓存操作方法及装置
US10423418B2 (en) 2015-11-30 2019-09-24 International Business Machines Corporation Method for maintaining a branch prediction history table
US10489296B2 (en) 2016-09-22 2019-11-26 International Business Machines Corporation Quality of cache management in a computer
US10620961B2 (en) * 2018-03-30 2020-04-14 Intel Corporation Apparatus and method for speculative conditional move operation

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5611063A (en) * 1996-02-06 1997-03-11 International Business Machines Corporation Method for executing speculative load instructions in high-performance processors
US6418516B1 (en) * 1999-07-30 2002-07-09 International Business Machines Corporation Method and system for managing speculative requests in a multi-level memory hierarchy
US6473833B1 (en) * 1999-07-30 2002-10-29 International Business Machines Corporation Integrated cache and directory structure for multi-level caches
US6606702B1 (en) * 2000-06-06 2003-08-12 International Business Machines Corporation Multiprocessor speculation mechanism with imprecise recycling of storage operations
US6609192B1 (en) * 2000-06-06 2003-08-19 International Business Machines Corporation System and method for asynchronously overlapping storage barrier operations with old and new storage operations

Also Published As

Publication number Publication date
US20020199070A1 (en) 2002-12-26
US6721855B2 (en) 2004-04-13
JP2005520222A (ja) 2005-07-07
KR20040007546A (ko) 2004-01-24
AU2002349805A1 (en) 2003-01-08
EP1399823A2 (de) 2004-03-24
WO2003001383A3 (en) 2003-08-14
JP4050226B2 (ja) 2008-02-20
WO2003001383A2 (en) 2003-01-03
EP1399823B1 (de) 2011-02-16
KR100704089B1 (ko) 2007-04-05
ATE498866T1 (de) 2011-03-15

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