DE60224939D1 - Mehrraten-shared-memory-architektur für die rahmenspeicherung und vermittlung - Google Patents

Mehrraten-shared-memory-architektur für die rahmenspeicherung und vermittlung

Info

Publication number
DE60224939D1
DE60224939D1 DE60224939T DE60224939T DE60224939D1 DE 60224939 D1 DE60224939 D1 DE 60224939D1 DE 60224939 T DE60224939 T DE 60224939T DE 60224939 T DE60224939 T DE 60224939T DE 60224939 D1 DE60224939 D1 DE 60224939D1
Authority
DE
Germany
Prior art keywords
shared memory
rated
communication
memory architecture
frame storage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60224939T
Other languages
English (en)
Other versions
DE60224939T2 (de
Inventor
William J Mitchem
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
McData Corp
Original Assignee
McData Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by McData Corp filed Critical McData Corp
Application granted granted Critical
Publication of DE60224939D1 publication Critical patent/DE60224939D1/de
Publication of DE60224939T2 publication Critical patent/DE60224939T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1689—Synchronisation and timing concerns
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/35—Switches specially adapted for specific applications
    • H04L49/356—Switches specially adapted for specific applications for storage area networks
    • H04L49/357—Fibre channel switches
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/10—Packet switching elements characterised by the switching fabric construction
    • H04L49/103—Packet switching elements characterised by the switching fabric construction using a shared central buffer; using a shared memory
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/25—Routing or path finding in a switch fabric
    • H04L49/253—Routing or path finding in a switch fabric using establishment or release of connections between ports
    • H04L49/254—Centralised controller, i.e. arbitration or scheduling

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Communication Control (AREA)
  • Storing Facsimile Image Data (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Small-Scale Networks (AREA)
  • Multi Processors (AREA)
  • Image Input (AREA)
DE60224939T 2001-08-17 2002-02-27 Mehrraten-shared-memory-architektur für die rahmenspeicherung und vermittlung Expired - Lifetime DE60224939T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/932,223 US7054312B2 (en) 2001-08-17 2001-08-17 Multi-rate shared memory architecture for frame storage and switching
US932223 2001-08-17
PCT/US2002/006228 WO2003017115A1 (en) 2001-08-17 2002-02-27 Multi-rate shared memory architecture for frame storage and switching

Publications (2)

Publication Number Publication Date
DE60224939D1 true DE60224939D1 (de) 2008-03-20
DE60224939T2 DE60224939T2 (de) 2009-02-05

Family

ID=25461968

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60224939T Expired - Lifetime DE60224939T2 (de) 2001-08-17 2002-02-27 Mehrraten-shared-memory-architektur für die rahmenspeicherung und vermittlung

Country Status (5)

Country Link
US (2) US7054312B2 (de)
EP (1) EP1425672B1 (de)
AT (1) ATE385591T1 (de)
DE (1) DE60224939T2 (de)
WO (1) WO2003017115A1 (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3897994B2 (ja) * 2001-05-31 2007-03-28 富士通株式会社 スイッチ装置およびデータ転送システム
US7814280B2 (en) * 2005-01-12 2010-10-12 Fulcrum Microsystems Inc. Shared-memory switch fabric architecture
US9226151B2 (en) 2006-04-04 2015-12-29 Jasper Wireless, Inc. System and method for enabling a wireless device with customer-specific services
US7525968B1 (en) * 2006-03-16 2009-04-28 Qlogic Corporation Method and system for auto routing fibre channel class F frames in a fibre channel fabric
US7916718B2 (en) 2007-04-19 2011-03-29 Fulcrum Microsystems, Inc. Flow and congestion control in switch architectures for multi-hop, memory efficient fabrics
US8125991B1 (en) * 2007-07-31 2012-02-28 Hewlett-Packard Development Company, L.P. Network switch using managed addresses for fast route lookup
CN101257034B (zh) * 2008-04-10 2011-05-18 中国科学院长春光学精密机械与物理研究所 可提高分辨率的ccd像元
JP5831035B2 (ja) * 2011-08-18 2015-12-09 富士通株式会社 インタフェースモジュール，通信装置，及び通信方法
US10152262B2 (en) * 2016-05-03 2018-12-11 Micron Technology, Inc. Memory access techniques in memory devices with multiple partitions
US11923978B1 (en) * 2021-05-13 2024-03-05 Marvell Asia Pte Ltd Multi-port transceiver

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4700391A (en) 1983-06-03 1987-10-13 The Variable Speech Control Company ("Vsc") Method and apparatus for pitch controlled voice signal processing
US5535197A (en) * 1991-09-26 1996-07-09 Ipc Information Systems, Inc. Shared buffer switching module
US5603064A (en) * 1994-10-27 1997-02-11 Hewlett-Packard Company Channel module for a fiber optic switch with bit sliced memory architecture for data frame storage
US5513139A (en) 1994-11-04 1996-04-30 General Instruments Corp. Random access memory with circuitry for concurrently and sequentially writing-in and reading-out data at different rates
US5894481A (en) * 1996-09-11 1999-04-13 Mcdata Corporation Fiber channel switch employing distributed queuing
US6031842A (en) 1996-09-11 2000-02-29 Mcdata Corporation Low latency shared memory switch architecture
JPH10150446A (ja) * 1996-11-19 1998-06-02 Fujitsu Ltd Ａｔｍ交換システム
US6061358A (en) 1997-02-13 2000-05-09 Mcdata Corporation Data communication system utilizing a scalable, non-blocking, high bandwidth central memory controller and method
US6160813A (en) * 1997-03-21 2000-12-12 Brocade Communications Systems, Inc. Fibre channel switching system and method
US6118835A (en) 1997-09-05 2000-09-12 Lucent Technologies, Inc. Apparatus and method of synchronizing two logic blocks operating at different rates
US6065087A (en) 1998-05-21 2000-05-16 Hewlett-Packard Company Architecture for a high-performance network/bus multiplexer interconnecting a network and a bus that transport data using multiple protocols
US6138185A (en) 1998-10-29 2000-10-24 Mcdata Corporation High performance crossbar switch
US6697359B1 (en) * 1999-07-02 2004-02-24 Ancor Communications, Inc. High performance switch fabric element and switch systems
US7301956B2 (en) * 2001-05-10 2007-11-27 Brocade Communications Systems, Inc. System and method for storing and retrieving multi-speed data streams within a network switch
US7042842B2 (en) * 2001-06-13 2006-05-09 Computer Network Technology Corporation Fiber channel switch

Also Published As

Publication number Publication date
ATE385591T1 (de) 2008-02-15
US20030046496A1 (en) 2003-03-06
US20070002861A1 (en) 2007-01-04
EP1425672A1 (de) 2004-06-09
DE60224939T2 (de) 2009-02-05
EP1425672A4 (de) 2006-07-19
US7054312B2 (en) 2006-05-30
EP1425672B1 (de) 2008-02-06
WO2003017115A1 (en) 2003-02-27

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Legal Events

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