DE60211684D1 - Verfahren und Einrichtung für die parallele Synchronisation von mehreren seriellen Datenströmen - Google Patents

Verfahren und Einrichtung für die parallele Synchronisation von mehreren seriellen Datenströmen

Info

Publication number
DE60211684D1
DE60211684D1 DE60211684T DE60211684T DE60211684D1 DE 60211684 D1 DE60211684 D1 DE 60211684D1 DE 60211684 T DE60211684 T DE 60211684T DE 60211684 T DE60211684 T DE 60211684T DE 60211684 D1 DE60211684 D1 DE 60211684D1
Authority
DE
Germany
Prior art keywords
serial data
data streams
multiple serial
parallel synchronization
synchronization
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60211684T
Other languages
English (en)
Other versions
DE60211684T2 (de
Inventor
Iain Robertson
Richard Simpson
Michael Hardwood
Andy Joy
Robert Simpson
Richard Ward
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of DE60211684D1 publication Critical patent/DE60211684D1/de
Application granted granted Critical
Publication of DE60211684T2 publication Critical patent/DE60211684T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/14—Channel dividing arrangements, i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/002—Arrangements for synchronising receiver with transmitter correction of synchronization errors correction by interpolation
    • H04L7/0025—Arrangements for synchronising receiver with transmitter correction of synchronization errors correction by interpolation interpolation of clock signal

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Power Engineering (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
DE60211684T 2002-07-22 2002-07-22 Verfahren und Einrichtung für die parallele Synchronisation von mehreren seriellen Datenströmen Expired - Lifetime DE60211684T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP02255101A EP1385306B1 (de) 2002-07-22 2002-07-22 Verfahren und Einrichtung für die parallele Synchronisation von mehreren seriellen Datenströmen

Publications (2)

Publication Number Publication Date
DE60211684D1 true DE60211684D1 (de) 2006-06-29
DE60211684T2 DE60211684T2 (de) 2007-05-10

Family

ID=29797306

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60211684T Expired - Lifetime DE60211684T2 (de) 2002-07-22 2002-07-22 Verfahren und Einrichtung für die parallele Synchronisation von mehreren seriellen Datenströmen

Country Status (3)

Country Link
US (1) US7233628B2 (de)
EP (1) EP1385306B1 (de)
DE (1) DE60211684T2 (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE60211684T2 (de) 2002-07-22 2007-05-10 Texas Instruments Inc., Dallas Verfahren und Einrichtung für die parallele Synchronisation von mehreren seriellen Datenströmen
SG161294A1 (en) * 2005-04-18 2010-05-27 Agency Science Tech & Res Time delay apparatus
US9178690B2 (en) * 2013-10-03 2015-11-03 Qualcomm Incorporated N factorial dual data rate clock and data recovery
US9313058B2 (en) 2013-03-07 2016-04-12 Qualcomm Incorporated Compact and fast N-factorial single data rate clock and data recovery circuits
US9363071B2 (en) 2013-03-07 2016-06-07 Qualcomm Incorporated Circuit to recover a clock signal from multiple wire data signals that changes state every state cycle and is immune to data inter-lane skew as well as data state transition glitches
US9374216B2 (en) 2013-03-20 2016-06-21 Qualcomm Incorporated Multi-wire open-drain link with data symbol transition based clocking
US9203599B2 (en) 2014-04-10 2015-12-01 Qualcomm Incorporated Multi-lane N-factorial (N!) and other multi-wire communication systems
US9755818B2 (en) * 2013-10-03 2017-09-05 Qualcomm Incorporated Method to enhance MIPI D-PHY link rate with minimal PHY changes and no protocol changes
US9735948B2 (en) 2013-10-03 2017-08-15 Qualcomm Incorporated Multi-lane N-factorial (N!) and other multi-wire communication systems
KR102298160B1 (ko) * 2015-08-13 2021-09-03 삼성전자주식회사 반도체 장치 및 이를 포함하는 통신 시스템
US9413524B1 (en) * 2015-10-20 2016-08-09 Xilinx, Inc. Dynamic gain clock data recovery in a receiver
KR102674031B1 (ko) 2019-05-13 2024-06-12 삼성전자주식회사 메모리 컨트롤러, 이를 포함하는 메모리 시스템 및 그 동작 방법
US11165554B1 (en) * 2020-10-27 2021-11-02 Cadence Design Systems, Inc. Transmitter test using phase-lock loop

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11122117A (ja) * 1997-10-15 1999-04-30 Sony Corp シリアル・パラレル変換装置
US6363129B1 (en) * 1998-11-09 2002-03-26 Broadcom Corporation Timing recovery system for a multi-pair gigabit transceiver
EP0996262A1 (de) * 1998-10-22 2000-04-26 Texas Instruments France Kommunikationssystem mit mehreren synchronisierten Datenverbindungen
US6239629B1 (en) * 1999-04-29 2001-05-29 Agilent Technologies, Inc. Signal comparison system and method for detecting and correcting timing errors
US7035368B2 (en) * 2002-03-18 2006-04-25 Texas Instruments Incorporated High speed parallel link receiver
DE60211684T2 (de) 2002-07-22 2007-05-10 Texas Instruments Inc., Dallas Verfahren und Einrichtung für die parallele Synchronisation von mehreren seriellen Datenströmen

Also Published As

Publication number Publication date
US20040052322A1 (en) 2004-03-18
EP1385306B1 (de) 2006-05-24
DE60211684T2 (de) 2007-05-10
EP1385306A1 (de) 2004-01-28
US7233628B2 (en) 2007-06-19

Similar Documents

Publication Publication Date Title
DE60331966D1 (de) Verfahren und Vorrichtung zur Synchronisation von Basisstationen
DE50302793D1 (de) Spitzensystem und Verfahren für ein solches
DE60324376D1 (de) Halbleiterbauelement und Verfahren zu dessen Herstellung
DE60328951D1 (de) Bilderzeugungsgerät und Verfahren
DE602004002195D1 (de) Verfahren und apparat für die ablauffolgesteuerung von paketen
AU2003296957A8 (en) Apparatus and method for skipping songs without delay
AU2003293204A8 (en) Method and apparatus for combining multiple search workers
DE60318588D1 (de) Produktionsinformations- und fehlerbehebungssystem und verfahren
DE60326651D1 (de) Verfahren und vorrichtung zur synchronisierung von trainingssequenzen
DE602004025322D1 (de) Verfahren und Vorrichtung für die Spinnvliesherstellung
DE50310782D1 (de) Piezoaktor und verfahren zu dessen herstellung
DE60211684D1 (de) Verfahren und Einrichtung für die parallele Synchronisation von mehreren seriellen Datenströmen
DE50302268D1 (de) Mikroskopiesystem und Mikroskopieverfahren für mehrere Beobachter
DE60328788D1 (de) Verfahren und einrichtung zum verknüpfen von multimedia-daten
DE60333896D1 (de) Verfahren und Vorrichtung für Rückwärtswiedergabe
DE602004003632D1 (de) Turbidimetrisches Immuntestverfahren und zugehörige Vorrichtung
DE60225508D1 (de) Leiterplatte und verfahren zu ihrer herstellung
DE60219157D1 (de) Verfahren und Einrichtung für die parallele Synchronisation von mehreren seriellen Datenströmen
DE60232305D1 (de) Vorrichtung und verfahren zur synchronisierung von mehreren alarmgeräten
DE602004031350D1 (de) Penamkristall und verfahren zu dessen herstellung
DE60319773D1 (de) Vorrichtung zum Unterstützen von tragbaren Endgeräten, Verfahren zur Datensynchronisation, und tragbares Endgerät
DE60219156D1 (de) Verfahren und Einrichtung für die parallele Synchronisation von mehreren seriellen Datenströmen
DE60303891D1 (de) Kameraeinheit und Verfahren zu deren Herstellung
DE60327081D1 (de) Synchronisationssystem und verfahren für audiovisuelle programme, assoziierte einrichtungen und verfahren
DE60123743D1 (de) Verfahren und Vorrichtung zum Multiplexen von Daten

Legal Events

Date Code Title Description
8364 No opposition during term of opposition