DE60206150D1 - Input circuit for a multiplexer with a DLL phase detector - Google Patents

Input circuit for a multiplexer with a DLL phase detector

Info

Publication number
DE60206150D1
DE60206150D1 DE60206150T DE60206150T DE60206150D1 DE 60206150 D1 DE60206150 D1 DE 60206150D1 DE 60206150 T DE60206150 T DE 60206150T DE 60206150 T DE60206150 T DE 60206150T DE 60206150 D1 DE60206150 D1 DE 60206150D1
Authority
DE
Germany
Prior art keywords
flop
flip
multiplexer
signal
input circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60206150T
Other languages
German (de)
Other versions
DE60206150T2 (en
Inventor
Berthold Wedding
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alcatel Lucent SAS
Original Assignee
Alcatel SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alcatel SA filed Critical Alcatel SA
Application granted granted Critical
Publication of DE60206150D1 publication Critical patent/DE60206150D1/en
Publication of DE60206150T2 publication Critical patent/DE60206150T2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D13/00—Circuits for comparing the phase or frequency of two mutually-independent oscillations
    • H03D13/003—Circuits for comparing the phase or frequency of two mutually-independent oscillations in which both oscillations are converted by logic means into pulses which are applied to filtering or integrating means
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/091—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/04—Distributors combined with modulators or demodulators
    • H04J3/047—Distributors with transistors or integrated circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/0033—Correction by delay
    • H04L7/0037—Delay of clock signal

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Pulse Circuits (AREA)

Abstract

An input circuit, in particular for a multiplexer, for phase controlling of a data input signal with a clock signal, comprises a flip-flop (1), wherein the data signal is fed to a clock input of the flip-flop and the clock signal is fed to the data input of the flip-flop, and wherein the data output of the flip-flop is used as a control signal of a locked loop. <??>An advantage of the invention is, that it is of simple design which makes the invention especially useful for high frequencies. The data output of the flip-flop is dependent on the phase relationship of the data input signal with respect to the clock signal. <IMAGE>
DE60206150T 2002-07-12 2002-07-12 Input circuit for a multiplexer with a DLL phase detector Expired - Lifetime DE60206150T2 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP02360209A EP1381153B1 (en) 2002-07-12 2002-07-12 Multiplexer input circuit with DLL phase detector

Publications (2)

Publication Number Publication Date
DE60206150D1 true DE60206150D1 (en) 2005-10-20
DE60206150T2 DE60206150T2 (en) 2006-01-26

Family

ID=29724586

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60206150T Expired - Lifetime DE60206150T2 (en) 2002-07-12 2002-07-12 Input circuit for a multiplexer with a DLL phase detector

Country Status (5)

Country Link
US (1) US20040008733A1 (en)
EP (1) EP1381153B1 (en)
CN (1) CN1472886A (en)
AT (1) ATE304747T1 (en)
DE (1) DE60206150T2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3938917B2 (en) * 2003-11-12 2007-06-27 沖電気工業株式会社 Semiconductor integrated circuit device
JP4271623B2 (en) * 2004-06-17 2009-06-03 富士通株式会社 Clock adjustment apparatus and method
US9859874B2 (en) 2015-10-30 2018-01-02 Sandisk Technologies Llc Loop delay optimization for multi-voltage self-synchronous systems
US10366383B2 (en) * 2016-03-31 2019-07-30 Square, Inc. Combined reliable and unreliable data transmission

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3805180A (en) * 1972-12-27 1974-04-16 A Widmer Binary-coded signal timing recovery circuit
JPH04260239A (en) * 1991-02-15 1992-09-16 Nec Corp Timing extracting circuit
US5272390A (en) * 1991-09-23 1993-12-21 Digital Equipment Corporation Method and apparatus for clock skew reduction through absolute delay regulation
US5457718A (en) * 1992-03-02 1995-10-10 International Business Machines Corporation Compact phase recovery scheme using digital circuits
DE4229148A1 (en) * 1992-09-01 1994-03-03 Sel Alcatel Ag Digital phase comparator and phase locked loop
JPH06152556A (en) * 1992-10-30 1994-05-31 Ando Electric Co Ltd Data multiplex circuit
US5799048A (en) * 1996-04-17 1998-08-25 Sun Microsystems, Inc. Phase detector for clock synchronization and recovery
US6125157A (en) * 1997-02-06 2000-09-26 Rambus, Inc. Delay-locked loop circuitry for clock delay adjustment
GB2333916B (en) * 1998-01-09 2001-08-01 Plessey Semiconductors Ltd A phase detector
US20020085656A1 (en) * 2000-08-30 2002-07-04 Lee Sang-Hyun Data recovery using data eye tracking
US6759881B2 (en) * 2002-03-22 2004-07-06 Rambus Inc. System with phase jumping locked loop circuit

Also Published As

Publication number Publication date
EP1381153B1 (en) 2005-09-14
US20040008733A1 (en) 2004-01-15
EP1381153A1 (en) 2004-01-14
DE60206150T2 (en) 2006-01-26
ATE304747T1 (en) 2005-09-15
CN1472886A (en) 2004-02-04

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: ALCATEL LUCENT, PARIS, FR