DE602007009861D1 - Verfahren und vorrichtung zur erkennung eines unterprogrammaufrufes - Google Patents

Verfahren und vorrichtung zur erkennung eines unterprogrammaufrufes

Info

Publication number
DE602007009861D1
DE602007009861D1 DE602007009861T DE602007009861T DE602007009861D1 DE 602007009861 D1 DE602007009861 D1 DE 602007009861D1 DE 602007009861 T DE602007009861 T DE 602007009861T DE 602007009861 T DE602007009861 T DE 602007009861T DE 602007009861 D1 DE602007009861 D1 DE 602007009861D1
Authority
DE
Germany
Prior art keywords
sub
detecting
program request
input
receiving
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602007009861T
Other languages
English (en)
Inventor
Micheal William Morrow
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of DE602007009861D1 publication Critical patent/DE602007009861D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
    • G06F9/30054—Unconditional branch instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
    • G06F9/3806—Instruction prefetching for branches, e.g. hedging, branch folding using address prediction, e.g. return stack, branch history buffer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Advance Control (AREA)
  • Communication Control (AREA)
  • Debugging And Monitoring (AREA)
DE602007009861T 2006-11-28 2007-11-27 Verfahren und vorrichtung zur erkennung eines unterprogrammaufrufes Active DE602007009861D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/563,943 US7444501B2 (en) 2006-11-28 2006-11-28 Methods and apparatus for recognizing a subroutine call
PCT/US2007/085574 WO2008067277A2 (en) 2006-11-28 2007-11-27 Methods and apparatus for recognizing a subroutine call

Publications (1)

Publication Number Publication Date
DE602007009861D1 true DE602007009861D1 (de) 2010-11-25

Family

ID=39465182

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602007009861T Active DE602007009861D1 (de) 2006-11-28 2007-11-27 Verfahren und vorrichtung zur erkennung eines unterprogrammaufrufes

Country Status (13)

Country Link
US (1) US7444501B2 (de)
EP (1) EP2087420B1 (de)
JP (1) JP2010511251A (de)
KR (1) KR20090094335A (de)
CN (1) CN101535951A (de)
AT (1) ATE484795T1 (de)
BR (1) BRPI0719371A2 (de)
CA (1) CA2668584A1 (de)
DE (1) DE602007009861D1 (de)
ES (1) ES2351894T3 (de)
MX (1) MX2009005584A (de)
RU (1) RU2009124438A (de)
WO (1) WO2008067277A2 (de)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4836903B2 (ja) * 2007-09-13 2011-12-14 株式会社東芝 マイクロプロセッサ制御装置並びにその方法およびプログラム
US8694760B2 (en) * 2009-05-19 2014-04-08 Panasonic Corporation Branch prediction using a leading value of a call stack storing function arguments
US20140025894A1 (en) * 2012-07-18 2014-01-23 Electronics And Telecommunications Research Institute Processor using branch instruction execution cache and method of operating the same
CN103795738A (zh) * 2012-10-26 2014-05-14 苏州工业园区新宏博通讯科技有限公司 一种采集终端及应用该采集终端的远程监控系统
US10209992B2 (en) * 2014-04-25 2019-02-19 Avago Technologies International Sales Pte. Limited System and method for branch prediction using two branch history tables and presetting a global branch history register
US10908902B2 (en) * 2016-05-26 2021-02-02 International Business Machines Corporation Distance based branch prediction and detection of potential call and potential return instructions
GB2563384B (en) * 2017-06-07 2019-12-25 Advanced Risc Mach Ltd Programmable instruction buffering
US10884929B2 (en) 2017-09-19 2021-01-05 International Business Machines Corporation Set table of contents (TOC) register instruction
US10725918B2 (en) 2017-09-19 2020-07-28 International Business Machines Corporation Table of contents cache entry having a pointer for a range of addresses
US10705973B2 (en) 2017-09-19 2020-07-07 International Business Machines Corporation Initializing a data structure for use in predicting table of contents pointer values
US11061575B2 (en) 2017-09-19 2021-07-13 International Business Machines Corporation Read-only table of contents register
US10620955B2 (en) * 2017-09-19 2020-04-14 International Business Machines Corporation Predicting a table of contents pointer value responsive to branching to a subroutine
US10896030B2 (en) 2017-09-19 2021-01-19 International Business Machines Corporation Code generation relating to providing table of contents pointer values
US10713050B2 (en) 2017-09-19 2020-07-14 International Business Machines Corporation Replacing Table of Contents (TOC)-setting instructions in code with TOC predicting instructions
CN109960607B (zh) * 2017-12-22 2021-04-20 龙芯中科技术股份有限公司 预测栈的错误恢复方法、装置及存储介质

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4831517A (en) * 1986-10-10 1989-05-16 International Business Machines Corporation Branch and return on address instruction and methods and apparatus for implementing same in a digital data processing system
US6157999A (en) * 1997-06-03 2000-12-05 Motorola Inc. Data processing system having a synchronizing link stack and method thereof
US5974543A (en) * 1998-01-23 1999-10-26 International Business Machines Corporation Apparatus and method for performing subroutine call and return operations
JP3513038B2 (ja) * 1998-12-10 2004-03-31 富士通株式会社 命令フェッチ制御装置
JP3723019B2 (ja) * 1999-09-29 2005-12-07 富士通株式会社 サブルーチンリターン相当の命令の分岐予測を行う装置および方法
US6910124B1 (en) * 2000-05-02 2005-06-21 International Business Machines Corporation Apparatus and method for recovering a link stack from mis-speculation
US6973563B1 (en) * 2002-01-04 2005-12-06 Advanced Micro Devices, Inc. Microprocessor including return prediction unit configured to determine whether a stored return address corresponds to more than one call instruction
JP2007041837A (ja) * 2005-08-03 2007-02-15 Nec Electronics Corp 命令プリフェッチ装置及び命令プリフェッチ方法
US7478228B2 (en) * 2006-08-31 2009-01-13 Qualcomm Incorporated Apparatus for generating return address predictions for implicit and explicit subroutine calls

Also Published As

Publication number Publication date
JP2010511251A (ja) 2010-04-08
ES2351894T3 (es) 2011-02-11
MX2009005584A (es) 2009-06-15
RU2009124438A (ru) 2011-01-10
US7444501B2 (en) 2008-10-28
US20080126770A1 (en) 2008-05-29
WO2008067277A2 (en) 2008-06-05
EP2087420A2 (de) 2009-08-12
KR20090094335A (ko) 2009-09-04
WO2008067277A3 (en) 2008-09-25
EP2087420B1 (de) 2010-10-13
BRPI0719371A2 (pt) 2014-02-11
CN101535951A (zh) 2009-09-16
CA2668584A1 (en) 2008-06-05
ATE484795T1 (de) 2010-10-15

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