DE602007002718D1 - Prozessor und verfahren für einen prozessor - Google Patents

Prozessor und verfahren für einen prozessor

Info

Publication number
DE602007002718D1
DE602007002718D1 DE602007002718T DE602007002718T DE602007002718D1 DE 602007002718 D1 DE602007002718 D1 DE 602007002718D1 DE 602007002718 T DE602007002718 T DE 602007002718T DE 602007002718 T DE602007002718 T DE 602007002718T DE 602007002718 D1 DE602007002718 D1 DE 602007002718D1
Authority
DE
Germany
Prior art keywords
processor
credit parameter
value
data packet
admitted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602007002718T
Other languages
English (en)
Inventor
Jakob Carlstroem
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xelerated AB
Original Assignee
Xelerated AB
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xelerated AB filed Critical Xelerated AB
Publication of DE602007002718D1 publication Critical patent/DE602007002718D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H04L47/215—Flow control; Congestion control using token-bucket

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Hardware Redundancy (AREA)
DE602007002718T 2006-06-22 2007-06-12 Prozessor und verfahren für einen prozessor Active DE602007002718D1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
SE0601389 2006-06-22
US81709506P 2006-06-29 2006-06-29
PCT/EP2007/055777 WO2007147756A1 (en) 2006-06-22 2007-06-12 A processor and a method for a processor

Publications (1)

Publication Number Publication Date
DE602007002718D1 true DE602007002718D1 (de) 2009-11-19

Family

ID=38669965

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602007002718T Active DE602007002718D1 (de) 2006-06-22 2007-06-12 Prozessor und verfahren für einen prozessor

Country Status (6)

Country Link
US (3) US8171478B2 (de)
EP (1) EP2036267B1 (de)
AT (1) ATE445277T1 (de)
DE (1) DE602007002718D1 (de)
TW (1) TWI435574B (de)
WO (1) WO2007147756A1 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102084628B (zh) 2008-04-24 2014-12-03 马维尔国际有限公司 通信量管理器和用于通信量管理器的方法
US8483194B1 (en) * 2009-01-21 2013-07-09 Aerohive Networks, Inc. Airtime-based scheduling
JP5492709B2 (ja) * 2010-09-06 2014-05-14 株式会社日立製作所 帯域制御方法及び帯域制御装置
US8442056B2 (en) 2011-06-28 2013-05-14 Marvell International Ltd. Scheduling packets in a packet-processing pipeline
US9280503B2 (en) * 2013-04-12 2016-03-08 Apple Inc. Round robin arbiter handling slow transaction sources and preventing block
US10649796B2 (en) * 2014-06-27 2020-05-12 Amazon Technologies, Inc. Rolling resource credits for scheduling of virtual computer resources
US9900253B2 (en) * 2014-08-28 2018-02-20 Cavium, Inc. Phantom queue link level load balancing system, method and device

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2367574A1 (en) * 1999-03-18 2000-09-28 Peng Zhang Overload control method for a packet-switched network
US6757249B1 (en) 1999-10-14 2004-06-29 Nokia Inc. Method and apparatus for output rate regulation and control associated with a packet pipeline
US6992984B1 (en) * 2000-03-07 2006-01-31 Lucent Technologies Inc. Credit-based adaptive flow control for multi-stage multi-dimensional switching architecture
US6950395B1 (en) * 2000-12-31 2005-09-27 Cisco Technology, Inc. Method and apparatus for a token bucket metering or policing system with a delayed filling scheme
WO2003019394A1 (en) * 2001-08-24 2003-03-06 Intel Corporation A general input/output architecture, protocol and related methods to support legacy interrupts
US6798741B2 (en) 2001-12-05 2004-09-28 Riverstone Networks, Inc. Method and system for rate shaping in packet-based computer networks
US7447155B2 (en) 2002-06-17 2008-11-04 Intel Corporation Guaranteed service in a data network
AU2003245225A1 (en) 2002-07-19 2004-02-09 Xelerated Ab Method and apparatus for pipelined processing of data packets
US6970426B1 (en) 2003-05-14 2005-11-29 Extreme Networks Rate color marker
TWI263429B (en) 2004-06-30 2006-10-01 Reti Corp System and method for correlated token bucket shapers
US8250231B2 (en) 2004-12-22 2012-08-21 Marvell International Ltd. Method for reducing buffer capacity in a pipeline processor

Also Published As

Publication number Publication date
EP2036267B1 (de) 2009-10-07
US8997105B2 (en) 2015-03-31
US20090183164A1 (en) 2009-07-16
ATE445277T1 (de) 2009-10-15
TW200818781A (en) 2008-04-16
US8171478B2 (en) 2012-05-01
EP2036267A1 (de) 2009-03-18
US20130326530A1 (en) 2013-12-05
US20120210327A1 (en) 2012-08-16
WO2007147756A1 (en) 2007-12-27
TWI435574B (zh) 2014-04-21
US8522246B2 (en) 2013-08-27

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