DE602006015945D1 - Steuerung von ausserreihenfolge-ausführungs-pipelines unter verwendung von versatzparametern - Google Patents

Steuerung von ausserreihenfolge-ausführungs-pipelines unter verwendung von versatzparametern

Info

Publication number
DE602006015945D1
DE602006015945D1 DE602006015945T DE602006015945T DE602006015945D1 DE 602006015945 D1 DE602006015945 D1 DE 602006015945D1 DE 602006015945 T DE602006015945 T DE 602006015945T DE 602006015945 T DE602006015945 T DE 602006015945T DE 602006015945 D1 DE602006015945 D1 DE 602006015945D1
Authority
DE
Germany
Prior art keywords
pipelines
offset parameters
controlling outside
outside sequence
sequence
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602006015945T
Other languages
English (en)
Inventor
Roger Arnold
Neil Stuart Hastie
Erik Norden
Robert E Ober
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of DE602006015945D1 publication Critical patent/DE602006015945D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/3017—Runtime instruction translation, e.g. macros
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3853—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution of compound instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
    • G06F9/3873—Variable length pipelines, e.g. elastic pipeline

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
DE602006015945T 2005-05-16 2006-05-16 Steuerung von ausserreihenfolge-ausführungs-pipelines unter verwendung von versatzparametern Active DE602006015945D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/130,552 US20060259742A1 (en) 2005-05-16 2005-05-16 Controlling out of order execution pipelines using pipeline skew parameters
PCT/EP2006/062356 WO2006122941A2 (en) 2005-05-16 2006-05-16 Controlling out of order execution pipelines using skew parameters

Publications (1)

Publication Number Publication Date
DE602006015945D1 true DE602006015945D1 (de) 2010-09-16

Family

ID=36607601

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602006015945T Active DE602006015945D1 (de) 2005-05-16 2006-05-16 Steuerung von ausserreihenfolge-ausführungs-pipelines unter verwendung von versatzparametern

Country Status (4)

Country Link
US (1) US20060259742A1 (de)
EP (1) EP1886216B1 (de)
DE (1) DE602006015945D1 (de)
WO (1) WO2006122941A2 (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7454598B2 (en) * 2005-05-16 2008-11-18 Infineon Technologies Ag Controlling out of order execution pipelines issue tagging
US8099583B2 (en) * 2006-08-23 2012-01-17 Axis Semiconductor, Inc. Method of and apparatus and architecture for real time signal processing by switch-controlled programmable processor configuring and flexible pipeline and parallel processing
US8078833B2 (en) * 2008-05-29 2011-12-13 Axis Semiconductor, Inc. Microprocessor with highly configurable pipeline and executional unit internal hierarchal structures, optimizable for different types of computational functions
US8181003B2 (en) * 2008-05-29 2012-05-15 Axis Semiconductor, Inc. Instruction set design, control and communication in programmable microprocessor cores and the like
JP2011191906A (ja) * 2010-03-12 2011-09-29 Fujitsu Ltd データ記憶装置、データ監視装置、制御方法及びプログラム
US8635501B2 (en) * 2011-07-25 2014-01-21 Microsoft Corporation Detecting memory hazards in parallel computing
US20150261542A1 (en) * 2014-03-14 2015-09-17 Arm Limited Data processing apparatus and method for performing data processing operation with a conditional processing step
US10419537B1 (en) 2016-03-24 2019-09-17 EMC IP Holding Company LLC Architecture for a converged compute and file system within network-attached storage clusters
US10331630B1 (en) 2016-03-24 2019-06-25 EMC IP Holding Company LLC Systems and methods for file triggers in a converged compute and file system
US10534616B2 (en) 2017-10-06 2020-01-14 International Business Machines Corporation Load-hit-load detection in an out-of-order processor
US10417002B2 (en) 2017-10-06 2019-09-17 International Business Machines Corporation Hazard detection of out-of-order execution of load and store instructions in processors without using real addresses
US10606591B2 (en) 2017-10-06 2020-03-31 International Business Machines Corporation Handling effective address synonyms in a load-store unit that operates without address translation
US10394558B2 (en) 2017-10-06 2019-08-27 International Business Machines Corporation Executing load-store operations without address translation hardware per load-store unit port
US11175924B2 (en) 2017-10-06 2021-11-16 International Business Machines Corporation Load-store unit with partitioned reorder queues with single cam port
US10565036B1 (en) 2019-02-14 2020-02-18 Axis Semiconductor, Inc. Method of synchronizing host and coprocessor operations via FIFO communication
US20240220268A1 (en) * 2023-01-04 2024-07-04 Mercedes-Benz Group AG System, device and/or method for processing signal streams

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5511172A (en) * 1991-11-15 1996-04-23 Matsushita Electric Co. Ind, Ltd. Speculative execution processor
US5941983A (en) * 1997-06-24 1999-08-24 Hewlett-Packard Company Out-of-order execution using encoded dependencies between instructions in queues to determine stall values that control issurance of instructions from the queues
JP2002544588A (ja) * 1999-05-06 2002-12-24 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ データ処理装置、ロード又は格納命令を実行する方法、及び、プログラムをコンパイルする方法
US6859873B2 (en) * 2001-06-08 2005-02-22 Infineon Technologies Ag Variable length instruction pipeline
US7203817B2 (en) * 2001-09-24 2007-04-10 Broadcom Corporation Power consumption reduction in a pipeline by stalling instruction issue on a load miss
GB2382422A (en) * 2001-11-26 2003-05-28 Infineon Technologies Ag Switching delay stages into and out of a pipeline to increase or decrease its effective length
US7139003B1 (en) * 2003-12-15 2006-11-21 Nvidia Corporation Methods of processing graphics data including reading and writing buffers
US20050216900A1 (en) * 2004-03-29 2005-09-29 Xiaohua Shi Instruction scheduling
US7730282B2 (en) * 2004-08-11 2010-06-01 International Business Machines Corporation Method and apparatus for avoiding data dependency hazards in a microprocessor pipeline architecture using a multi-bit age vector
US20060095732A1 (en) * 2004-08-30 2006-05-04 Tran Thang M Processes, circuits, devices, and systems for scoreboard and other processor improvements
US7454598B2 (en) * 2005-05-16 2008-11-18 Infineon Technologies Ag Controlling out of order execution pipelines issue tagging

Also Published As

Publication number Publication date
WO2006122941A2 (en) 2006-11-23
US20060259742A1 (en) 2006-11-16
WO2006122941A3 (en) 2007-06-14
EP1886216B1 (de) 2010-08-04
EP1886216A2 (de) 2008-02-13

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