DE602006013444D1 - Verfahren und System zur Steuerung von Datensynchronisation in FIFO-Speichern und zugehöriger Synchronisierer - Google Patents

Verfahren und System zur Steuerung von Datensynchronisation in FIFO-Speichern und zugehöriger Synchronisierer

Info

Publication number
DE602006013444D1
DE602006013444D1 DE602006013444T DE602006013444T DE602006013444D1 DE 602006013444 D1 DE602006013444 D1 DE 602006013444D1 DE 602006013444 T DE602006013444 T DE 602006013444T DE 602006013444 T DE602006013444 T DE 602006013444T DE 602006013444 D1 DE602006013444 D1 DE 602006013444D1
Authority
DE
Germany
Prior art keywords
data synchronization
controlling data
fifo memories
synchronizers
associated synchronizers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE602006013444T
Other languages
English (en)
Inventor
Riccardo Condorelli
Giovanni Auditore
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
STMicroelectronics SRL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SRL filed Critical STMicroelectronics SRL
Publication of DE602006013444D1 publication Critical patent/DE602006013444D1/de
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
    • G06F5/12—Means for monitoring the fill level; Means for resolving contention, i.e. conflicts between simultaneous enqueue and dequeue operations
    • G06F5/14—Means for monitoring the fill level; Means for resolving contention, i.e. conflicts between simultaneous enqueue and dequeue operations for overflow or underflow handling, e.g. full or empty flags
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2205/00—Indexing scheme relating to group G06F5/00; Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F2205/10—Indexing scheme relating to groups G06F5/10 - G06F5/14
    • G06F2205/102—Avoiding metastability, i.e. preventing hazards, e.g. by using Gray code counters

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
DE602006013444T 2006-07-11 2006-07-11 Verfahren und System zur Steuerung von Datensynchronisation in FIFO-Speichern und zugehöriger Synchronisierer Expired - Fee Related DE602006013444D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP06116947A EP1879101B1 (de) 2006-07-11 2006-07-11 Verfahren und System zur Steuerung von Datensynchronisation in FIFO-Speichern und zugehöriger Synchronisierer

Publications (1)

Publication Number Publication Date
DE602006013444D1 true DE602006013444D1 (de) 2010-05-20

Family

ID=37909819

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602006013444T Expired - Fee Related DE602006013444D1 (de) 2006-07-11 2006-07-11 Verfahren und System zur Steuerung von Datensynchronisation in FIFO-Speichern und zugehöriger Synchronisierer

Country Status (3)

Country Link
US (1) US20080013386A1 (de)
EP (1) EP1879101B1 (de)
DE (1) DE602006013444D1 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7899965B2 (en) * 2009-01-14 2011-03-01 International Business Machines Corporation Managing message signaled interrupts
CN107220023B (zh) * 2017-06-29 2022-03-22 无锡中微亿芯有限公司 一种嵌入式可配置fifo存储器
IT201800003008A1 (it) 2018-02-23 2019-08-23 St Microelectronics Srl Un circuito di conversione da binario a gray, relativi memoria fifo, circuito integrato e procedimento

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5084841A (en) * 1989-08-14 1992-01-28 Texas Instruments Incorporated Programmable status flag generator FIFO using gray code
US5345419A (en) * 1993-02-10 1994-09-06 At&T Bell Laboratories Fifo with word line match circuits for flag generation
US5491659A (en) * 1995-01-13 1996-02-13 Hughes Aircraft Corp. Hazard-free circuitry for determining full and empty conditions in first-in-first-out memory
US6263410B1 (en) * 1998-09-15 2001-07-17 Industrial Technology Research Institute Apparatus and method for asynchronous dual port FIFO
US6857043B1 (en) * 2000-04-28 2005-02-15 Altera Corporation Shift register implementations of first-in/first-out memories utilizing a double increment gray code counter
US6327207B1 (en) * 2001-04-09 2001-12-04 Lsi Logic Corporation Synchronizing data operations across a synchronization boundary between different clock domains using two-hot encoding
EP1396786A1 (de) * 2002-09-03 2004-03-10 STMicroelectronics Limited Brückenschaltung zur Neutaktung in einer integrierten Halbleiterschaltung
US7668983B2 (en) * 2003-10-24 2010-02-23 Broadcom Corporation System for designing data structures
US7254677B1 (en) * 2004-05-04 2007-08-07 Xilinx, Inc. First-in, first-out memory system with reduced cycle latency

Also Published As

Publication number Publication date
EP1879101B1 (de) 2010-04-07
EP1879101A1 (de) 2008-01-16
US20080013386A1 (en) 2008-01-17

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee