DE602005005726D1 - Verbreitung eines Thread-IDs in einem Multithreadpipelineprozessor - Google Patents
Verbreitung eines Thread-IDs in einem MultithreadpipelineprozessorInfo
- Publication number
- DE602005005726D1 DE602005005726D1 DE602005005726T DE602005005726T DE602005005726D1 DE 602005005726 D1 DE602005005726 D1 DE 602005005726D1 DE 602005005726 T DE602005005726 T DE 602005005726T DE 602005005726 T DE602005005726 T DE 602005005726T DE 602005005726 D1 DE602005005726 D1 DE 602005005726D1
- Authority
- DE
- Germany
- Prior art keywords
- spread
- thread
- pipeline processor
- multithreaded pipeline
- multithreaded
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3802—Instruction prefetching
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3802—Instruction prefetching
- G06F9/3808—Instruction prefetching for instruction reuse, e.g. trace cache, branch target cache
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Multimedia (AREA)
- Debugging And Monitoring (AREA)
- Advance Control (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US774226 | 2004-02-06 | ||
US10/774,226 US7263599B2 (en) | 2004-02-06 | 2004-02-06 | Thread ID in a multithreaded processor |
Publications (2)
Publication Number | Publication Date |
---|---|
DE602005005726D1 true DE602005005726D1 (de) | 2008-05-15 |
DE602005005726T2 DE602005005726T2 (de) | 2009-04-30 |
Family
ID=34679405
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE602005005726T Active DE602005005726T2 (de) | 2004-02-06 | 2005-02-03 | Verbreitung eines Thread-IDs in einem Multithreadpipelineprozessor |
Country Status (3)
Country | Link |
---|---|
US (1) | US7263599B2 (de) |
EP (1) | EP1562109B1 (de) |
DE (1) | DE602005005726T2 (de) |
Families Citing this family (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7890735B2 (en) * | 2004-08-30 | 2011-02-15 | Texas Instruments Incorporated | Multi-threading processors, integrated circuit devices, systems, and processes of operation and manufacture |
US20060095732A1 (en) * | 2004-08-30 | 2006-05-04 | Tran Thang M | Processes, circuits, devices, and systems for scoreboard and other processor improvements |
US7877734B2 (en) * | 2006-01-12 | 2011-01-25 | International Business Machines Corporation | Selective profiling of program code executing in a runtime environment |
US7721071B2 (en) * | 2006-02-28 | 2010-05-18 | Mips Technologies, Inc. | System and method for propagating operand availability prediction bits with instructions through a pipeline in an out-of-order processor |
US8032737B2 (en) * | 2006-08-14 | 2011-10-04 | Marvell World Trade Ltd. | Methods and apparatus for handling switching among threads within a multithread processor |
US9946547B2 (en) | 2006-09-29 | 2018-04-17 | Arm Finance Overseas Limited | Load/store unit for a processor, and applications thereof |
US20080082793A1 (en) * | 2006-09-29 | 2008-04-03 | Mips Technologies, Inc. | Detection and prevention of write-after-write hazards, and applications thereof |
US7594079B2 (en) | 2006-09-29 | 2009-09-22 | Mips Technologies, Inc. | Data cache virtual hint way prediction, and applications thereof |
US8443341B2 (en) * | 2006-11-09 | 2013-05-14 | Rogue Wave Software, Inc. | System for and method of capturing application characteristics data from a computer system and modeling target system |
US8533530B2 (en) * | 2006-11-15 | 2013-09-10 | Qualcomm Incorporated | Method and system for trusted/untrusted digital signal processor debugging operations |
US8341604B2 (en) * | 2006-11-15 | 2012-12-25 | Qualcomm Incorporated | Embedded trace macrocell for enhanced digital signal processor debugging operations |
US8370806B2 (en) * | 2006-11-15 | 2013-02-05 | Qualcomm Incorporated | Non-intrusive, thread-selective, debugging method and system for a multi-thread digital signal processor |
US8380966B2 (en) * | 2006-11-15 | 2013-02-19 | Qualcomm Incorporated | Method and system for instruction stuffing operations during non-intrusive digital signal processor debugging |
US8484516B2 (en) * | 2007-04-11 | 2013-07-09 | Qualcomm Incorporated | Inter-thread trace alignment method and system for a multi-threaded processor |
US9710280B2 (en) * | 2011-12-30 | 2017-07-18 | Intel Corporation | Overlapping atomic regions in a processor |
US9329870B2 (en) | 2013-02-13 | 2016-05-03 | International Business Machines Corporation | Extensible execution unit interface architecture with multiple decode logic and multiple execution units |
GB2526018B (en) | 2013-10-31 | 2018-11-14 | Silicon Tailor Ltd | Multistage switch |
CN105094747B (zh) * | 2014-05-07 | 2018-12-04 | 阿里巴巴集团控股有限公司 | 基于smt的中央处理单元以及用于检测指令的数据相关性的装置 |
CN108958798B (zh) * | 2018-06-15 | 2021-04-20 | 上海兆芯集成电路有限公司 | 指令翻译电路、处理器电路及其执行方法 |
US11288072B2 (en) * | 2019-09-11 | 2022-03-29 | Ceremorphic, Inc. | Multi-threaded processor with thread granularity |
US11782719B2 (en) | 2021-03-27 | 2023-10-10 | Ceremorphic, Inc. | Reconfigurable multi-thread processor for simultaneous operations on split instructions and operands |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6088788A (en) * | 1996-12-27 | 2000-07-11 | International Business Machines Corporation | Background completion of instruction and associated fetch request in a multithread processor |
US6073159A (en) * | 1996-12-31 | 2000-06-06 | Compaq Computer Corporation | Thread properties attribute vector based thread selection in multithreading processor |
US5890008A (en) * | 1997-06-25 | 1999-03-30 | Sun Microsystems, Inc. | Method for dynamically reconfiguring a processor |
US6463522B1 (en) * | 1997-12-16 | 2002-10-08 | Intel Corporation | Memory system for ordering load and store instructions in a processor that performs multithread execution |
US6507862B1 (en) * | 1999-05-11 | 2003-01-14 | Sun Microsystems, Inc. | Switching method in a multi-threaded processor |
US6609193B1 (en) * | 1999-12-30 | 2003-08-19 | Intel Corporation | Method and apparatus for multi-thread pipelined instruction decoder |
US6665755B2 (en) * | 2000-12-22 | 2003-12-16 | Nortel Networks Limited | External memory engine selectable pipeline architecture |
US6651158B2 (en) * | 2001-06-22 | 2003-11-18 | Intel Corporation | Determination of approaching instruction starvation of threads based on a plurality of conditions |
-
2004
- 2004-02-06 US US10/774,226 patent/US7263599B2/en active Active
-
2005
- 2005-02-03 DE DE602005005726T patent/DE602005005726T2/de active Active
- 2005-02-03 EP EP05002225A patent/EP1562109B1/de not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US7263599B2 (en) | 2007-08-28 |
EP1562109B1 (de) | 2008-04-02 |
DE602005005726T2 (de) | 2009-04-30 |
EP1562109A1 (de) | 2005-08-10 |
US20050177703A1 (en) | 2005-08-11 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |