DE602004031852D1 - Verfahren und vorrichtungen zur bereitstellung früher antworten aus einem abgesetzten daten-cache - Google Patents

Verfahren und vorrichtungen zur bereitstellung früher antworten aus einem abgesetzten daten-cache

Info

Publication number
DE602004031852D1
DE602004031852D1 DE602004031852T DE602004031852T DE602004031852D1 DE 602004031852 D1 DE602004031852 D1 DE 602004031852D1 DE 602004031852 T DE602004031852 T DE 602004031852T DE 602004031852 T DE602004031852 T DE 602004031852T DE 602004031852 D1 DE602004031852 D1 DE 602004031852D1
Authority
DE
Germany
Prior art keywords
remote
data cache
devices
request
previous answers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE602004031852T
Other languages
English (en)
Inventor
David B Glasco
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Newisys Inc
Original Assignee
Newisys Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Newisys Inc filed Critical Newisys Inc
Publication of DE602004031852D1 publication Critical patent/DE602004031852D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0813—Multiuser, multiprocessor or multiprocessing cache systems with a network or matrix configuration
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G06F12/082—Associative directories

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Information Transfer Between Computers (AREA)
  • Computer And Data Communications (AREA)
  • Multi Processors (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
DE602004031852T 2003-08-05 2004-07-29 Verfahren und vorrichtungen zur bereitstellung früher antworten aus einem abgesetzten daten-cache Expired - Lifetime DE602004031852D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/635,703 US7249224B2 (en) 2003-08-05 2003-08-05 Methods and apparatus for providing early responses from a remote data cache
PCT/US2004/024685 WO2005017755A1 (en) 2003-08-05 2004-07-29 Methods and apparatus for providing early responses from a remote data cache

Publications (1)

Publication Number Publication Date
DE602004031852D1 true DE602004031852D1 (de) 2011-04-28

Family

ID=34116290

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602004031852T Expired - Lifetime DE602004031852D1 (de) 2003-08-05 2004-07-29 Verfahren und vorrichtungen zur bereitstellung früher antworten aus einem abgesetzten daten-cache

Country Status (8)

Country Link
US (1) US7249224B2 (de)
EP (1) EP1652091B1 (de)
JP (1) JP2007501466A (de)
CN (1) CN1860452A (de)
AT (1) ATE502335T1 (de)
CA (1) CA2533203A1 (de)
DE (1) DE602004031852D1 (de)
WO (1) WO2005017755A1 (de)

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US20070079074A1 (en) * 2005-09-30 2007-04-05 Collier Josh D Tracking cache coherency in an extended multiple processor environment
US7404045B2 (en) * 2005-12-30 2008-07-22 International Business Machines Corporation Directory-based data transfer protocol for multiprocessor system
US7680987B1 (en) * 2006-03-29 2010-03-16 Emc Corporation Sub-page-granular cache coherency using shared virtual memory mechanism
JP5338375B2 (ja) * 2009-02-26 2013-11-13 富士通株式会社 演算処理装置、情報処理装置および演算処理装置の制御方法
US8447934B2 (en) * 2010-06-30 2013-05-21 Advanced Micro Devices, Inc. Reducing cache probe traffic resulting from false data sharing
US8656115B2 (en) * 2010-08-20 2014-02-18 Intel Corporation Extending a cache coherency snoop broadcast protocol with directory information
KR101975288B1 (ko) * 2012-06-15 2019-05-07 삼성전자 주식회사 멀티 클러스터 프로세싱 시스템 및 그 구동 방법
CN109562137A (zh) 2015-09-01 2019-04-02 第波生物公司 用于治疗与异常炎性反应有关的病况的方法和组合物
US9792210B2 (en) * 2015-12-22 2017-10-17 Advanced Micro Devices, Inc. Region probe filter for distributed memory system
US10936496B2 (en) * 2019-06-07 2021-03-02 Micron Technology, Inc. Managing collisions in a non-volatile memory system with a coherency checker
US10980756B1 (en) 2020-03-16 2021-04-20 First Wave Bio, Inc. Methods of treatment

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US5778437A (en) * 1995-09-25 1998-07-07 International Business Machines Corporation Invalidation bus optimization for multiprocessors using directory-based cache coherence protocols in which an address of a line to be modified is placed on the invalidation bus simultaneously with sending a modify request to the directory
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US5887138A (en) * 1996-07-01 1999-03-23 Sun Microsystems, Inc. Multiprocessing computer system employing local and global address spaces and COMA and NUMA access modes
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Also Published As

Publication number Publication date
WO2005017755A1 (en) 2005-02-24
CN1860452A (zh) 2006-11-08
EP1652091B1 (de) 2011-03-16
US7249224B2 (en) 2007-07-24
EP1652091A1 (de) 2006-05-03
ATE502335T1 (de) 2011-04-15
JP2007501466A (ja) 2007-01-25
US20050033924A1 (en) 2005-02-10
EP1652091A4 (de) 2008-10-29
CA2533203A1 (en) 2005-02-24

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