DE602004007503D1 - RECONFIGURABLE ARCHITECTURE FOR SOCs - Google Patents

RECONFIGURABLE ARCHITECTURE FOR SOCs

Info

Publication number
DE602004007503D1
DE602004007503D1 DE602004007503T DE602004007503T DE602004007503D1 DE 602004007503 D1 DE602004007503 D1 DE 602004007503D1 DE 602004007503 T DE602004007503 T DE 602004007503T DE 602004007503 T DE602004007503 T DE 602004007503T DE 602004007503 D1 DE602004007503 D1 DE 602004007503D1
Authority
DE
Germany
Prior art keywords
socs
reconfigurable architecture
reconfigurable
architecture
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE602004007503T
Other languages
German (de)
Other versions
DE602004007503T2 (en
Inventor
Miron Abramovici
Alfred E Dunlop
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
DAFCA Inc
Original Assignee
DAFCA Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by DAFCA Inc filed Critical DAFCA Inc
Publication of DE602004007503D1 publication Critical patent/DE602004007503D1/en
Application granted granted Critical
Publication of DE602004007503T2 publication Critical patent/DE602004007503T2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318555—Control logic
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318541—Scan latches or cell details
DE602004007503T 2003-04-28 2004-04-28 RECONFIGURABLE ARCHITECTURE FOR SOCs Expired - Lifetime DE602004007503T2 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US425101 1995-04-20
US10/425,101 US7058918B2 (en) 2003-04-28 2003-04-28 Reconfigurable fabric for SoCs using functional I/O leads
PCT/US2004/013155 WO2004102210A1 (en) 2003-04-28 2004-04-28 RECONFIGURABLE FABRIC FOR SoCs

Publications (2)

Publication Number Publication Date
DE602004007503D1 true DE602004007503D1 (en) 2007-08-23
DE602004007503T2 DE602004007503T2 (en) 2008-04-17

Family

ID=33299473

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602004007503T Expired - Lifetime DE602004007503T2 (en) 2003-04-28 2004-04-28 RECONFIGURABLE ARCHITECTURE FOR SOCs

Country Status (6)

Country Link
US (2) US7058918B2 (en)
EP (1) EP1620739B1 (en)
JP (1) JP4406648B2 (en)
KR (1) KR20060003063A (en)
DE (1) DE602004007503T2 (en)
WO (1) WO2004102210A1 (en)

Families Citing this family (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7127697B1 (en) * 2001-08-07 2006-10-24 Xilinx, Inc. Methods of utilizing programmable logic devices having localized defects in application-specific products
US6842039B1 (en) * 2002-10-21 2005-01-11 Altera Corporation Configuration shift register
KR101034494B1 (en) * 2004-02-11 2011-05-17 삼성전자주식회사 Bus system based on open core protocol
EP1716424B1 (en) * 2004-02-17 2009-07-15 Institut National Polytechnique De Grenoble Integrated circuit chip with communication means enabling remote control of testing means of ip cores of the integrated circuit
US7607057B2 (en) * 2004-12-28 2009-10-20 Lsi Corporation Test wrapper including integrated scan chain for testing embedded hard macro in an integrated circuit chip
US7358765B2 (en) * 2005-02-23 2008-04-15 Cswitch Corporation Dedicated logic cells employing configurable logic and dedicated logic functions
US7605605B2 (en) * 2005-01-27 2009-10-20 Cswitch Corporation Programmable logic cells with local connections
US7394708B1 (en) 2005-03-18 2008-07-01 Xilinx, Inc. Adjustable global tap voltage to improve memory cell yield
KR100662471B1 (en) 2005-10-11 2007-01-02 엘지전자 주식회사 System-on-chip structure and method for transferring data
US7348796B2 (en) * 2005-10-26 2008-03-25 Dafca, Inc. Method and system for network-on-chip and other integrated circuit architectures
US7296201B2 (en) * 2005-10-29 2007-11-13 Dafca, Inc. Method to locate logic errors and defects in digital circuits
US7484153B2 (en) * 2005-12-06 2009-01-27 Kabushiki Kaisha Toshiba Systems and methods for LBIST testing using isolatable scan chains
US8656191B2 (en) 2005-12-23 2014-02-18 Nagravision S.A. Secure system-on-chip
EP1811415A1 (en) * 2005-12-23 2007-07-25 Nagracard S.A. Secure system-on-chip
EP1802030A1 (en) * 2005-12-23 2007-06-27 Nagracard S.A. Secure system-on-chip
US7519884B2 (en) 2006-06-16 2009-04-14 Texas Instruments Incorporated TAM controller for plural test access mechanisms
US7827515B2 (en) * 2007-03-15 2010-11-02 Oracle America, Inc. Package designs for fully functional and partially functional chips
US20090271877A1 (en) * 2008-04-28 2009-10-29 Dafca, Inc. Method to secure embedded system with programmable logic, hardware and software binding, execution monitoring and counteraction
US8082474B2 (en) * 2008-07-01 2011-12-20 International Business Machines Corporation Bit shadowing in a memory system
US20100005335A1 (en) * 2008-07-01 2010-01-07 International Business Machines Corporation Microprocessor interface with dynamic segment sparing and repair
US7895374B2 (en) * 2008-07-01 2011-02-22 International Business Machines Corporation Dynamic segment sparing and repair in a memory system
US8234540B2 (en) * 2008-07-01 2012-07-31 International Business Machines Corporation Error correcting code protected quasi-static bit communication on a high-speed bus
US8082475B2 (en) * 2008-07-01 2011-12-20 International Business Machines Corporation Enhanced microprocessor interconnect with bit shadowing
US8245105B2 (en) * 2008-07-01 2012-08-14 International Business Machines Corporation Cascade interconnect memory system with enhanced reliability
US8201069B2 (en) * 2008-07-01 2012-06-12 International Business Machines Corporation Cyclical redundancy code for use in a high-speed serial link
US8139430B2 (en) * 2008-07-01 2012-03-20 International Business Machines Corporation Power-on initialization and test for a cascade interconnect memory system
FR2933826B1 (en) * 2008-07-09 2011-11-18 Univ Paris Curie PROGRAMMABLE LOGIC NETWORK, INTERCONNECT SWITCH AND LOGIC UNIT FOR SUCH A NETWORK
US7956639B2 (en) * 2008-07-23 2011-06-07 Ndsu Research Foundation Intelligent cellular electronic structures
WO2010055462A1 (en) * 2008-11-13 2010-05-20 Nxp B.V. Testable integrated circuit and test method therefor
US7979759B2 (en) * 2009-01-08 2011-07-12 International Business Machines Corporation Test and bring-up of an enhanced cascade interconnect memory system
US20100180154A1 (en) * 2009-01-13 2010-07-15 International Business Machines Corporation Built In Self-Test of Memory Stressor
JP5451542B2 (en) * 2010-06-30 2014-03-26 日本電信電話株式会社 Integrated circuit
US9043665B2 (en) * 2011-03-09 2015-05-26 Intel Corporation Functional fabric based test wrapper for circuit testing of IP blocks
US8522189B2 (en) 2011-03-09 2013-08-27 Intel Corporation Functional fabric based test access mechanism for SoCs
US8793095B2 (en) * 2011-03-09 2014-07-29 Intel Corporation Functional fabric-based test controller for functional and structural test and debug
US20150067428A1 (en) * 2012-05-02 2015-03-05 Freescale Semiconductor, Inc. System-on-chip, method of manufacture thereof and method of communicating diagnostic data
US9436623B2 (en) * 2012-09-20 2016-09-06 Intel Corporation Run-time fabric reconfiguration
TW201935306A (en) 2018-02-02 2019-09-01 美商多佛微系統公司 Systems and methods for policy linking and/or loading for secure initialization
US11797398B2 (en) 2018-04-30 2023-10-24 Dover Microsystems, Inc. Systems and methods for checking safety properties
TW202022679A (en) 2018-11-06 2020-06-16 美商多佛微系統公司 Systems and methods for stalling host processor
US11841956B2 (en) 2018-12-18 2023-12-12 Dover Microsystems, Inc. Systems and methods for data lifecycle protection

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5212652A (en) * 1989-08-15 1993-05-18 Advanced Micro Devices, Inc. Programmable gate array with improved interconnect structure
JP3552175B2 (en) * 1995-05-17 2004-08-11 株式会社アドバンテスト Fail memory device
US6968514B2 (en) * 1998-09-30 2005-11-22 Cadence Design Systems, Inc. Block based design methodology with programmable components
US6484280B1 (en) 1999-09-30 2002-11-19 Agilent Technologies Inc. Scan path test support
US6594802B1 (en) 2000-03-23 2003-07-15 Intellitech Corporation Method and apparatus for providing optimized access to circuits for debug, programming, and test
US6877122B2 (en) * 2001-12-21 2005-04-05 Texas Instruments Incorporated Link instruction register providing test control signals to core wrappers
EP1296152A1 (en) 2001-09-21 2003-03-26 Siemens Aktiengesellschaft Electronic circuit and method for measuring its characteristics

Also Published As

Publication number Publication date
WO2004102210A1 (en) 2004-11-25
US20040212393A1 (en) 2004-10-28
KR20060003063A (en) 2006-01-09
JP2007501586A (en) 2007-01-25
DE602004007503T2 (en) 2008-04-17
EP1620739B1 (en) 2007-07-11
US7058918B2 (en) 2006-06-06
US7146548B1 (en) 2006-12-05
EP1620739A1 (en) 2006-02-01
JP4406648B2 (en) 2010-02-03

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Legal Events

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