DE602004007494D1 - Asynchrones Mehrfachtaktsystem - Google Patents

Asynchrones Mehrfachtaktsystem

Info

Publication number
DE602004007494D1
DE602004007494D1 DE602004007494T DE602004007494T DE602004007494D1 DE 602004007494 D1 DE602004007494 D1 DE 602004007494D1 DE 602004007494 T DE602004007494 T DE 602004007494T DE 602004007494 T DE602004007494 T DE 602004007494T DE 602004007494 D1 DE602004007494 D1 DE 602004007494D1
Authority
DE
Germany
Prior art keywords
clock system
multiple clock
asynchronous multiple
asynchronous
clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE602004007494T
Other languages
English (en)
Inventor
Matthew Peter Hutson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Ltd Great Britain
Original Assignee
SGS Thomson Microelectronics Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics Ltd filed Critical SGS Thomson Microelectronics Ltd
Publication of DE602004007494D1 publication Critical patent/DE602004007494D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Information Transfer Systems (AREA)
DE602004007494T 2004-05-24 2004-05-24 Asynchrones Mehrfachtaktsystem Expired - Lifetime DE602004007494D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP04253042A EP1601131B1 (de) 2004-05-24 2004-05-24 Asynchrones Mehrfachtaktsystem

Publications (1)

Publication Number Publication Date
DE602004007494D1 true DE602004007494D1 (de) 2007-08-23

Family

ID=34930335

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602004007494T Expired - Lifetime DE602004007494D1 (de) 2004-05-24 2004-05-24 Asynchrones Mehrfachtaktsystem

Country Status (3)

Country Link
US (2) US7545896B2 (de)
EP (1) EP1601131B1 (de)
DE (1) DE602004007494D1 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1601131B1 (de) * 2004-05-24 2007-07-11 STMicroelectronics Limited Asynchrones Mehrfachtaktsystem
US7639764B2 (en) * 2005-08-17 2009-12-29 Atmel Corporation Method and apparatus for synchronizing data between different clock domains in a memory controller
US7812682B2 (en) * 2009-03-05 2010-10-12 Nel Frequency Controls, Inc. Crystal-based oscillator for use in synchronized system
US8072273B2 (en) * 2009-03-05 2011-12-06 Nel Frequency Controls, Inc. System employing synchronized crystal oscillator-based clock, to be used in either discrete or integrated applications
US8255702B1 (en) * 2009-12-03 2012-08-28 Altera Corporation Programmable logic device with improved security
US9607674B1 (en) * 2016-01-06 2017-03-28 Qualcomm Incorporated Pulse latch reset tracking at high differential voltage

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5256912A (en) * 1991-12-19 1993-10-26 Sun Microsystems, Inc. Synchronizer apparatus for system having at least two clock domains
US5448715A (en) * 1992-07-29 1995-09-05 Hewlett-Packard Company Dual clock domain interface between CPU and memory bus
SG47976A1 (en) * 1994-05-10 1998-04-17 Intel Corp Method and apparatus for providing synchronous data transmission between digital devices operating at frequencies having a p/q integer ratio relationship
US6260152B1 (en) * 1998-07-30 2001-07-10 Siemens Information And Communication Networks, Inc. Method and apparatus for synchronizing data transfers in a logic circuit having plural clock domains
US6370600B1 (en) * 1999-05-25 2002-04-09 Advanced Micro Devices, Inc. Staging buffer for translating clock domains when source clock frequency exceeds target clock frequency
US6549593B1 (en) * 1999-07-19 2003-04-15 Thomson Licensing S.A. Interface apparatus for interfacing data to a plurality of different clock domains
ATE376211T1 (de) * 2000-02-09 2007-11-15 Texas Instruments Inc Gerät zur signalsynchronisierung zwischen zwei taktbereichen
DE60006812D1 (de) * 2000-04-17 2004-01-08 Italtel Spa Schaltung zur synchronisation von impulsen, die im jeweils anderen geltungsbereich zweier verschiedener taktsignale erzeugt werden
US7027542B1 (en) * 2001-06-04 2006-04-11 Advanced Micro Devices, Inc. Apparatus and method for providing data transfer between two digital circuits with different clock domains and for solving metastability problems
EP1601131B1 (de) * 2004-05-24 2007-07-11 STMicroelectronics Limited Asynchrones Mehrfachtaktsystem

Also Published As

Publication number Publication date
US20090316845A1 (en) 2009-12-24
US20050280455A1 (en) 2005-12-22
US7545896B2 (en) 2009-06-09
US7929655B2 (en) 2011-04-19
EP1601131A1 (de) 2005-11-30
EP1601131B1 (de) 2007-07-11

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Legal Events

Date Code Title Description
8332 No legal effect for de