DE602004004868D1 - Kaskadierter A/D-Wandler - Google Patents
Kaskadierter A/D-WandlerInfo
- Publication number
- DE602004004868D1 DE602004004868D1 DE602004004868T DE602004004868T DE602004004868D1 DE 602004004868 D1 DE602004004868 D1 DE 602004004868D1 DE 602004004868 T DE602004004868 T DE 602004004868T DE 602004004868 T DE602004004868 T DE 602004004868T DE 602004004868 D1 DE602004004868 D1 DE 602004004868D1
- Authority
- DE
- Germany
- Prior art keywords
- cascaded
- converter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
- H03M1/0675—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy
- H03M1/069—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy by range overlap between successive stages or steps
- H03M1/0695—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy by range overlap between successive stages or steps using less than the maximum number of output states per stage or step, e.g. 1.5 per stage or less than 1.5 bit per stage type
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/44—Sequential comparisons in series-connected stages with change in value of analogue signal
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004016770 | 2004-01-26 | ||
JP2004016770 | 2004-01-26 | ||
JP2004208528A JP4320732B2 (ja) | 2004-01-26 | 2004-07-15 | カスケードa/d変換器 |
JP2004208528 | 2004-07-15 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE602004004868D1 true DE602004004868D1 (de) | 2007-04-05 |
DE602004004868T2 DE602004004868T2 (de) | 2007-10-31 |
Family
ID=34635696
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE602004004868T Active DE602004004868T2 (de) | 2004-01-26 | 2004-11-10 | Kaskadierter A/D-Wandler |
Country Status (4)
Country | Link |
---|---|
US (1) | US6965338B2 (de) |
EP (1) | EP1557952B1 (de) |
JP (1) | JP4320732B2 (de) |
DE (1) | DE602004004868T2 (de) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10690448B2 (en) | 2017-01-20 | 2020-06-23 | Raytheon Company | Method and apparatus for variable time pulse sampling |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5465092A (en) * | 1994-01-19 | 1995-11-07 | National Semiconductor Corporation | Pipelined analog-to-digital converter with curvefit digital correction |
JP3353626B2 (ja) * | 1995-12-26 | 2002-12-03 | 横河電機株式会社 | カスケードa/d変換器 |
FR2750549B1 (fr) * | 1996-06-28 | 1998-09-18 | Thomson Csf | Convertisseur analogique-numerique |
JP3042423B2 (ja) * | 1996-09-30 | 2000-05-15 | 日本電気株式会社 | 直並列型a/d変換器 |
US6020840A (en) * | 1997-12-24 | 2000-02-01 | Ong; Lance | Method and apparatus for representing analog waveforms in digital form based on a multiplier, elapsed time and polarity |
US6222477B1 (en) * | 1998-06-16 | 2001-04-24 | Yokogawa Electric Corporation | Cascade A/D converter |
JP3559534B2 (ja) * | 2001-05-09 | 2004-09-02 | 沖電気工業株式会社 | アナログ・ディジタル変換回路 |
US6606042B2 (en) * | 2001-05-23 | 2003-08-12 | Texas Instruments Incorporated | True background calibration of pipelined analog digital converters |
-
2004
- 2004-07-15 JP JP2004208528A patent/JP4320732B2/ja not_active Expired - Fee Related
- 2004-11-10 EP EP04026689A patent/EP1557952B1/de not_active Expired - Fee Related
- 2004-11-10 DE DE602004004868T patent/DE602004004868T2/de active Active
- 2004-11-19 US US10/991,497 patent/US6965338B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP4320732B2 (ja) | 2009-08-26 |
JP2005244923A (ja) | 2005-09-08 |
US20050162300A1 (en) | 2005-07-28 |
US6965338B2 (en) | 2005-11-15 |
EP1557952B1 (de) | 2007-02-21 |
EP1557952A1 (de) | 2005-07-27 |
DE602004004868T2 (de) | 2007-10-31 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |