DE60107217T2 - MEMORY MODULE WITH HIERARCHICAL FUNCTIONALITY - Google Patents

Description

The following patent applications filed with the same Applicant and in the name of the same inventors on the filing date of the present application disclose related matters, the subject matter of each application being incorporated in its entirety by reference in the present application:
Memory Module with Hierarchical Functionality, Att. 40050 / B600 / JFO; High Precision Measurement Circuit, Att. 37079 / B600 / JFO; Single-Ended Sense Amplifier with Sample-and-Hold Reference, Att. 37362 / B600 / JFO; Limited Switch Driver Circuit, Att. 37361 / B600 / JFO; Fast Decoder with Asynchronous Reset with Row Redundancy; Anwaltsnr. 37115/600 / JFO; Diffusion Replica Delay Circuit, Att. 37360 / B600 / JFO; Sense Amplifier with Offset Cancellation and Batch Share Limited Swing Drivers, Att. 37363 / B600 / JFO; Memory Architecture with Single-Port Cell and Dual-Port (Read and Write) Functionality, Att. 37364B600 / JFO; Memory Redundancy Implementation, Att. 37496B600 / JFO; and A Circuit Technique for High Speed Low Power Data Transfer Bus, Att. 37497 / B600 / JFO.

BACKGROUND OF THE INVENTION

1. Field of the invention

The The present invention relates to memory devices, in particular on semiconductor memory devices, and in particular on scalable, powerful Semiconductor memory devices.

2. Background of the art

storage structures are integral parts of modern VLSI systems, including digital ones Signal processing systems, become. Although it is typically desirable preferably is to include many memory cells in a given range is the storage cell density normally by other design factors, For example, layout efficiency, performance, energy requirements and noise sensitivity, limited.

In Considering the trend towards compact, high performance integrated High bandwidth, portable and mobile computer networks communications equipment can the aforementioned limitations the design of the memory structure severe conditions impose traditional storage systems and sub-part implementations possibly can not handle.

A The type of basic memory element is Static Random Access Memory (SRAM) that can maintain its memory state without being refreshed to become, as long as the cell is supplied with energy. At a SRAM device, the memory state is usually called voltage differential in a bistable functional element, e.g. an inverter loop, saved. An SRAM cell is more complex than its counterpart, a Dynamic RAM (DRAM) cell, and requires more individual components, preferably Transistors. Accordingly, SRAM devices usually consume more energy and give more heat as a DRAM with comparable storage density and efficiency; SRAM device designs lower energy are particularly suitable for VLSI systems, require the high-density SRAM components, provided that these storage components often stringent Overall design constraints of the specific VLSI system. Further, the SRAM subsystems many VLSI systems frequently in Integrated with specific design implementations, with specific ones Adaptations of the SRAM subsystem The scalability of the SRAM subsystem design restrict or even exclude. As a consequence, SRAM memory subsystem designs, even those that are considered "scalable" Design conditions often do not fulfill, when using these memory subsystem designs for use in a VLSI system with the need of larger storage cell population and / or density are increased.

It there is a need for an efficient, scalable, high-performance memory structure with lower Energy that enables a system designer to have an SRAM storage subsystem to generate strict conditions with regard to the device area, Energy, performance, noise sensitivity, etc. fulfilled.

The US-A-5,751,648 relates to a two stage reading technique for large static Random Access Memory (SRAM) devices.

The JP 10 134 573 relates to a main amplifier circuit for a semiconductor memory, which cooperates with a WRITE amplification circuit.

The US-A-5,247,479 relates to a sense amplifier for use in the context with a static random access memory (SRAM) array.

The US-A-6,009,024 relates to a highly integrated semiconductor memory with reduced area.

EP-A-0 745 995 relates to a flash EEPROM memory device for feedthrough various operations in different sectors, eg deleting one sector while at the same time reading another sector.

It Object of the present invention, a dual port functionality of a hierarchical storage structure with single port. These Task is solved by the method of claims 1 and 2. advantageous Embodiments of Invention are in the subclaims Are defined.

The present invention the aforementioned need by providing a memory module with hierarchical functionality. The present invention further provides a hierarchical one Memory structure prepared, composed of such memory modules is. The memory module itself can be tiered and hierarchical, so that a "global" device in one certain stage as a "local" device in relation be classified to a level immediately higher in the hierarchy can. On the other hand, a "local" device in the same certain level as a "global" device in relation classified to a level immediately lower in the hierarchy become.

In At the basic level or first level, a memory module can be one or have a plurality of memory cells coupled to a local sense amplifier are. One or more local sense amplifiers may be coupled to a global sense amplifier and thus form a column-oriented memory structure. A memory state signal from the memory is received by the local sense amplifier, which in turn to the global sense amplifier outputs local memory state signal. The global sense amplifier can receive this local memory state signal and in response then provide a global memory state signal. Several Column structures can be grouped together to form a two-dimensional one for a given stage Storage array to form. In successive higher levels For example, a memory module can have one or more individual memory modules have, which are composed of a lower level. groups single memory modules can selective with local sense amplifiers coupled, which in turn coupled with a global sense amplifier which is a signal corresponding to a memory location either to the next higher level or, if in the highest Level of the hierarchy, to the memory structure I / O buffers, can spend.

Also in the first stage can one or more cells in the memory module with a local one Word line or line decoder coupled. One or more local word line decoders can be coupled to a global wordline, resulting in a row-oriented Memory structure is formed. A global wordline decoder receives global selection signal corresponding to selected memory cells and forwards this signal to local wordline decoders. The local word line decoders receive this signal and set a local selection signal is available that the selected ones Memory cells activated. As with the column structures, several Lines are grouped together to form a two-dimensional Memory array for to form a given level. In successive higher levels For example, a memory module can have one or more individual memory modules have a lower level. Groups of individual memory modules can be selective coupled with local word line decoders, which in turn are coupled to global word line decoders, which are a selection signal according to a storage location either from the next higher level or, if arranged at the top level of the hierarchy, from that from the address entrances received Predecoder / Word Line Drivers.

signals with limited voltage fluctuation can be detected by the memory cells, the local sense amplifiers, the global sense amplifiers, the local word line decoders, the global word line decoders, or combinations thereof. Where memory cells Produce signals with limited voltage fluctuation, speaks the corresponding local sense amplifier too to such a signal. Preferably, signals are more limited everywhere Voltage fluctuation used to minimize energy consumption and the operating speed of the memory module and the resulting to maximize composite memory structure. To this end For example, one aspect of the present invention includes a single ended grounded one (single-ended) sense amplifier with sample and hold reference. At a In another aspect of the present invention, a batch share becomes more fluctuation limited Driver sense amplifier (charge-share limited-swing-driver). In addition to limiting voltage fluctuations it is also desirable synchronous circuits, for example predecoder and clocked word line decoder, asynchronous circuits, such as local word line decoders, to isolate. Therefore, another aspect of the present invention Invention asynchronously resettable Row decoder available.

Since it is desired to control signal voltage duration and decay and thereby limit signals with limited voltage fluctuation, devices are provided which accurately terminate a signal, including a high accuracy delay measurement circuit and a diffusion replication delay circuit delay circuit). The high accuracy delay measurement circuit can provide exceptionally accurate time measurements, such as a half gate delay. The high accuracy delay measurement circuit can be realized with a multi-stage ring oscillator which can be coupled to a plurality of oscillation signal detectors, which can be counters and signal edge detection circuits respectively counting the number of oscillations through the circuit and determining the extent to which a particular oscillation signal enters the oscillator propagates.

The Diffusion replication delay circuit restricts the signal with limited voltage fluctuation by essential Replicate a delay characteristic a given memory structure component, e.g. a bit line a, so that a localized timing signal can be generated, thus providing highly localized decision making becomes what e.g. the independent ones Operation of and access to memory structure lines allows. An embodiment This aspect of the invention comprises a diffusion capacity, which in the general with the total capacity of the associated structure (e.g., bitline), and a transistor, in general the collected characteristics of the transistors that may be used are replicated to access the associated structure. Another embodiment This aspect of the invention may include dummy cells associated with a selected word line decoder and a selected sense amplifier are effectively coupled. Also can be a split dummy bitline be associated with a particular wordline, causing excessive delay of grouped wordline association is avoided. At another Aspect of the present invention, a data transfer bus is provided, a limited, controlled voltage swing on a data bus apply with which the various components of the present Invention can be coupled. additionally the data transfer bus may have a programmable driver, which can apply logic signals to the data bus, including coded ones Signals, logic signals of multiple levels, or both. Besides that is also provided a bidirectional data transfer bus circuit.

Around To provide robust high-yield storage structures, in particular in embedded contexts, Several redundancy devices are provided. In one embodiment The redundancy aspects of the present invention are redundant Group of memory cells and a redundancy controller provided. Of the Redundancy controller replaces a specific memory group by the re dundante group in response to a storage condition, typically an inoperable or "FAILED" storage group. The redundant storage group can be a storage line, a storage column, a previously chosen one Section of a memory module, a selectable section of a memory module Memory module and a combination thereof. This embodiment the redundancy can be during manufacturing, for example by using fuses and decoders. Or it can be dynamic "on-site", for example by use programmable switch, to be implemented. The redundancy can can also be implemented in other ways. In a further embodiment the redundancy according to the present Invention is provided a word line decoder with line redundancy. The wordline decoder can be coupled to two memory lines be. While the typical operation chooses the word line decoder outputs the first memory line and decodes she. In response to another line select signal, e.g. from a Row failure results, chooses the word line decoder, however, the second memory line instead out and decode it. In a further embodiment of the redundancy aspect The present invention can be asynchronously reset Row decoders are modified to provide the above-mentioned row redundancy having. The memory module and the hierarchical memory structure according to the present Invention can in a semiconductor device, an optical device, or a combination thereof, for example, in a communication device housed be.

The present invention also includes a method for obtaining dual port functionality from a single port hierarchical storage structure. One aspect of this embodiment results in a WRITE AFTER READ operation without a separate PRECHARGE cycle coupled between the READ and WRITE cycles, where the entire WRITE AFTER READ operation is performed within a memory access cycle of the hierarchical memory structure. Where first data is to be retrieved from a first storage location and second data stored at a second storage location, the method comprises locally selecting the first storage location from which the first data is to be retrieved; local reading of the first data (ie the READ operation); the global selection of the second memory location; essentially simultaneously with the global selecting, the global reading of the first data at the first memory location; outputting the first data after global reading; inputting the second data substantially immediately after outputting the first data; local selecting the second memory location; and storing the second data (ie the WRITE operation). Where necessary, precharge the required bitlines before the first data is read locally (ie a PRECHARGE operation). Due to the efficiency realized by a hierarchical memory structure according to the invention, including the elimination of a second PRECHARGE operation immediately before the WRITE operation, such a PRECHARGE / READ / WRITE operation can be performed in less than a single memory access cycle of the hierarchical memory structure. In fact, where the context of the entire hierarchical memory structure (eg, long interconnect lines, large total memory structure, etc.) permits, multiple PRECHARGE / READ / WRITE operations can be performed in less than one memory access cycle. In another embodiment of this method, a WRITE-AFER-READ operation may be performed by interposing a PRECHARGE operation between successive WRITE operations. This embodiment of the method according to the invention comprises the global selection of the first memory location at which the first data is to be stored; precharging bitlines coupled to the first memory location (PRECHARGE1 operation); local selecting the first memory location; storing the first data (WRITE1 operation); global selecting the second memory location where the second data is to be stored; substantially simultaneously with globally selecting the second memory location, precharging bitlines coupled to the second memory location (PRECHARGE2 operation); local selecting the second memory location; and storing the second data (WRITE2 operation). Despite the intermediate PRECHARGE2 operation, the efficiencies provided by a hierarchical storage structure according to the invention allow one or more WRITE AFTER WRITE operations to be performed in less than a single memory access cycle of the hierarchical storage structure.

The The present invention will become apparent from the following detailed description the embodiments together with the attached Drawings are better understood.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other features, aspects and advantages of the present invention will be better understood if they detail in relation to the following Description, attached Claims and the accompanying drawings are considered. It shows:

1 a block diagram of an exemplary static random access memory (SRAM) architecture;

2 a general circuit diagram of an exemplary six-transistor CMOS SRAM memory cell;

3 a block diagram of an embodiment of a hierarchical memory module using local bit line scanning, according to the present invention;

4 a block diagram of an embodiment of a hierarchical memory module using an alternative local bitline scanning structure;

5 a block diagram of an exemplary two-dimensional, two-stage hierarchical memory structure, the plurality of local bit line sampling modules of 3 used;

6 10 is a block diagram of an exemplary hierarchical memory structure showing a memory module using both local word line decoding and local bit line sampling structures;

7 a perspective view of a hierarchical storage structure with a three-level hierarchy, according to the present invention;

8th a circuit diagram of an asynchronously resetable decoder according to an aspect of the present invention;

9 a circuit diagram of a limited fluctuation driver circuit according to one aspect of the present invention;

10 a circuit diagram of a single-ended sense amplifier sample and hold reference (SAMPLE) reference circuit according to one aspect of the present invention;

11 a circuit diagram of a charge-share, fluctuation-limited driver-sense amplifier circuit according to one aspect of the present invention;

12 a block diagram showing an embodiment of hierarchical memory module redundancy;

13 a block diagram showing another embodiment of hierarchical memory module redundancy;

14 a block diagram of a memory redundancy device, the another embodiment of hierarchical memory module redundancy shows;

15A a diagram of the signal flow of an exemplary error-free memory module with column-oriented redundancy;

15B 5 is a diagrammatic representation of the shifted signal flow of the exemplary faulty memory module which is shown in FIG 15A is shown;

16 a generalized block diagram of a redundancy selection circuit showing another embodiment of the hierarchical memory module redundancy;

17 a circuit diagram of an embodiment of a global row decoder with row redundancy according to the present invention;

18 12 is a block diagram showing dual port functionality in a single port hierarchical memory structure using hierarchical memory modules according to the present invention.

19 a schematic diagram of an embodiment of a high-precision delay measurement circuit according to the present invention;

20 a simplified block diagram of an aspect of the present invention using an embodiment of a diffusion replication delay circuit;

21 a simplified block diagram of an aspect of the present invention using a further embodiment of a diffusion replication delay circuit;

22A a schematic diagram of another aspect of an embodiment of the present invention using a high-speed low-energy data transfer bus circuit; and

22B a schematic diagram of another aspect of an embodiment of the present invention using a high-speed low-power data transfer bus circuit.

DETAILED DESCRIPTION THE EMBODIMENTS

As the expert knows Most VLSI systems include communication systems and DSP devices include VLSI memory subsystems. Modern applications VLSI memory subsystems almost always require high efficiency High performance implementations, design compromises in layout efficiency, Speed, power consumption, scalability, design tolerances and the like increase. The present invention reduces these trade-offs by use a novel hierarchical architecture. The memory module of The present invention may also include one or more novel ingredients use that further enhances the efficiency and robustness of the memory modules contribute.

in the the following is helpful, but only for purposes of illustration, the various aspects and embodiments of the present invention To describe the invention in the context of an SRAM memory structure, uses the CMOS SRAM memory cells. For the However, it is obvious to a person skilled in the art that the present invention Invention is not limited to CMOS-based methods, and that the present aspects and embodiments are mutatis mutandis also in SRAM different categories of memory products, including, but not limited on, DRAM, ROM, PLA and the like, whether in a VLSI system embedded or as independent Storage device, can be used.

EXEMPLARY SRAM MODULE AND EXAMPLE STORAGE CELL

1 is a functional block diagram of the SRAM memory structure 100 which shows the basic features of most SRAM subsystems. The module 100 has a memory core 102 , a wordline control 104 , a precharge control 112 , Memory address inputs 114 and a bit line control device 116 on. The memory core 102 is a two-dimensional array of K bits of memory cells 103 arranged to have C columns and R rows of bit storage locations, where K = (C × R). The most common configuration of the storage core 102 uses a single word line 106 to cells 103 on paired differential bitlines 118 connect to. In general, the core is 102 arranged as an array of 2 ^P word lines, based on a set of P memory address input lines 114 , ie R = 2 ^P. Therefore, the p-bit address of the row address decoder 110 and the column address decoder 122 decoded. The access to a given memory cell 103 is in such a single-core memory by activating the column 105 and the line 106 according to the cell 103 carried out. The gap 105 is selected by, and switching, all of the bitlines in the particular column corresponding to the cell 103 activated.

The particular row to be accessed is enabled by selectively activating the row address decoder 110 is selected, and usually corresponds to only one given line, or word line, all cells 103 in the particular line. The word driver 108 can select the selected word line 106 so drive that the selected memory cell 103 on a particular pair of bit lines 118 can be written or read according to the memory address inputs 114 supplied bit address.

The bit line control device 116 can pre-charge cells 120 , Column multiplexer 122 , Sense amplifier 124 and input / output buffers 126 exhibit. Since differential read / write schemes are typically used for memory cells, it is desirable that bitlines be put into a defined state before being accessed. Precharge cells 120 can be used to control the state of the bitlines 118 through a PRECHARGE cycle according to a predefined precharge scheme. In a static precharge scheme, the precharge cells 120 be started constantly. Although often easy to implement, static precharging of the active operation of the device can impose a large energy load. Dynamic precharge schemes may use precharge cells clocked to charge the bitlines 120 use and so can the energy budget of the structure 100 to reduce. In addition to establishing a defined state on the bitlines 118 can the bitlines 120 also used to approximate differential voltages on the bitlines 118 before a read operation. sense amplifier 124 allow it to be the size of the memory cell 103 by sampling the differential voltage on the bit line 118 , which indicates its state, and is reduced by converting this differential voltage into a logic-level signal.

In general, a READ operation is performed by activating the row decoder 110 performed selecting a particular line. The charge on a bit line 118 each pair of bitlines in each column discharges through the activated memory cell 103 indicating the state of active cells 103 in this column 105 represents. The column decoder 122 activates only one of the columns and connects the bitlines 118 with the input / output buffer 126 , The sense amplifiers 124 provide the driver capability to provide power to the input / output buffer 126 to disposal. If the sense amplifier 124 is activated, lead the unbalanced bit lines 118 causing the balanced sense amplifier to be triggered on the state of the bit lines, and data 125 be from the buffer 126 output.

A WRITE operation is done by creating the data 125 to the input / output buffers 126 carried out. Before the WRITE operation, the bitlines become 118 of precharge cells 120 preloaded to a predetermined value. The creation of input data 125 to the input / output buffers 126 causes the precharge voltage on one of the bitlines 118 discharges, resulting in a bit line logic HIGH and a bit line logic LOW. The column decoder 122 chooses a specific column 105 that the bit line 118 with the input / output buffers 126 connects, out, causing one of the bitlines 118 unloaded. The row decoder 110 selects a particular line and the information on the bitlines 118 be at the intersection of the column 105 with the line 106 into the cell 103 written. At the beginning of a typical internal timing cycle, the precharge is disabled and not activated again until the entire operation has been performed. The column decoder 122 and the row decoder 110 are then activated, followed by the activation of the sense amplifier 124 , At the end of a READ or WRITE operation, the sense amplifier becomes 124 disabled. This is followed by disabling the decoder 110 . 122 ; at this time are the pre-charge cells 120 re-activated during a subsequent PRECHARGE cycle. In general, activating the sense amplifier will result 124 during the whole READ / WRITE operation very high power consumption of the device because of the sense amplifier 124 only while actually for scanning the state of the memory cell 103 needed time to be active.

2 shows an implementation of the memory cell 103 in 1 in the form of a CMOS cell 200 with six transistors. The transistor cell 200 is a type of transistor that may also be used in embodiments of the present invention. The SRAM cell 200 may be in one of three possible states: (1) in the STABLE state in which the cell 200 has a signal value corresponding to a logical "1" or logical "0"; (2) in the READ operation state; or (3) in the WRITE operation state. In the STABLE state is the memory cell 200 effectively from the memory core (eg the core 102 in 1 ) separated. The bitlines 202 . 204 are precharged to HIGH (logic "1") before any operation (READ or WRITE) can take place The row select transistors 206 . 208 are switched off during pre-charging. The precharge energy is supplied by precharge cells (not shown) connected to the bitlines 202 . 204 , similar to the precharge cells 12 in 1 , are connected. A READ operation is initiated by performing a PRECHARGE cycle, whereby the bitlines 202 . 204 Logically HIGH summoned and the word line 205 using the row select transistors 206 . 208 is activated. One of the bit lines 202 . 204 discharges through the bit cell 200 , and a differential Voltage will be between the bit lines 202 . 204 generated. This voltage is sensed and amplified to logic levels. A WRITE operation in the cell 200 becomes after another PRECHARGE cycle by driving the bitlines 202 . 204 in the required state and activate the word line 205 carried out. CMOS is a desirable technology because the current drawn from such a SRAM cell is typically due to the leakage current of the transistors 201a-d is limited when they are in the STABLE state.

With the growth of memory cell density and the further integration of memory components into more complex systems, it becomes imperative to provide memory architectures that are robust, reliable, fast, and space and power efficient. Single-core architectures similar to those found in 1 are increasingly unable to meet the performance, speed, range, and robustness constraints for a given high performance storage application. Therefore, it is desirable to minimize power consumption, increase device speed, and improve the reliability and robustness of the device, and numerous approaches have been developed for this purpose. The advantages of the present invention may be better understood in the following context with some of these approaches, particularly as they relate to energy reduction and speed improvement as well as redundancy and ruggedness.

ENERGY REDUCTION AND SPEED IMPROVEMENT

With reference to 1 becomes the content of the memory cell 103 of the memory block 100 in the sense amplifier 102 using a differential signal between the bit lines 104 . 106 determined. However, this architecture is not scalable. Also, there is when the memory block 100 is increased, practical limitations of the ability of the sense amplifier 102 , an appropriate signal in time on the bit lines 104 . 106 to recieve. Increasing the length of the bitlines 104 . 106 increases the associated bit-line capacitance and thus the time it takes for a signal to propagate in the bitlines 104 . 106 to develop. The wires 104 . 106 need more energy to overcome the extra capacity. Also, the architectures of the prior art take longer to precharge longer bitlines, thereby reducing the effective device speed. Similarly, writing into longer bit lines requires 104 . 106 as encountered in the prior art, longer precharge, which increases the power requirements of the circuit and further reduces the effective device speed.

In general, a reduced power consumption in memory devices such as the structure 100 in 1 be achieved, for example, that the entire switching capacity is reduced and voltage fluctuations are minimized. The advantages of the energy reduction aspects of certain embodiments of the present invention may be better understood in the context of reducing switching capacitance and limiting voltage fluctuation.

REDUCTION OF SWITCHING CAPACITY

With the increase the density of memory structures is accompanied by observation that single-core memory structures associated with each memory access high switching capacities can have that are not acceptable. Access to a bit position in Such a single core memory requires activating the entire line, or word line, in which the data is stored, as well the switching of all bitlines in the structure. It is therefore desirable to have high performance memory structures to configure the total switching capacity during a given access to reduce.

Two known approaches to reduce the total switching capacity during a memory structure access include dividing a single core memory structure into one Bank memory structure and using shared wordline structures. In the first approach, it is necessary to use only the particular memory bank, which is connected to the memory cell of interest. In the second approach, the switching capacity is achieved by locating the wordline activation in the highest practicable Extent reduced.

Shared or bank memory core

One The approach to reducing switching capacity is to use the memory core split into separate switchable banks of memory cells. typically, is the total switching capacity while a given memory access for bank memory cores vice versa proportional to the number of banks used. By reasonable Choose the number and placement of banking units within a bank given memory core designs, as well as the type of decoding used, can the total switching capacity, and thus the total energy consumed by the memory core, greatly reduced become. A bank design can also lead to higher product output because the memory banks can be arranged that a defective bank becomes inoperative and inaccessible, while the remaining operational banks of the memory core packed into a lower capacity product can be.

Bank designs are however for certain applications are not suitable. Require shared storage cores an additional Decoding circuitry to allow selective access to individual banks which resulted in a delay leads. Also Many bank designs use memory segments that are just downsized Versions of traditional monolithic core memory designs are, where each segment has a dedicated control, precharge, Decoding, sampling and driver circuit having. These circuits consume both in standby mode and in operation mode tends to consume much more energy than their associated storage cells. Such bank structures like simple to be design, but the extra complexity and the extra Energy consumption can reduce the overall performance of the storage components.

by virtue of By their nature, bank designs are not likely to be magnified too be great for them Take in design requirements. It is also possible that Traditional bank designs are not easily adapted to applications can be which require a memory core configuration different from the underlying one Memory bank structure (e.g., a memory structure, which requires relatively few lines of very long bit length words). Preferred embodiments support the present invention not on a division of the basic storage structure from above down using bank memory designs, but ask a hierarchical storage structure prepared by use of a bottom-up approach is synthesized by hierarchical Coupling the basic memory modules with localized decision-making features, which work synergistically to drastically reduce the overall energy requirements reduce and improve the working speed of the structure. As a minimum, such a hierarchical basic module can be located Having bit line scanning.

Shared word line

Frequently becomes the bit width of a memory device is dimensioned to be a certain word length can record. With the increase in word length for a particular design take also the associated word line delays, the switching capacity, the energy consumption, etc. too. For recording very long word lines, it may be desirable be memory-spanning global word lines in local word lines divided, each of smaller groups be nachbarter, word-oriented Memory cells exist. Each local group uses local decoding and driver components for generating the local wordline signals when the global wordline to which it is connected is enabled. For applications with large word length can the extra overhang, which results from the shared word lines, by reduced Word-line delays Energy consumption, etc. are compensated. The extra overhang, that results from existing shared wordline schemes, However, this can be for make many implementations inappropriate. As previously stated a particular preferred embodiment of the present invention, rather than the traditional layout to use wordlines from top to bottom, a local one Word line for that aforementioned basic memory module prepared what the local decision-making features of the module further improved. As before, here are by use a bottom-up approach to hierarchical to basic memory modules pair, with the extra localized decision-making features of local wordlines according to the present Invention additional synergies realizes the total energy consumption and the signal propagation times further reduce.

VOLTAGE Surge REDUCTION TECHNIQUES

energy reduction can also be achieved by reducing the voltage fluctuations, which arise throughout the structure. By limiting of Voltage fluctuations it is possible the amount of energy that is consumed when the voltage is at one Node or a wire during of a particular event or operation reduce, as well as the amount of energy that is required to the various dropped voltages after the particular event or the particular operation, or before the next access the wished To bring state to reduce. Two techniques point to this Purpose to use pulsed word lines as well as sense amplifier voltage swing reduction on.

Pulsed word lines

By activating a wordline just long enough to correctly detect the differential voltage across a selected memory cell, it is possible to reduce the bitline voltage discharge corresponding to a READ operation in the selected cell. In some embodiments, by applying a pulsed signal to the associated wordline during a selected interval, a sense amplifier is activated only during this interval, thereby reducing the duration of the bitline voltage drop. These embodiments typically use a form of pulse generator that generates a fixed duration pulse. When the pulse duration is aligned, that it satisfies worst-timing scenarios, the extra margin results in unnecessary bit-line pull-off during nominal operations. It is therefore desirable to provide a self-timing self-limiting word line device that is responsive to the actual duration of a given READ operation in a selected cell and that limits word line activation substantially to that duration. Furthermore, if a sense amplifier can successfully perform a READ operation in less than one memory system clock cycle, it may also be desirable for the pulse width activation to occur asynchronously with respect to the memory system clock. Certain aspects of the present invention provide a pulsed wordline signal, for example, by utilizing cooperative interaction between global and local wordline decoders.

Sense amplifier voltage fluctuation reduction

at the production of large Storage arrays it is very desirable the size of one keep individual memory cell to a minimum. Consequently, individual can Memory cells generally do not associate a driver current with Supply input / output bit lines. Be sense amplifier typically used to calculate the value of in a given memory cell to determine stored data and to drive the input / output lines provide required power. In the embodiment of sense amplifier there is typically a tradeoff between energy and speed, where faster response times usually lead to higher energy requirements to lead. Faster sense amplifiers can also tend to be physically larger than slow low energy devices. Furthermore, can the analog nature of sense amplifiers cause that they consume a significant proportion of the total energy. Although a way the response of a sense amplifier to is to use a more sensitive sense amplifier, all will compensated for the advantages associated with the associated circuit complexity, the raised anyway sound sensitivity suffers. It is then desirable Limit bit line voltage variations and consumed by the sense amplifier To reduce energy.

at In a typical embodiment, the sense amplifier detects the small differential signals over a memory cell with respect to that stored in the cell Data value are in an unbalanced state, and amplifies that resulting signal to a logic level. Before a READ operation become the bitlines associated with a particular memory column on a selected one Value preloaded. If a specific memory cell is activated, selects Line decoder the particular line in which the memory cell is located and an associated column decoder selects one with the particular one Column associated sense amplifier out. The charge on one of these bit lines is activated by the Unload memory cell in a manner similar to that stored in the memory cell Data value corresponds. This creates an imbalance between the signals on the paired bit lines and leads to a Bit-line voltage fluctuation. When activated, determined the sense amplifier the unbalanced signal, and it changes in response to this normally symmetrical state of the sense amplifier to a state that represents the data value. This status determination and response takes place within a finite period while of which a certain amount of energy is consumed. The longer it is takes to determine the unbalanced signal, the greater the Voltage drop on the precharged bitlines, and more Energy gets during consumed the READ operation. Any energy over that indeed for the Sampling of the memory cell state consumes time consumed is, is actually wasted energy. For traditional SRAM designs, the Sense amplifier, the while a specific READ operation, while almost the entire Read cycle active. However, this approach unnecessarily consumes high amounts of energy, considering that a sense amplifier only long enough to be active, the differential voltage across a selected memory cell correctly specifying the stored memory state.

There are two general approaches to reducing power in sense amplifiers. First, the sense amplifier current can be limited by using sense amplifiers which automatically turn off when the scan operation is completed. A sense amplifier design for this purpose is a self-latching sense amplifier which turns off as soon as the sense amplifier has indicated the sampled data state. Second, sense amplifier currents can be limited by limiting the activation of the sense amplifier to just the required amount of time. This approach can be realized through the use of a dummy column circuit, complete with bit cells, sense amplifiers, and support circuits. By providing the operation of a functional column, the dummy circuit of a sense amplifier timing circuit may provide an approximation of the activation period characteristics of the functional sense amplifier in the memory system. Although the dummy circuit approach can be quite satisfactory, It is assumed that all the functional sense amplifiers have their scanning operation performed at the time the dummy circuit completes its operation. In this regard, the use of a dummy circuit may be similar to activating the sense amplifiers with a fixed duration pulse signal. Aspects of the present invention provide circuits and sense amplifiers that limit voltage fluctuations and improve the sensitivity and robustness of the sense amplifier operation. For example, compact, power-sensing sense amplifiers having increased resistance to noise and to intrinsic and operational offsets are provided. In the context of the present invention, such sense amplifiers can be realized both in the local module stage and throughout the higher stages of a hierarchical memory structure in accordance with the invention.

REDUNDANCY

Store Designer same energy and device area typically with the Speed off. High-performance memory components provide a serious burden for the energy and range budgets of connected systems, in particular, if such components in a VLSI system, such as a digital Signal processing system, are embedded. Therefore, it is highly desirable Provide storage subsystems that deliver fast, yet energy-efficient and are area efficient. Highly integrated high-performance components require complicated fabrication and manufacturing processes. These methods face unavoidable parameter variations that cause physical defects to the units to be manufactured or that Design so vulnerable can do, that the affected units are no longer usable or under the standard.

at For example, redundancy may be a memory structure be important because of a manufacturing defect or an operating error even a single-bit cell failure of the system which depends on the memory to lead can. Similar can process-invariant features needed be to make sure the internal operations of the structure precise Timing and parameter definitions correspond. Without redundancy and method invariant features can the actual Liche manufacturing yield for one certain memory structure to be so low that it is not accepted can be. Memory structures with low yield are in particular then not accept it when embedded in more complex systems are that have multiple fabrication and manufacturing vulnerabilities exhibit. A higher one Manufacturing yield leads at lower unit costs, and robust design leads too reliable Products with lower operating costs. Therefore, it is also highly desirable to components design wherever possible Have redundancy and procedural invariant features.

redundancy devices and techniques set forth certain particular preferred aspects of the present invention Invention, individually or together, the functionality of the hierarchical Improve memory structure. The aforementioned redundancy aspects of the present invention the hierarchical storage structure less prone to failure by mistake while the manufacture or during of operation, and lead advantageously to a memory product that is better at the same time and cost-effective and robust in operation. The redundancy in a hierarchical memory module can be increased by adding a or multiple redundant rows, columns, or both, to the base module structure will be realized. In one aspect of the present invention a decoder available provided that allows line redundancy. In addition, a memory structure, which is composed of hierarchical memory modules or use multiple redundant modules to faulty memory circuits to map. A redundant module can be a one-to-one replacement of a defective module, or it may be one or more Memory cell circuits for one or more primary Memory modules available put.

STORAGE MODULE WITH HIERARCHIC FUNCTIONALITY

The inventive modular, hierarchical storage architecture provides a compact, robust, energy-efficient, high-performance storage system available that advantageously a flexible and highly scalable architecture having. The hierarchical memory structure is made up of basic memory modules composed, which can be coupled cooperatively, and which are arranged in several hierarchical levels to form a composite To give memory product with any column depth or line length. This modular bottom-up approach locates timing considerations, Decision making and energy consumption in the particular one Unit (s) in which the desired data is stored.

Within a defined design hierarchy, the base memory modules can be grouped into a larger block of memory that itself can be connected to similar memory structures to yield even larger blocks of memory. These larger structures may in turn be arranged to create a complex structure at the highest level of the hierarchy. In hierarchical scanning, it is desirable to use two or three provide more levels of bit-sampling, thereby reducing the read and write time of the device, ie, increasing the effective device speed while reducing the overall power requirements of the device. In a hierarchical design, the switching and memory cell power consumption are located during a read / write operation in the immediate vicinity of the memory cells being evaluated or written, ie, those memory cells in selected memory modules, except for a limited number of global word line selectors and sense amplifiers, and support circuits. Most of the modules that do not contain the memory cells that are being evaluated or written to remain generally inactive.

preferred embodiments of the present invention provide a hierarchical memory module to disposal, local bit line sampling, local word line decoding, or both, using what the total energy consumption and the signal propagation intrinsically reduced and the overall speed as well as the design flexibility and the Scalability increased. Aspects of the present invention contemplate devices and methods before, the total energy consumption of the hierarchical storage structure further restrict while she minimize the impact of a multi-level hierarchy. Certain aspects The present invention is directed to functional susceptibilities mitigated by variations in operating parameters can, or related to the manufacturing process. Besides, they are Devices and techniques disclosed the deterioration system performance resulting from temporary inefficiencies, advantageously, including, but not limited to, highly accurate Delay measurement circuit, Diffusion delay replication circuit and associated Dummy devices. In another aspect of the present invention Invention is an asynchronously resettable Decoder provided the bit line voltage discharge, the for example, a READ operation in the selected cell by limiting the wordline activation to the Time, the sense amplifier actually needed to the differential voltage over a selected one To determine memory cell correctly, reduced.

HIERARCHICAL MEMORY MODULES

at Memory designs of the prior art, for example, the aforementioned Bank designs, will be great logical memory blocks divided into smaller, physical modules, each containing the overhang present an entire memory block including predecoders, sense amplifiers, multiplexers and the like exhibit. Taken together, such memory blocks behave like a single memory block. When using the present invention can however memory blocks comparable, or much larger, size by joining hierarchical functional modules to larger physical memory blocks with any number of words and word length to be provided. For example, existing designs require smaller ones memory blocks into a single logical block, usually replication the predecoder, sense amplifier, and other overhang circuits, which would be associated with a single memory block. According to the present However, this replication is unnecessary and undesirable. A embodiment The invention comprises local bit line scanning in which a limited number of memory cells coupled to a single local sense amplifier is, whereby a basic memory module is formed. Similar Memory modules are grouped and arranged to hold the local sense amplifier signal to the global sense amplifier signal output. Thus, the bit lines associated with the memory cells are not directly coupled to a global sense amplifier, causing the Signal propagation delay and the power consumption typically associated with global bitline sampling are reduced. In this approach, the touches local bitline sense amplifiers the state of a selected one Memory cell quickly and economically and reports the condition to the global sense amplifier. In another embodiment of the present invention, the delays and energy consumption global wordline decoding by providing a Memory module reduces that from a limited number of memory cells exists that have local word line decoding. Similar to The approach of local bit line sampling may be a single global word line decoder with the respective local word line decoders be coupled to several modules. If the global decoder with a Address is activated, only the local word line decoder responds, the one with the desired Memory cell is associated, and activates the memory cell. This Aspect is also particularly energy-saving and fast because the loading on the global line is on the associated local word line decoder limited, and the global wordline signal only needs to be present for so long as needed to trigger the appropriate local wordline. In a further embodiment The present invention is a hierarchical memory module. this includes both local bitline scanning and local wordline decoding provided, which realizes the advantages of both approaches. Each of the aforementioned embodiments will be discussed below.

Local bit line sampling

3 shows a memory block 300 By connecting several cooperating individual modules 320a-e is formed, each of the modules 320a-e each a local sense amplifier 308a-e having. Each module consists of a predefined number of memory cells 325a-g connected to one of the respective local sense amplifiers 308a-e are connected. Each local sense amplifier 308a-e is with the global sense amplifier 302 over bit lines 304 . 306 connected. Because every local sense amplifier 308a-e only the local bitlines 310a-e . 312a-e the respective memory modules 320a-e is sampled, which is for precharging the local bit lines 310a-e and 312a-e required time and energy significantly reduced. Only if the local sense amplifier 308a-e a signal on the respective local lines 310a-e and 312a-e it samples a signal to the global sense amplifier 302 from. This architecture provides flexibility and scalability to a memory architecture design because memory size can be increased by adding locally sampled memory modules such as memory 320a-e , can be increased.

Increasing the number of local sense amplifiers 308a-e that with the global bitlines 304 . 306 are not significantly increasing the load on the global bitlines, and also increasing power consumption in the global bitlines 304 . 306 not because signal development and pre-charging only in the local sense amplifier 308a-e take place near in the memory cells 325a-g in the corresponding memory module 320a-e found signal.

In preferred embodiments of the present invention, it is desirable for each module to have a self-determined timing. This means that every memory module 320a-e may have an internal circuit that samples and generates a sufficient amount of time to place the local sample. Such self-timed circuits are known in the art. In single-core designs, or even bank designs, self-timed memory arrays may be unsuitable for high power operation because timing tends to depend on the slowest of the many components in the structure, and because the signal propagation time in such large structures may be significant. The implementation of self-determined timing may be adversely affected in these larger structures by variations in fabrication and manufacturing techniques, which may significantly affect the operating parameters of the memory array and the underlying timing circuitry.

For a hierarchical memory module, self-determined timing is desirable because the timing paths for each module 320a-e only a limited number of memory cells 325a-g over a very limited signal path. In fact, each module is essentially autonomous in determining the time required to perform a given PRECHARGE, READ, or WRITE operation. Mostly, the duration of an operation at the local level is very short in terms of the access time of the forest, so the memory structure 300 coming from the hierarchical memory modules 320a-e is not subject to the normal, with self-determined timing associated difficulties, and is also resistant to variations in the manufacturing and manufacturing processes.

In general, the cores of localized sense amplifiers 308a-e be smaller than a typical global sense amplifier 302 because within a given time period on the local sense amplifier bitlines 310a-e . 312a-e developed a relatively larger signal. This means that more signal is available to the local sense amplifier 308a-e to drive. In an architecture having only one global sense amplifier, a larger delay occurs while a signal is developed across the global bitlines; This delay can be reduced at the cost of increased energy consumption. Advantageously, local bit-sampling implementations can reduce the delay while at the same time reducing power consumption.

In certain aspects of the present invention, discussed in greater detail below, a driver signal with limited variation may be sent from the active local sense amplifier to the global sense amplifier. A full fluctuation signal can also be sent; in this case, a very simple digital buffer can be used. However, if a signal with limited variation is used, a more complicated sense amplifier may be necessary. For a limited energy application, it may be desirable for two or more memory modules to share local sense amplifiers. However, sharing the sense amplifiers can indirectly slow the bit signal development line indirectly because during the first part of a sample period, the capacitances of both the upper and lower shared memory modules are discharged. However, this slowdown can be minimized and relatively low compared to the benefits achieved by using logical sense amplifiers over existing architectures using only global sense amplifiers. In addition, preferred embodiments of the present invention may be disadvantageous Avoid the effects of sharing sense amplifiers by substantially isolating the local sense amplifier from associated local bitlines that are not coupled to the memory cell to be scanned.

4 shows a memory structure 400 that the in 3 shown structure 300 is similar to that of local bit line scanning of modules 420a-d provides. Each memory module 420a-d consists of a predefined number of memory cells 425a-g , The memory cells 425a-g are with respective local sense amplifiers 408a, b over local bitlines 410a-d . 412a-d connected. Unlike the structure 300 in 3 in which each module 320a-e its own local sense amplifier 308a-e has, are the memory modules 420a-d with a single sense amplifier 408a, b paired. Similar to 3 shows 4 a global sense amplifier 402 that with the local read amplifiers 408a . 408b is coupled.

5 further shows that memory structures like the module 300 in 3 can be coupled so that the overall structure is extended in address size (ie, vertical) or in bit length (ie, horizontal), or both. In the 5 Array structure shown can also be modules such as the module 400 in 4 use. 5 also shows that a composite memory structure 500 that uses hierarchical memory modules can be genuinely hierarchical. The memory blocks 502 . 503 can consist of multiple memory modules, such as the memory module 504 , consist; these can be modules as they relate to 3 and 4 have been described. Each memory block 502 . 503 uses a two-step scan, as has already been shown. In the structure 500 use the memory blocks 502 . 503 however, an intermediate stage of bit line sampling by, for example, using intermediate stage sense amplifiers 514 . 516 use. Under the hierarchical memory paradigm, the middle stage sense amplifiers 514 . 516 with the global sense amplifier 520 be coupled. In fact, the hierarchical storage paradigm according to the present invention may have a highly scalable, multi-level hierarchy, allowing the memory designer to design storage structures whose storage cell densities and configurations are tailored to the application. Advantageously, this scalability and configurability can be obtained without the delays accompanying the memory architectures of the prior art and without the substantially increased power and area consumption.

One of the key factors in designing a faster, power-efficient device is that the capacity per unit length of the global bitline can be reduced as compared to the capacity of the local bitlines. Because when using the hierarchy scheme, the capacity of the global bitline is no longer limited by the cell design. For example, metal lines may run on top of the storage device. Also, a multiplexing scheme may be used that increases the pitch of the bitlines, thereby diverge and further reduces bitline capacitance. Overall, the distance between the global bitlines may be larger because the memory cells are not directly connected to the global bitlines. Instead, every cell is the cell, for example 303 in 3 , only with the local sense amplifier, eg the sense amplifier 308a-e , connected.

Local wordline decoding

6 shows a hierarchical structure 600 with hierarchical wordline decoding, in which each hierarchical memory module 605 from a predefined number of memory cells 610 is constructed with a specific local word line decoder 615a-c are coupled. Each local wordline decoder 615a-c is with a respective global wordline decoder 620 coupled. Every global wordline decoder 620a-d is activated when the Predecoder 622 via the predecoder lines 623 Transmit address information that relates to a specific global wordline decoder 620a-d Respectively. In response, the global wordline decoder activates 620a-d the global wordline 630 which, in turn, has a particular local wordline decoder 615a-c activated. The local wordline decoder 615a-c then activates the associated memory module 605 so that the particular memory cell of interest 610 can be evaluated. Each of the memory modules 605 can thus be considered as an independent memory component, as the hierarchical functionality of each of the modules 605 from local sampling via the local sense amplifiers 608a-b , local decoding via the local word line decoder 615a-c , or both, depends. As with other preferred embodiments of the present invention, it is desirable that each module 605 has a self-determined timing. Self-determined timing may be particularly useful when used in conjunction with local wordline decoding because a local timing signal from a respective memory module 605 can be used to terminate global wordline enable, bitline local sense, or both.

Similar in the 5 shown scaling can multiple storage devices 600 coupled to global bitlines or global decode wordlines to form a composite memory component desired size and configuration. In one embodiment of the present invention, in each module 605 Uses 256 rows of memory that allow the memory designer to create a memory block of arbitrary size that has a granularity of 256 lines. For prior art memory devices, a typical realistic limitation on the number of bits sampled per sense amplifier is about 512 bits. Long bit or word lines can be a problem, especially for WRITE operations, because the associated driver can be affected by the amount of power that it can generate and by the speed with which signal lines, such as the global bit lines 604 . 606 in 6 , sufficient charge can be built up, can be restricted.

Even though 6 shows hierarchical word line decoding in the context of hierarchical bit line operations, hierarchical word line decoding can also be implemented without hierarchical bit line scanning. It is preferable to use both hierarchical word line decoding and bit line hierarchical sampling to obtain the synergies of less energy and higher speed for the entire device.

Hierarchical functionality

In typical embodiments, the energy grows approximately linearly with the size of the memory. According to the present invention, as shown in FIG 3 to 6 however, the power requirements increase only slightly as the overall memory structure size grows, primarily because only the memory module and the associated local bitlines and local wordlines are activated during a given operation. Due to the localized functionality, the global bitlines and wordlines are activated for relatively short periods of time at the beginning and at the end of the operation. In any case, energy consumption is generally determined by the bit size of the word and the basic module configuration, ie, the number of rows and the row length of the modules 620a-e , certainly. Therefore, substantial advantages can be realized by judiciously selecting the configuration of a memory module with respect to the overall memory structure configuration. For example, in a memory structure according to the invention a doubling of the size of the memory device to an energy consumption increase of about 20 percent and not, as found in embodiments of the prior art, lead to a doubling. Furthermore, a memory structure according to the invention can realize a four to sixfold reduction in power requirements and operate 30% to 50% faster, and often faster, than traditional architectures.

7 shows that memory structures according to the invention, for example the memory structure 740 are hierarchical in that each stage within the hierarchy includes local bitline scanning, local wordline decoding, or both. The exemplary memory structure 740 is a three-level hierarchical device, wherein the memory module 700 for the basic, or lowest, level (L ₀ ) of the memory hierarchy, the memory device 720 for the intermediate stage (L ₁ ) of the memory hierarchy and the memory structure 740 is representative of the upper level (L ₂ ) of the memory hierarchy. For the sake of simplicity, only one storage column is shown in each stage, such that the storage column 702 for the basic level (L ₀ ), the storage column 722 for the intermediate stage (L ₁ ) and the storage column 742 for the upper stage (L ₂ ) should be representative.

Memory devices of the stage L ₀ , for example, the memory module 700 , consist of several memory cells, generally by the memory cell 701 which may be arranged in row, column or 2-D array (row and column) formats. The memory module 700 Preferably, it uses local bitline scanning, local wordline decoding, or both as described with respect to FIG 3 to 6 has been described. In the present example, the module M00 includes both local bitline scanning and local wordline decoding. Each memory cell M01 in a respective column of memory cells 702 is through local bitlines 704a . 704b with the local sense amplifier 703 coupled. Although local bit line sampling may be performed in a memory column having a single memory cell, it is preferred that two, or more, memory cells 701 with the local sense amplifier 703 are coupled. Unlike some prior art memory devices that forego local bit line sampling by using special memory cells that provide strong signals at full logic levels, the module can 700 conventional memory cells 701 with low energy than individual memory cells, and it is indeed preferable that it uses them. An advantage of local bit line sampling is that the local sense amplifier 703 only a limited voltage fluctuation on the bit lines 704a . 704b needed to change the state of the memory cell 701 accurately scan, which allows rapid detection and rapid reporting of the memory state with much lower power consumption than in prior art designs. The local sense amplifier of stage L ₀ 703 determines the memory state of the memory cell 701 by coupling the memory state signal over the local bitlines 704a . 704b at the local reading amplifier of stage L ₀ 703 , It is preferable that the memory state signal is a signal with a limited voltage fluctuation. The amplifier 703 transmits a sampled signal indicative of the memory state of the memory cell 701 is representative of the sense amplifier of the stage L ₁ 723 over the exits 705a . 705b the local sense amplifier of the stage L ₀ , with the intermediate stage bit lines 724a . 724b are connected. It is preferable that the sampled signal is also a signal with limited voltage fluctuation. The amplifier 723 in turn, transmits a second sampled signal indicative of the memory state of the memory cell 701 representative of the sense amplifier of stage L ₂ 743 over the exits 725a . 725b the local sense amplifier of the stage L ₁ , which is connected to the bit lines 744a . 744b the upper level are connected. It is also preferable that the second sampled signal is a signal with limited voltage fluctuation.

If the stage L _{2 is} the topmost level in the memory hierarchy, as shown in the present example, the sense amplifier can 743 a global sense amplifier that provides a third signal to the memory cell 701 representative of the sense amplifier output lines 746a . 746b to the associated input / output circuit (not shown). Such input / output circuit may be the input / output circuit in 1 be similar to. However, the present invention provides a hierarchical structure that may consist of two, three, four, or more hierarchical levels. The top level signal may be a full swing signal. When looking at the 7 It will be appreciated by those skilled in the art that "bit line local sampling" occurs and is desired at each stage L ₀ , L _1, and L ₂ in the example hierarchy, eg, because only a limited voltage swing may be required to lower the requested memory state from a lower level to report the hierarchy to the next higher level.

Hierarchical memory structures may also use local wordline decoding, as in the memory device 740 is shown. In 7 is the storage device 740 the uppermost stage (L ₂ ) in the hierarchical memory structure, therefore becomes the incoming global wordline signal 746 from the global wordline drivers (not shown), eg, the global row address decoders 110 in 1 , received. In certain preferred embodiments of the present invention, predecoding is used to provide rapid access to desired wordlines, although predecoding is not required and desired at each stage in a particular implementation. The signal M46 is from the Predecoder 747 the upper stage is received, predecoded and sent to the upper-level global word line decoders (L ₂ ), eg the global word line decoder 748 , forwarded. The decoder M48 is by means of the global word line 750 the upper level to the local word line decoder 749 coupled and activates the local word line decoder 749 the upper level selective. The activated local L ₂ decoder M49 in turn activates the local L ₂ word line 751 containing the selected wordline signal 726 to the Predecoder 727 the intermediate stage (L ₁ ) passes. The Predecoder 727 decodes and activates the corresponding global word line decoder of the intermediate stage (L ₁ ), eg the global word line decoder 728 , The decoder 728 is with the local word line decoder 729 the stage L ₁ by means of the global word line 730 coupled to the stage L ₁ and activates this selectively. The activated local L ₁ decoder 729 in turn, passes a selected wordline signal 706 to the Predecoder 707 the basic stage (L ₀ ), which is the corresponding global word line decoder of the stage L ₀ , for example, the global word line decoder 708 , decoded and activated. The activated local L ₀ decoder 709 in turn, activates the local L ₀ word line 711 and selects the memory cell 701 to access. In view of the above discussion of hierarchical wordline decoding, those skilled in the art will recognize that "local wordline decoding" occurs and is desirable at each stage L ₀ , L ₁ and L ₂ in the example hierarchy because of a substantial reduction in access to selected memory cells required time and energy can be realized.

Although the local wordline decoding in the module 700 in the context of a single column of memory cells, namely the memory columns 702 . 722 . 742 2, the present invention contemplates that local wordline decoding be performed over two or more columns in each hierarchy level, each of the rows in the respective columns being two or more local wordline decoders, eg, the local wordline decoders 709 . 729 . 749 used with respective global word line decoders, eg the global word line decoders 708 . 728 . 748 , by means of respective global word lines, eg the global word lines 710 . 730 . 750 , are coupled. However, it is not necessary to use the same number of rows and columns in two stages of the hierarchical structure. In general, the storage device 720 from several memory modules 700 be constructed, these basic modules 700 can be arranged in a row, column or 2-D array (rows and columns) format. Such basic memory modules may be similar to those described with respect to 3 to 6 shown, as well as combinations thereof. Similarly, the storage device 740 from several storage devices 720 be constructed, these intermediate devices 720 can also be arranged in rows, columns or 2-D array (rows and columns) format. This extended, and extensible, hierarchy allows for the formation of multi-dimensional memory modules that differ from prior art prior art hierarchical implementations, which are generally 2-D groupings of bank, page or segment memory devices, or register file storage devices There is a lack of local functionality at every level of the hierarchy.

Fast decoder with asynchronous reset

typically, can perform local decoder reset used to narrow pulse widths in word lines in one to generate a fast memory device. The in the word line decoder input signals are generally applied to a clock or chip select signal synchronized. However, it is desirable that the wordline independent of Clock and also from varying the input signals in the word line decoder reset becomes.

8th is a circuit diagram showing an asynchronously resettable decoder 800 according to this aspect of the present invention. It may be desirable to implement the AND function by, for example, a source coupled logic. The capacity at the input x2_n 802 may generally be large, therefore, the AND function is performed with approximately one inverter delay plus three buffer stages. The buffers undergo skewing, which reduces the charge capacity by about half and lowers the buffer delay.

To the word line WL 804 To reset independently, it is desirable that the inputs 802 . 803 from the exit 804 be isolated, and the node 805 should be loaded on _Vdd , causing the large PMOS driver M8 807 is switched off as soon as the word line WL 804 is set to logically HIGH. Loading the node 805 on _Vdd can be achieved by a feedback reset loop. The inputs 802 . 803 can from the output 804 by setting the NMOS device 808 to be isolated logically LOW. When the output WL 804 becomes high, becomes the monitor node 810 discharged to ground and the device M0 812 is turned off, reducing the inputs 802 . 803 from the output WL 804 be isolated. The feedback loop loads the rest of the nodes in the buffers across the monitor node 810 before, and the PMOSFET M13 815 is turned on, causing the input x2_n 802 with the node 810 is connected. The decoder 800 will not start until x2_n 802 is reset to V _dd , which normally happens when the system clock signal transitions to a logical LOW. As soon as x2_ 802 Logically HIGH, the node loads 810 using the PMOS device M14 818 on _Vdd , and the device M0 812 is turned on. This turns on the PMOS device M13 815 which causes the input x2_n 802 is isolated from the reset loop, which is the node 810 used. The decoder 800 is now ready for the next input cycle.

Driver circuit with limited fluctuation

9 shows a driver circuit 900 with limited variation according to one aspect of the present invention. With large word length memories, a significant amount of power can be consumed in the data buses. Limiting the voltage fluctuation in such buses can lower the overall energy consumption of the system. This may also apply to a system in which a significant amount of energy is consumed in switching high capacity lines. The driver circuit with limited fluctuation 900 For example, it can reduce energy consumption in high-capacity lines. If the IN signal 902 logic high, the NMOS transistor MN1 conducts 904 , and the node 905 is effectively grounded. In addition, the bit line becomes 910 through the PMOSFET MP1 912 discharged. By suitable dimensioning of the device, the voltage fluctuation in the bit line 910 be limited to a desired value when the inverter is powered by the CMOSFETS MP2 914 and MN2 916 is formed, the PMOSFET MP1 912 OFF switches. In general, the size of the circuit 900 in relation to the capacity (C _{bit line} ) 918 that is driven, and to the sizes of MP2 914 and MN2 916 , In another embodiment of this aspect of the present invention, the limited swing driver circuit includes a tri-state output enable and a self-reset feature. Tri-state functionality is desirable when data lines are multiplexed or shared. Although the voltage at the memory cell node 905 can fluctuate to about zero volts, it is highly desirable that the bit line voltage only varies by about 200-300 mV.

Single-ended sense amplifier with Sample and hold reference

In general, single-ended sense amplifiers are useful to conserve metal space, but the existing designs tend not to be robust due to their susceptibility to power and noise floor. In a further aspect of the present invention shows 10 a single-ended sense amplifier 1000 , preferably with a sample and hold reference. The amplifier 1000 may, for example, be useful as a global sense amplifier sampling input data. At the beginning of an operation Da Tain 1004 sampled, preferably just before the measurement begins. Therefore, the supply, ground or other noise affects the reference voltage of the sense amplifier 1000 generally in the same manner in which the noise affects the node to be measured, which is the noise immunity of the sense amplifier 1000 tends to increase. Both inputs 1010 . 1011 of the differential amplifier 1012 are at the voltage level of DataIn 1004 when the activation signal (GWSELH) 1014 logical is LOW (ie at zero potential). At a preselected interval before starting the measurement, but before DataIn 1013 begins to change, the activation signal (GWSELH) 1014 to logically HIGH, causing the input node 1002 of the transistor M162 1008 is isolated. The DataIn voltage, which exists just before the measurement is taken, is sampled and held as a reference, making the circuit of ground or voltage supply references essentially independent. The transistors M190 1025 and M187 1026 can the node 1021 in which the reference voltage is stored, add capacity. The transistor M190 1025 can also be used as a pump capacitor to detect the voltage drop at the reference node 1021 compensate when the activation signal becomes HIGH and the source 1002 from M1623 1008 pulls on lower tension. The feedback 1030 from the output data Data_toLSA 1035 which are transmitted to a local sense amplifier (not shown) is connected to the source / drain of the transistor M187 1026 coupled, causing the reference voltage at the node 1021 is actively adjusted by capacitive coupling, adaptively adjusting the amplifier gain.

Sense amplifier with Offset Cancellation and Charge-Share Varying Drivers

In a further aspect of the present invention is a sense amplifier 1100 provided by the latchtype with dynamic offset cancellation. The sense amplifier 1100 may also be useful as a global sense amplifier and is suitable for use in conjunction with hierarchical bitline scanning. Typically, the sensitivity of differential sense amplifiers may be limited by the offsets caused by inherent process variations for devices ("device matching") and by dynamic offsets that may develop in the input lines during high speed operation Amplifier offsets usually result in a corresponding reduction in the minimum bitline variation required for a reliable operation, and lower bitline variations can result in faster, lower energy memory operations 1100 For example, the offset in the bitlines may be through the three PMOS precharge balance transistors M3 1101 , M4 1102 , M5 1103 To get picked up; this arrangement is known to the person skilled in the art. Despite the precharge balance transistors 1101 - 1103 however, an additional offset may exist at the inputs of the latch. By using the PMOS balance transistor (M14) 1110 For example, an offset which may be present at the input of the latch-type differential sense amplifier can be substantially equalized. The sense amplifier 1100 has a batch sharing driver 1115 with limited variation. The global bitlines 1150 . 1151 be from the sense amplifier 1100 disconnected when the sense amplifier 1100 is not used, ie in a tri-state condition. The sense amplifier 1100 may be in a precharged state if the two input / output nodes are logic HIGH, ie if both PMOS drivers are M38 1130 and M29 1131 are switched off (inputs at logical HIGH). A large capacitor, C ₀ 1135 in the sense amplifier 1100 can be powered by two series-connected NMOS transistors, M37 1140 and M40 1141 , are held at substantially zero volts. The size of the capacitor 1135 may be due to the amount of voltage fluctuation that typically occurs in the global bitlines 1120 . 1121 is required to be determined.

If the sense amplifier 1100 is activated and the bitlines 1150 . 1151 are logic high, the PMOS transistor M29 1131 turned on, and the global bit_n 1150 is discharged with limited fluctuation. When a bit to be sampled is logic low, the PMOS transistor becomes M38 1130 turned on, and the global bit 1151 is discharged with limited fluctuation. This common charge scheme can result in very low power consumption because only the charge that has the limited voltage swing in the global bitlines 1150 . 1151 caused to be discharged to ground. This means that there is essentially no "over-voltage protection" current Furthermore, this aspect of the present invention may be useful in memories in which the global bitlines are multiplexed for input and output.

Module-level memory redundancy implementation

In 12 has a memory structure 1200 consisting of hierarchical functional memory modules 1201 is constructed, preferably in each module 1201 at least one or more redundant memory lines 1202 . 1204 , one or more redundant storage columns 1205 . 1208 , or both. It is preferred that the redundant memory lines 1202 . 1204 and / or columns 1206 . 1208 are paired because it has been observed that bit cell failure tends to occur in pairs. Redundancy at the module level can, as in 12 is shown where redundancy using a preselected number of redundant memory lines 1202 . 1204 or redundant storage columns 1206 . 1208 in the memory module 1201 is a very area-efficient approach, provided that the typical number of bit cell failures per module remains low. By doing that, only a single line 1202 or a single column 1206 or both in the memory module 1201 is implemented, only one additional multiplexer is needed for the particular row or column. While it may be simpler to provide redundant memory cell circuits that may be activated during testing of the product in the manufacturing phase, it may also be desirable to activate selected redundant memory cells when the memory product is in use, eg, during the Maintenance or during operation of the product. Such activation can be accomplished by numerous techniques and support circuits known in the art.

Memory redundancy implementation with redundant module

As in 13 As shown, memory redundancy may also be provided by providing a redundant module 1301 in the memory structure 1300 coming from the primary modules 1304 . 1305 . 1306 . 1307 is implemented. The redundant module 1301 may be a one-to-one replacement of a defective primary module, eg the module 1304 , be. In a further aspect of the invention, the re dundante module 1301 into smaller redundant memory segments 1310a-d be split, with respective segments 13a-d as redundant memory cells, eg for respective sections of primary memory modules 1304 - 1307 that are defective, are present. The number of each segment 1310a-d in the redundant memory module 1301 allocated memory cells may be a fixed number, or may be flexibly allocated to a different number of defective memory circuits in respective primary memory modules 1304 - 1307 Take into account.

Redundant memory device

14 FIG. 12 shows another aspect of the present invention illustrating an implementation of row and column redundancy for a memory structure, such as the memory structure 100 in 1 , or the memory structure 300 in 3 , provides. This aspect of the present invention may be implemented by using fuses that may be programmed, for example during manufacture. Examples of such uses include metal fuses that are blown electrically or by a focused laser, or a dual-gate device that may be permanently programmed. Although the technique can be used to provide row redundancy or column redundancy, or both, the present discussion will refer to column redundancy in which both the inputs and the outputs may need the benefits of redundancy.

14 shows an embodiment of this aspect of the present invention, the four column pairs 1402a-d with a redundant pair 1404 having. It is desirable to implement this aspect of the present invention in the form of pairs of lines, since a substantial number of RAM failures occur in pairs, whether in columns or rows. Nevertheless, this aspect of the present invention also provides single-line redundancy. In general, the number of fuses in the fuse box 1403 used to provide redundancy, logarithmically related to the number of pairs of lines, eg, the column pairs: log ₂ (number of column pairs), where the number of column pairs also includes the redundant pairs. Since fuses tend to be large, their numbers should be minimized; thus, the logarithmic relationship is advantageous. The fuse outputs 1405 be in the decoder circuits 1406a-d fed, eg one fuse output per column pair. A fuse output produces a so-called "shift pointer." The shift pointer indicates the shift signal in the column pair to be made redundant, and subsequent column pairs can then be inactivated 1405 from the fuse box 1410 be decoded to a shift signal 1412a-d in each column pair. If the shift signal 1412a-d for a specific location of the column pair 1402a-d is selected as from the backup signals 1405 is decoded, the shift pointer shows 1412a-d to this place. The shift signals for this column and all subsequent columns to the right of the column shift pointer column also become inactive.

This aspect of the present invention can be additionally described in 15A and 15B by means of the aforementioned concept of the "shift pointers" 15A are three column pairs 1501 . 1502 . 1503 and a redundant column pair 1504 shown. The shift method is conceptually indicated by "line diagrams." The upper lines 1505 - 1508 The line charts are representative of the columns 1501 - 1504 in the memory core, while the bottom line pairs 1509 - 1511 the data input / output pairs are from the input / output buffers. If a shift signal, eg the signal 1405 in 14 , for a specific column pair 1501 - 1503 logical is LOW, it is preferable that the data is in 1509 - 1511 with the ever right column 1501 - 1503 which is located directly above, be connected by multiplexer. 15B shows a faulty column state. If the shift signal is logically HIGH, eg the signal 1405 in 14 , a faulty column is displayed, eg column 1552 , The active columns 1550 . 1551 remain error-free and continue to receive their data through the input / output lines 1554 . 1555 , However, because the column 1552 is erroneous, data may be from the input / output buffer 1556 to the redundant column pair 1553 be multiplexed. In the chart, it appears that data entering the memory core columns is shifted to the left while data leaving the memory core columns is shifted to the right. By adjusting the position of the shift pointer, which is generally determined by the state of the fuses, the unused redundant column pair may be shifted to a non-functional column, eg, the column 1552 , collapses, thus repairing the gap defect, thereby increasing the full functional storage yield.

Selector for redundant memory circuits

16 shows a further aspect of the present invention, wherein the selector 1600 can provide some form of redundancy. The selector 1600 can be a primary decoder circuit 1605 which may be a global wordline decoder connected to a multiplexer 1610 is coupled. The multiplexer 1610 can through a redundancy circuit 1620 can be activated, which may be a backup system, a programmable memory or other circuitry that generates an activation signal 1630 over the multiplexer 1610 to the selector 1600 can provide. The selector 1600 is suitable for implementing module-level redundancy, such as the one related to the module 1200 in 12 which, for a given implementation, may be row redundancy or column redundancy. In normal operation, the input wordline signal becomes 1650 in the decoder circuit 1605 decoded and, if in the local wordline 1670 If there is no error, the word line signal goes to the first local line 1680 forwarded. If an error is detected, the multiplexer selects 1610 the second local line 1660 which is preferably a redundant word line.

More quickly Decoder with line redundancy

17 shows a preferred embodiment of the selector 1600 in 16 in the form of the decoder 1700 with row redundancy, as implemented in a hierarchical storage environment. The decoder 1700 can be used to implement module-level redundancy, such as those related to the module 1200 in 12 described, be particularly suitable. The global decoder 1700 can be similar to the asynchronously resettable decoder 800 of the 8th work. In general, the decoder 1700 be coupled to a first, desired memory line and a second, alternative memory line. Although the second row may be a physical row next to the first memory row and another of the originally desired rows of the memory module, the second row may also be a redundant row implemented in the module. Although the line decoder 1700 during normal operations, decodes the first memory line, it may also select and decode the second memory line in response to a signal to select an alternative line. If the second row is a redundant row, it may be more appropriate to assume that the select signal is a signal for "selecting a redundant row." The aforementioned row select signals are inputs 1701 and 1702 shown.

If therefore the entrance 1701 or 1702 is activated, transmits the decoder 1700 the local wordline signal normally on WL 1706 is issued, so that it is on xL_Next 1705 is output, which is coupled to an adjacent word line. In general, when a wordline decoder located at a particular location in a memory module receives a shift signal, the decoder remaining after that decoder also shifts, so that the last decoder in the row shuffles its respective WL data Redundant word line shifts. Using a two-dimensional model, if a redundant row is at the bottom of a model, that process may be described as an error at a particular location causing all local wordlines to shift at and below the position of the error down. The local word lines above the position of the error can remain unchanged.

Hybrid Singale Port and Dual Port (R / W) functionality

Hierarchical memory module implementations lead to significant time savings, due in part to localized functionality. The signal propagation time at the local module stage tends to be significantly less than the typical access time of a larger memory structure, even though it uses existing page, bank, and segment memory array and register file schemes. In fact, both read and write operations performed at the basic module level can be done within a fraction of the Total memory structure access time take place. Furthermore, because bit line sampling in accordance with the present invention is energy efficient and does not result in any significant drop in precharge voltages, the bit line voltage levels tend to be marginally lowered after operation. As a result, in certain preferred embodiments of the present invention, it is possible to perform two operations directly in succession without an intervening precharge cycle, within a single access cycle of the overall memory structure. Therefore, although a memory device may be configured as a single-port device, a preferred embodiment of the memory module functions similar to a two-port memory device, which can give such an embodiment a significant advantage over prior art memory structures of comparable total memory size.

18 shows a specific embodiment of this aspect of the present invention in the memory structure 1800 in which both local bit line scanning and local word line decoding are used as described above. The memory structure 1800 has the memory module 1805 on top of that with the local wordline decoder 1815 and the local bit sense amplifier 1820 is coupled. In the memory module 1805 There is a predefined number of memory cells, for example the memory cell 1825 passing through the local wordline 1810 with the local word line decoder 1815 and over the local bitlines 1830 with the local bit sense amplifier 1820 is coupled. The typical single-port functionality becomes the local bitlines 1830 preloaded before the READ and WRITE operations. During a typical READ operation, the Predecoder activates 1835 the corresponding global wordline decoder 1840 which in turn is the local wordline decoder 1815 activated. Once the local wordline decoder 1815 determines that the associated memory cell 1826 is to be evaluated, he opens the memory cell 1825 for the evaluation and activates the local bit sense amplifier 1820 , At the end of the local sampling period, the local bit sense amplifier outputs 1820 the sampled data value on the global bit lines 1845 out. After the global sense amplifier 1850 sampled the data value, the data is sent to the input / output buffer 1855 output. If the READ operation is to be followed by a WRITE operation, a typical single port device would perform another precharge operation before the WRITE operation can begin.

In this particular embodiment of the dual-port functionality, the predecoding step of a subsequent WRITE operation may occur substantially immediately after the local bit-line sense amplifier 1820 the evaluation of the memory cell 1825 begin, ie at the beginning of the sample cycle for the global sense amplifier 1850 and before the data for the input / output buffer 1855 Are available. Therefore, during the period, the operation of the global sense amplifier 1850 and the input / output buffer 1855 and while the READ operation is still in progress, the Predecoder 1835 receive and decode the address signals for a subsequent WRITE operation and the global wordline decoder 1840 activate accordingly. The global wordline decoder 1840 in turn activates the local wordline 1815 in anticipation of the upcoming WRITE operation. Once the data from the input / output buffer 1855 can read out the new data associated with the WRITE cycle to the input / output buffer 1855 be admitted and immediately without a previous precharge cycle eg in the memory cell 1825 to be written. In order to provide the memory addresses for these READ and WRITE operations in a manner consistent with this embodiment of the invention, it is preferred that the clock cycle of the predecoder 1810 faster than the access cycle of the overall memory structure 1800 , For example, it may be desirable to adjust the predecode clock cycle to be approximately twice, or possibly more than twice, the nominal access cycle for the structure 1800 is. In this way, a PRECHARGE WRITE READ operation can be performed on the same memory cell in the same memory module in less than one access cycle, thereby providing dual port functionality from a single port device. It is also envisaged that the above embodiment can realize three or more operations in a single access cycle if it allows the unused time during an access cycle.

Is random the improved functionality described above, especially for large memory structures suitable with comparatively small individual modules in which the difference between global and local access times is more pronounced. In addition, in environments where delays due to signal propagation via interconnections and Signal propagation delays by embedded embedded logical components to sufficient idle time for one Lead storage structure, this improved functionality advantageously make use of otherwise "wasted" time.

19 shows a High Precision Delay Measurement (HPDM) 1900 in accordance with one aspect of the present invention, the time measurements are less as a single gate delay with respect to the underlying technique. These may be, for example, measurements of signal delays and periods, pulse widths, clock skews, etc. The HPDM circuit 1900 may also provide pulse, trigger, and timing signals to other circuits, including sense amplifiers, word line decoders, clocks, synchronizers, automata, etc. In fact, the HPDM circuit is 1900 a measuring circuit of wide applicability. The HPDM circuit 1900 For example, it can be implemented in a high performance microprocessor, where accurate measurements of internal time intervals, possibly on the order of a few picoseconds, can be very difficult when using devices outside the microprocessor. The HPDM circuit 1900 can be used to precisely measure skew between signals, and thus can also be used to introduce or eliminate measured skew intervals. The HPDM circuit 1900 can also be used to characterize the signals of individual components, which may be mismatched or mismatched components, and to substantially synchronize such components. Furthermore, the HPDM circuit 1900 advantageously used in register files, transceivers, adaptive circuits and a myriad of other applications where precise interval measurement per se is desired, as well as in the context of adjusting the behavior of components, circuits and systems in response to these measured intervals.

Advantageously, the HPDM circuit 1900 be designed to address operating voltage, design and process variations, design rules, etc., in relation to the underlying technology, including, but not limited to, bipolar, nMOS, CMOS, BiCMOS and GaAs technologies. Therefore, an HPDM circuit 1900 Designed to accurately measure intervals relative to a 1.8 micron technology, it scales in operation to accurately measure intervals with respect to 1.8 micron technology. Although the HPDM circuit 1900 can be adapted to measure fixed time intervals and thus remains independent of process variations, design rules, etc., it is preferred that the HPDM circuit 1900 to address the technology and design rules that are given. In general, the core of an effective HPDM circuit that can measure intervals on the order of picoseconds may require only a few transistors occupying a minimum footprint. This contrasts sharply with its counterpart in the human domain, ie, an expensive, highly accurate, handheld electronic test device or workbench device.

A feature of the HPDM circuit 1900 is the modified ring oscillator 1905 , As is known in the art of ring oscillators, the oscillation period T _{0 of} an N-ring oscillator is approximately equal to 2NT _D , where T _{D is} the large signal delay of the gate / inverter of each stage. The predetermined oscillation period T ₀ can be selected by selecting the number of gates to be used in the ring oscillator. In general, T _{D is} a function of the rise and fall times associated with a gate, which in turn relate to the underlying parameters, including, for example, gate transistor geometries and fabrication techniques. These parameters are manipulable so that T _{D can} be set to provide a given gate delay time. In a preferred embodiment of the present invention, in the context of a specific embodiment of a hierarchical memory structure, it is desirable that the parameters be related to a CMOS device implementation using 0.18 micron (μm) design rules. However, a person skilled in the art recognizes that the HPDM circuit 1900 is not limited thereto and may be applied in other technologies including, but not limited to, bipolar, nMOS, CMOS, BiMOS, GaAs and SiGe technologies, regardless of the design rules and regardless of whether on Si substrate, SOI and its variants , etc. implemented or not.

Although the exemplary HPDM circuit 1900 a ring oscillator 1905 used with seven (7) stages, more or fewer stages can be used, depending on the desired oscillation frequency. In this example, the ring oscillator points 1905 the NAND gate 1910 on, whose output as output 1920 the first stage is called, and six inverter gates 1911 - 1916 whose outputs 1921 - 1926 are each referred to as outputs of the second to seventh stage.

In addition to the ring oscillator 1905 can the HPDM circuit 1900 storage elements 1930-1937 each coupled to a preselected oscillator stage. The selection and arrangement of memory elements 1930 - 1937 allow the measurement of a minimum time quantum T _L , which is exactly half the gate delay, ie T _L ≈ T _D / 2. The maximum time duration, T _M , of the HPDM circuit 1900 can be conveniently measured by selecting one or more devices, or counters, to determine the number of oscillation cycles that have elapsed since the activation of the oscillator 1905 be kept in mind, for example by the ENABLE signal 1940 , If the selected counter is a single 3-bit device, at For example, up to eight (8) complete cycles through the oscillator 1905 are determined, each cycle in T ₀ time is completed. Taking the single 3-bit counter as an example, T _M ≈ 8T ₀ . The remaining storage elements 1932 - 1937 can be used to indicate the time at which the ENABLE signal occurs during a particular oscillation cycle 1940 has been deactivated, which by checking the respective states of given memory elements 1932 - 1937 after deactivating the oscillator 1905 is determined.

It's at the HPDM circuit 1900 prefers that a k-bit positive edge-triggered counter (PET) 1930 and a k-bit negatively edge-triggered counter (NET) 1931 with the output of the first stage 1920 are coupled. Furthermore, it is preferred that a dual edge-triggered counter (DET) 1932 - 1937 with respective outputs 1921 - 1925 of the oscillator 1905 is coupled. In a particular embodiment of the invention are PET 1930 and NET 1931 selected to be three-bit counters (ie, k = 3), and DET 1932 - 1937 are chosen so that they are each one-bit counters (latches). An advantage of using dual-edge detection in the counters 1932 - 1937 it is that the flank of a particular oscillation signal, passing through the ring oscillator 1905 can be registered in all Stu fen, and that the position of the oscillation signal can be determined at a certain time from it. Since a propagating oscillation signal has its polarity during the sequential passes through the ring oscillator 1905 changes, it is preferable to both the NET circuit 1930 as well as the PET circuit 1931 and it is preferred that the negative edge of a particular oscillation signal be the completion of the first loop event, or cycle, by the ring oscillator 1905 is scanned.

The operation of the HPDM circuit 1900 can be summarized as follows: with the EnableL signal set to HIGH 1904 is the ring oscillator 1905 in STATIC mode, so setting the ResetL signal 1906 on LOW the counters 1930 - 1937 resets. Setting the StartH signal 1907 on HIGH sets the RS flip-flop 1908 which in turn is the ring oscillator 1905 by passing an oscillation signal into the ACTIVE mode. Each edge of the oscillation signal can be identified by identifying the switching activity at each stage output 1920 - 1926 be followed. PET 1930 and NET 1931 that the exit 1920 the first level, identify and count the loop events. It is preferred that the maximum delay to be measured by the maximum count of PET 1930 and NET 1931 can be represented so that the counters do not overflow. To the propagation of the oscillation signal by the ring oscillator 1905 to stop, the StopL signal 1909 set to LOW, the RS flip-flop 1908 reset and the ring oscillator 1905 returned to the STATIC operating mode. Also, the data is in the counters 1930 - 1937 by setting the enL signal 1950 on LOW and the enH signal 1951 on HIGH from the output levels 1920 - 1926 isolated. The digital data is then lpos through the ports 1955 , Ineg 1956 and del 1957 read. Knowing the average step delay, the digital data can then be interpreted to accurately measure the interval during which the ring oscillator 1905 in ACTNE mode of operation, in real time. The HPDM circuit 1900 can be configured so that, for example, after a predetermined period of time, a precise clock or trigger signal, eg the TRIG signal 1945 , provides. For example, in the context of a memory system, such a period of time may be the time required to sample the state of a memory cell, to keep a wordline active, etc.

The average step delay through the steps 1910 - 1916 can be determined by the fact that the ring oscillator 1905 for a given average time by setting StartH 1907 and StopL 1909 operated on HIGH, causing the counters 1930 - 1937 be incremented. In a preferred embodiment of the present invention, the overflow is NET 1931 Keep in mind, with each overflow event 2 ^k Loop events by the ring oscillator 1905 displays. It is preferred that this in-eye retention be by a divider circuit, for example the DIVIDE-BY-64 circuit 1953 is carried out. At the end of the given average time, the data from the divider 1953 through the port RO_div64 1954 is read out as a waveform and then analyzed to determine the average oscillator stage delay. However, those skilled in the art will recognize that the central functionality of the HPDM circuit 1900 That is, to provide a precise measurement of a given amount of time would remain unchanged when the DIVIDE-BY-64 circuit 1953 or a similar divider circuit would not be included here.

The HPDM circuit 1900 may be used for many timing applications related to a memory structure or not in the context of a memory structure, for example, to precisely shape pulsed waveforms and duty cycles to skew or deskew for one or more clocked circuits, or to skew such circuits to provide highly accurate test data to the beginning, end, or duration of a sig nals or an event, etc. Furthermore, the HPDM circuit 1900 be applied to innumerable electronic devices other than memory structures where precise timing is desired.

Accurate self-timed circuits are important features of robust low energy storage. Replication bit-line techniques are described in the art as adjusting the timing of control circuits and sense amplifiers over wide variations in process, temperature, and operating voltage to the memory cell characteristics. One of the problems with some prior art schemes is that split dummy bitlines cluster wordlines into groups, and thus only one wordline can be activated during a memory cycle. Prior to subsequent activation of a wordline in the same group, the dummy bitlines must be precharged, resulting in undesirable delays. The diffusion replication delay technique of the present invention substantially equalizes the capacitance of a dummy bitline by using a diffusion capacitor, preferably for each row. Some prior art techniques use replication bit columns that can contribute to undesirable operational delays. 20 shows the diffusion replication timing circuit 2000 that is a transistor 2005 and a diffusion capacitor 2010 having. It is desirable that the transistor 2005 is an NMOSFET transistor, which is preferably substantially identical to an access transistor string when used in the memory cells of the memory structure (not shown). It is also desirable that the capacitance of the diffusion capacitor 2010 is substantially matched to the capacitance of the associated bit line (not shown). This capacitance may be a predetermined ratio of total bitline capacitance, with the ratio of diffusion capacitance to total bitline capacitance remaining substantially constant over process, temperature, and voltage variations. The total bitline capacitance may include both bitline metal and diffusion capacitances. That way, all the lines in a storage device that make up the timing circuit can be 2000 be used with substantially self-determined timing throughout the operation, even if another row in the same memory module has been activated and not yet preloaded. Therefore, write-to-read operations can be multiplexed into a memory module without significant access time or area penalties. It is therefore desirable to use the diffusion replication delay circuit 2000 in a memory structure like the one in 18 described memory structure 1800 to use. The diffusion replication delay circuit 2000 can be used to determine the fall time of a bit line before a sense amplifier is activated, keeping the drop on the bit line. In this way, the bit line drop voltage can be limited to a relatively small size, thereby saving energy and reducing the memory access time. Furthermore, the timing circuit 2000 used to generate many timing signals in a memory structure like the structure 1800 in 18 to generate exactly, including, but not limited to, PRECHARGE, WRITE and SHUT-OFF timing signals.

21 show an embodiment of the diffusion replication delay circuit 2000 in 20 , The word line activation of a memory cell frequency is pulsed to limit the voltage fluctuation in the high capacitance bit lines to minimize power consumption, especially for large word length memory structures. To accurately control the magnitude of a bitline voltage swing, dummy bitlines may be used. It is desirable that these dummy bit lines have a capacitance that is a predetermined fraction of the actual bit line capacitance. In such an apparatus, the capacitance ratio between dummy bit lines and real bit lines may affect the voltage fluctuations in the true bit lines. In prior art devices using dummy bitlines, a global dummy bitline is used for a global reset loop memory block. Such prior art schemes that use global reset tend to produce pulse widths of a duration that is substantially equivalent to the delay of global wordline drivers. Such an expanded pulse width allows bit line voltage variation, which may be greater than that actually required to activate a sense amplifier. This is undesirable in fast memory structures because the additional, and unnecessary, voltage variation results in a slower, more energy-demanding structure. In one aspect of the present invention, dummy bitlines are preferably shared such that the local bitlines generally have a low capacitance and a short discharge time. Word line pulse signals of very short duration (eg, 500 ps or less) are desired to limit bit line voltage variation. It may also be desirable to provide local reset of shared dummy bitlines to provide very short wordline pulses. The replication wordline 2110 can be used to check the delay between the activation of the memory cell 2120 and the connected sense amplifier 2130 to minimize. Such local signaling is against global signal propagation in relatively long high capacity word lines preferred. The word line 2140 activates the dummy cell 2150 together with the associated memory cell 2120 to be accessed. The dummy cell 2150 can be part of the dummy column 2160 be divided into small groups (for example, eight or sixteen groups). The size of each divided dummy group can be changed to adjust the voltage variation in the bit line. If a dummy bitline is completely discharged, the reset signal may be 2170 locally generated what the wordline 2140 essentially pulls against mass.

22A shows a controlled voltage fluctuation data bus circuit (CVS) 2200 that can be useful in the realization of low power, high speed and dense interconnect buses. The CVS 2200 can reduce bus power consumption by providing a limited, controlled voltage swing across the bus 2215 sets. In a significant configuration, the CVS 2000 an inverter 2205 , a pMOS pass transistor T2 2210 and an nMOS discharge transistor, for example transistor T1a 2205a , exhibit.

Both transistors T1a 2205a and T2 2210 can be programmed to increase the speed and extent of voltage fluctuations on the bus 2215 so that control a first preselected operating characteristic for the bus in response to the input signal 2220a provided. Additional discharge transistors T1b 2205b and B1c 2205c can with the pass transistor T2 2210 coupled and individually programmed to each have a second preselected operating characteristic for the bus and a third preselected operating characteristic for the bus in response to the respective input signals 2220b . 2220c provide. The preselected operating characteristic for the bus may be, for example, the discharge rate of the bus voltage through the respective discharge transistors T1a 2205a , T1b 2205b and T1c 2205c be, so the bus 2215 can provide encoded signals or multi-level logic. For example, as in 22A shown is the CVS 2200 provide three distinct logical levels. Additional discharge transistors programmed to provide additional logic levels may also be used. Therefore, the bus can 2215 Replace two or more lines. Along with the reduction in power consumption, the limited bus voltage variation tends to increase the speed of the bus in an advantageous manner.

22B shows a bidirectional data bus transmission circuit 2250 , the networked inverter I1 2260 and I2 2270 used to the bus 1 2252 with the bus 2 2254 connect to. It is desirable to incorporate a clocked charge / discharge circuit into the bidirectional data bus transfer circuit. The clocked charging transistor MPC1 2266 and the clocked discharge transistor MNC1 2268 are with the inverter I1 2260 coupled. Similarly, the inverter I2 2270 with the clocked charging transistor MPC2 2276 and the clocked discharge transistor MNC2 2278 coupled. The transistors MPC1 2266 , MNC1 2268 , MPC2 2276 and MNC2 2278 are preferably by the clock signal 2280 driven.

When the clock signal 2280 LOW, the charging transistors MPC1 turn on 2266 and MPC2 2276 ON and allow the input node 2265 from BUS 1 and the entrance node 2258 to be summoned by BUS 2 to HIGH. In addition, the discharge transistors MNC1 2268 and MNC2 2278 OFF, so there is no significant discharge. By the entrance node 2256 . 2258 go high, respective signals propagate through the inverter I1 2260 and I2 2270 and are inverted by them, producing a LOW signal for the pass transistor MP12 2262 from BUS 1 and the pass transistor MP22 2272 provided by BUS 2, whereby the signal on BUS 1 2252 to the entrance node 2256 is allowed and then through the entrance node 2258 from BUS 2 to BUS 2 2254 and vice versa. When the clock signal 2280 increases to HIGH, both charging transistors MPC1 turn on 2266 and MPC2 2276 OFF, and the discharge transistors MNC 1 2268 and MNC2 2278 turn ON, causing the data on BUS 1 2252 and BUS 2 2254 be licked. After the next LOW phase of the clock signal 2280 plants on BUS 1 2252 or BUS 2 2254 changed signal value between the buses.

Of the Professional can make many changes and make modifications without departing from the scope of the invention. It is therefore natural that the embodiments shown have been presented for illustrative purposes only and in the following claims do not restrict defined invention.

Claims (6)

Method for providing sequential storage of first data at a first storage location ( 1825 ) having a hierarchical structure and second data at a second memory location ( 1825 ) having a hierarchical structure within an access cycle of the memory structure, the structure comprising local and global site selection, the method comprising: a. global selection of the first memory location ( 1825 ) with a hierarchical structure on which the first data is to be stored; b. Precharging the with the memory cells at the first memory location ( 1825 ) hierarchical structure coupled bitlines (PRECHARGE1 operation); c. local selection of the first memory location ( 1825 ) with a hierarchical structure; d. Saving the first data (WRITE1 operation); e. global selection of the second memory location ( 1825 ) with a hierarchical structure to store the second data; f. Preloading the with the second memory location ( 1825 ) hierarchically structured bit lines (PRECHARGE2 operation) substantially simultaneously with the global selection of the second memory location (FIG. 1825 ) with a hierarchical structure; G. local selection of the second memory location ( 1825 ) with a hierarchical structure; and h. Save the second data (WRITE2 operation). Method for substantially concurrently retrieving first data from a first storage location ( 1825 ) and saving second data at a second storage location ( 1825 ), wherein both locations are located within a hierarchical single port memory structure with local and global data readout and local and global site selection, the method comprising: a. local selection of the first memory location ( 1825 ) from which the first data is to be retrieved; b. local read-out of the first data (READ operation); c. global selection of the second memory location ( 1825 ); d. global readout of the first data at the first memory location ( 1825 ) substantially simultaneously with global selection; e. Outputting the first data after the global readout; f. Inputting the second data substantially immediately after outputting the first data; G. local selection of the second memory location ( 1825 ); and h. Save the second data (WRITE operation). The method of claim 2, wherein the first storage location and the second memory location has the same memory location. The method of claim 2 or 3, further comprising precharging the first and second memory locations ( 1825 ) has coupled bitlines prior to local readout of the first data (PRECHARGE operation). Method according to claim 2 or 3, wherein (a) to (h) within one access cycle of the memory structure ( 1805 ) be performed. The method of claim 4, wherein a plurality of PRECHARGE-READ-WRITE operations within an access cycle of the memory structure ( 1805 ) be performed.