DE60031499T2 - Method for transmitting "fiber-channel" and "non-fiber-channel" signals over a common cable - Google Patents

Description

background the invention

The The present invention relates generally to data storage systems and specifically, data storage systems having a plurality of magnetic disk drives in a redundancy arrangement, with the disk drives of first Controlled disk controllers and second disk controllers can. In particular, the invention also relates to systems of the type in the disk drives through a serial, non-directional, "ring" or Fiber Channel protocol communication system coupled with the disk controllers.

As in the art are used in a data storage system type Data stored in a composite of magnetic disk drives. The disk drives and their interfaced interfaces are in sentences arranged, each set of a first disk controller and a second disk controller. Especially each record is also attached to a second or redundant disk controller coupled to allow the set disk drives in case of failure the first disk controller can work. Therefore, at a failure of the first or the second disk controller of the other disk controller can access the set.

today Although most disk storage systems of this type use one SCSI (Small Computer System Interconnection) protocol, for Working with higher Data transfer speeds are but other protocols introduced. A protocol for a higher one Data transfer speed is sometimes as a Fiber Channel protocol (FC protocol). Such an FC protocol uses a serial, unidirectional "ring" communication system. To provide redundancy, i. in case of a failure of the first Disk controller using the set of disk drives to allow, as discussed above, the sentence is using a separate, independent "ring" or Fiber Channel communication protocol coupled to the second or redundant disk controller. It are therefore two Fiber Channel channels for each Set of disk drives and for their disk interfaces provided: a first Fiber Channel and a second Fiber Channel.

As is also known, then, using the Fiber Channel communication protocol, if any element in the channel becomes inoperable, the entire channel inoperable. This means, if the first disk controller becomes inoperative or if any the disk drives in the set coupled to the first channel inoperable (i.e., as if the disk interface fails, the Disk interface is disabled or docked with it Disk drive or if the disk drive is attached to it fails which is removed), the first Fiber Channel is "interrupted" or open and will inoperable. The in the entire section of the coupled to the first disk channel Set of data stored by disk drives are therefore not available, until the disabled replaced the first disk controller or the inoperative disk drive becomes. This applies to both the first channel as well as the second channel. A proposed solution for this Problem occurs through the use of a switch, sometimes is called LRC (Loop Fail Safe Circuit). Such an LRC switch is used to remove an inoperable disk drive used from his channel.

In One proposed arrangement is one for each disk drive Board provided. The board has a pair of LRC, one for the first Channel and one for the second channel. The open channel can thus be "closed" in the case of an inoperable disk drive by the LRC is put into a bypass state. Such proposed method triggers Although the problem of the inoperable disk drive or open channel, but if one of the LRC pair fails, must replacing the complete board that has the LRC pair, whereby the first and the second channel are disturbed and therefore also the Operation of the entire data storage system is disturbed.

One approach suggested for solving this problem requires n LRC switches (where n is the number of disk drives in the set) in the first channel, ie one LRC for each of the n disk drives in the set and another n LRC switches in the second channel for each n disk drives in the second channel. The set of n first channel LRCs is mounted on a board and the set of n second channel lRCs is mounted on another board. A backplane is used to connect the two LRC-equipped boards, the associated selectors or multiplexers, and the disk drives together. To provide the requisite serial or sequential Fiber Channel connections, a meticulous, complex fanout wiring arrangement has been developed for the Backplane proposed. Further, the slots provided for the two LRC boards eliminate two disk drives and the disk interfaces that would otherwise be plugged into these two backplane slots. Another fiber channel arrangement is described in U.S. Patent No. 5,729,763, entitled "Data Storage System", inventor Eli Leshem, filed March 17, 1998, assigned to the same assignee as that of the present invention.

SUMMARY OF THE INVENTION

According to the present Invention, a method according to claim 1 is provided. preferred Embodiments of the present invention are described in the dependent claims 2 to 4 defined.

SHORT DESCRIPTION THE DRAWINGS

These and other preferred features of the invention will become apparent from the following detailed description easier to understand, when read in conjunction with the accompanying drawings, in which:

1 Fig. 10 is a block diagram of a data storage system according to the invention;

2 a block diagram of one in the system of 1 used redundant Fiber Channel network according to the invention;

3 a block diagram of one in the redundant Fiber Channel network of 3 used to one of a plurality of disk drive sections in the system of 1 used composite disk drive coupled port bypass section according to the invention;

4 there is a sketch showing the connection of in the system of 1 used with input / output (I / O) adapters with disk drives and a pair of port bypass cards operating in the redundant Fiber Channel network of 2 be used;

5 Figure 12 is an illustration of a cable for transmitting fiber channel signals and non-fiber channel signals;

5A a cross-sectional diagram of the cable of 5 is, wherein the cross section along line 5A-5A in 5 runs;

5B a schematic sketch is the connections between conductors in the cable of 5 and pins in a connector pair of such a cable;

6 is a schematic sketch of an elevation of a disk backplane into which the disk drives and the port bypass card pair of 4 are plugged;

7 Figure 10 is an isometric view of a rack used to store the disk backplane with the disk drive (s) and port bypass card pair connected thereto 4 is used;

7A an enlarged view of a part of the frame of 7 is, with this part in 7 is enclosed by arrow 7A-7A;

8th a plan view of part of the plate backplane of 6 wherein, at this disk backplane, a disk drive is connected to one of a plurality of connectors of that disk backplane;

9 FIG. 4 is an isometric view of a housing or mounting frame used for an exemplary one of the disk drives for plugging into the connector of the disk backplane of FIG 8th is executed;

10 a view of the housing from 9 from above, wherein a disk drive is shown looking in the mounting frame;

11 a side view of the housing of 9 is;

12 an enlarged view of the rear part of 10 is;

12A a cross-sectional sketch of a part of the mounting frame of 12 is, with this part in 12 from an arrow 12A - 12A is enclosed;

13 an enlarged view of the rear part of 10 is, wherein a disk drive to a cable of the mounting frame of 12 is shown connected;

14 a block diagram of a in the redundant Fiber Channel network of 3 used in a port bypass section according to an alternative embodiment of the invention to one of a plurality of disk drive sections in the system of 1 coupled composite disk drives, said port bypass section having a pair of port bypass cards with fail-safe control systems according to the invention;

15 a to understand the operation of the port bypass cards of 14 is a diagram useful with the failsafe control systems according to the invention;

16 a block diagram of one in the system of 1 used redundant Fiber Channel network, this network has a rear-end I / O adapter with a Fiber Channel hub according to the invention;

17 a representation of an exemplary one of a plurality of front-end directors of the system of 1 which is coupled to host computer sections by a Fiber Channel I / O adapter in accordance with the invention;

18 a test board for testing signal integrity in the system 1 is;

19 a representation is that the relationship between 19A and 19B shows, these being 19 . 19A and 19B together a system interface of the system of 1 demonstrate;

20 in a system backplane of the interface of 19 used slots, each of these slots has a plurality of pins, the test board of 18 for checking the integrity of the signal on each of the pins.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

THE SYSTEM TOTAL

In 1 to which reference is now made is a data storage system 10 pictured, where a host computer 12 through a system interface 16 to a composite 14 is coupled by disk drives. The system interface 16 has a cache memory 18 with an upper memory address section 18H and a lower address storage section 18L , A majority of directors 20 ₀ - 20 ₁₅ is for regulating the data transfer between the host computer 12 and the composite 14 disk drives while such data is through the cache memory 18 run through, provided. A pair of upper address buses TH, BH are electrically connected to the upper address storage section 18H connected. A pair of lower address buses TL, BL are electrically connected to the lower address memory section 18L connected. The cache memory 18 has a plurality of memory location addresses. Here are the memory locations with the higher order addresses in the upper address memory sections 18H and the memory locations with the lower-order addresses are located in the lower address memory sections 18L , It should be noted that each of the directors 20 ₀ - 20 ₁₅ is electrically connected to one of the pair of upper address buses TH, BH and one of the pair of lower address buses TL, BL. That's how each of the directors can 20 ₀ - 20 ₁₅ all locations in the entire cache memory 18 address (ie to the upper address memory sections 18H and to the lower address memory sections 18L ) and therefore can transfer data to and from any location in the entire cache memory 18 store or retrieve.

In particular, a rear-end part is the directors, here's the directors 20 ₀ - 20 ₃ and 20 ₁₂ - 20 ₁₅ , through respective I / O adapter cards 22 ₀ - 22 ₃ respectively. 22 ₁₂ - 22 ₁₅ and respective Fiber Channel (FC) port bypass sections 23 ₁ - 23 ₈ (in conjunction with 2 described in more detail) electrically connected to the composite 14 connected by disk drives. A front-end section of the directors, here's the directors 20 ₄ - 20 ₁₁ , is electrically powered by respective I / O adapter cards 22 ₁ - 22 ₈ as shown with the host 12 connected. It is too be make sure that each end of the buses TH, TL, BH, BL terminate with a pair of master and slave arbiter bus arrays, not shown, as described in co-pending patent specification of serial no. 09 / 224,194, filed December 30, 1998, entitled DATA STORAGE SYSTEM, inventor Mark Zani, of the same assignee as that of the present invention.

In operation, the host computer gives 12 a write request to one of the front-end directors 20 ₄ - 20 ₁₁ to execute a write command when the host computer 12 Wants to save data. One of the front-end directors 20 ₄ - 20 ₁₁ responds to the request and asks the host 12 to the data. After forwarding the request to the requesting one of the front-end directors 20 ₄ - 20 ₁₁ The director determines the size of the data and reserves it in cache memory 18 Space to save the request. The front-end director then generates control signals on an upper address memory bus (TH or BH) or a lower address memory bus (TL, BL) connected to such a front-end director, depending on the location in the cache memory 18 for storing the data and for enabling the transfer to the cache memory 18 was allocated. The host computer 12 then transmits the data to the front-end director. The front-end director then tells the host 12 with that the transfer is complete. The front-end director refers to one in the cache 18 saved table, not shown, to determine which of the rear-end directors 20 ₀ - 20 ₃ and 20 ₁₂ - 20 ₁₅ to process this request. The table forms the address of the host computer 12 to an address in the network 14 from disk drives. The front-end director then places a notification in a "mailbox" (not shown and cached 18 saved) for the rear-end director to handle the request, the amount of data, and the disk address for the data. Other rear-end directors ask for cache memory 18 when they are idle to control their "mailboxes." If the polled "mailbox" indicates that a transfer is to be made, the rear-end director processes the request, addressing the disk drive in the aggregate It reads the data from the cache memory and writes it into the addresses of a disk drive in the composite 14 , When data from the disk drive to the host 12 the system works the other way around.

The Directors 20 ₀ - 20 ₃ and 20 ₁₂ - 20 ₁₅ of the rear-end part are identical in construction and are described in detail in the aforementioned co-pending patent application Ser. No. 09 / 224.194, wherein they include a pair of central processor sections CPU X and CPU Y, a random access memory (RAM) Ports and shared resources (flash-memory, etc.) that pass through the I / O adapter cards 20 ₀ - 20 ₃ and 20 ₁₂ - 20 ₁₅ and the Fiber Channel (FC) Port Bypass sections 23 ₁ - 23 ₈ the composite 14 disk drives ( 1 ), and coupled to an upper memory address bus, here TH, and a lower memory address bus, here BL. It should be noted that each of the directors 20 ₀ - 20 ₃ and 20 ₁₂ - 20 ₁₅ has a first output port A and a second output port B. It should also be noted that different pairs of rear-end directors 20 ₀ . 20 ₁ ; 20 ₂ . 20 ₃ ; 20 ₁₂ . 20 ₁₃ (not shown) and 20 ₁₄ . 20 ₁₅ each in redundant Fiber Channel (FC) networks 25 ₁ - 25 ₄ are arranged as shown. It should also be noted that each of the redundant Fiber Channel (FC) networks 25 ₁ - 25 ₄ also includes pairs of I / O adapter cards 22 ₀ . 22 ₁ . 22 ₂ . 22 ₃ ; 22 ₄ . 22 ₁₂ ; 22 ₁₃ (not shown) and 22 ₁₄ . 22 ₁₅ ; Fiber Channel (FC) port by-pass sections 23 ₁ . 23 ₂ ; 23 ₃ . 23 ₄ ; 23 ₅ (not illustrated), 23 ₆ (not shown) or 23 ₇ . 23 ₈ as shown, and disk drive sets 14 ₁ . 14 ₂ ; 14 ₃ . 14 ₄ ; 14 ₄ (not illustrated), 14 ₆ (not shown) or 14 ₇ . 14 ₈ , as shown. The pairs of redundant Fiber Channel (FC) networks 25 ₁ - 25 ₄ are identical in structure, an example of this, here redundant Fiber Channel (FC) network 25 ₁ , is in 2 shown in detail. How out 1 can be seen, is Director 20 ₀ connected with buses TH and BL and Director 20 ₁ is connected to the buses TL and BH. The redundant FC network 25 ₁ ( 1 ) is thus about the directors 20 ₀ and 20 ₁ also coupled to all four buses TH, BH, TL and BL.

For an example of the redundant FC networks 25 ₁ - 25 ₄ , here the redundant FC network 25 ₁ So, that's how in 2 is shown, note that the first port A and the second port B of Director 20 ₀ through I / O adapter 22 ₀ with FC port bypass section 23 ₁ or FC port bypass section 23z are connected. Likewise, the first Port A and the second Port B are by Director 20 ₁ through I / O adapter 22 ₁ with FC port bypass section 23 ₁ or FC port bypass section 23z connected. Each of the FC port bypass sections 23 ₁ . 23 ₂ has a pair of FC port bypass cards 34 ₁ and 34 ₂ , here an A-port bypass card 34 ₁ and a B-port bypass card 34 ₂ , Each of the disk drive sections 14 ₁ - 14 ₈ ( 1 ) has a plurality, here eight, of disk drives 36 ₁ - 36 ₈ on as for the disk drive sections 14 ₁ and 14 ₂ in 2 It is assumed that the number of disk drives in a section can be selected according to the required memory requirement.

Each of the disk drives 36 ₁ - 36 ₈ has a pair of redundant ports, ie Port A and Port B as shown. Further, the A-port bypass card 34 ₁ from each of the port bypass sections 23 ₁ . 23 ₂ , as shown with the A ports of the disk drives 36 ₁ - 36 ₈ in a corresponding one of the disk drive sections 14 ₁ respectively. 14 ₂ connected. Therefore, the port A bypass card 34 ₁ from port bypass section 23 ₁ with the A port of the disk drives 36 ₁ - 36 ₈ in the disk drive section 14 ₁ connected and the port A bypass card 34 ₁ from port bypass section 23z is with the A port of the disk drives 36 ₁ - 36 ₈ in the disk drive section 14z connected as shown. Likewise is the B-port bypass card 34z from each of the port bypass sections 23 ₁ . 23 ₂ with the B ports of the disk drives 36 ₁ - 36 ₈ in a corresponding one of the disk drive sections 14 ₁ respectively. 14 ₂ connected as shown. The Port B bypass card 34 ₂ from port bypass section 23 ₁ So it is with the B-port of the disk drives 36 ₁ - 36 ₈ in the disk drive section 14 ₁ connected and the Port B bypass card 34z from port bypass section 23z is with the B-port of the disk drives 36 ₁ - 36 ₈ in the disk drive section 14z connected as shown. The FC Port Bypass Cards 34 ₁ . 34 ₂ are identical in structure and an exemplary, here FC port bypass 34 ₁ , is in 3 between the A ports of the disk drives 36 ₁ - 36 ₈ in the sentence 14 ₁ the disk drives and the I / O adapter 22 ₀ / Director 20 ₀ switched shown in detail. It should be noted that in 3 also the Port B bypass card 34 ₂ from port bypass section 23 ₁ between the B ports of the disk drives 36 ₁ - 36 ₈ in the sentence 14 ₁ the disk drives and the I / O adapter 22 ₁ / Director 20 ₁ is shown switched.

Regarding 2 you can see that in the event of a failure in Director 20 ₁ Director 20 ₀ through its port B to the disk drives 36 ₁ - 36 ₈ in the sentence 14 ₂ and the like in the event of a failure in Director 20 ₀ Director 20 ₁ through its A-port on disk drives 36 ₁ - 36 ₈ in the sentence 14 ₁ can access. It should also be noted that if there is a failure or removal of any of the Port A or Port B bypass cards 34 ₁ . 34 ₂ still from one of the directors 20 ₀ and 20 ₁ on both sets of disk drives 14 ₁ and 14 ₂ can be accessed. For example, if the port A bypass 34 ₁ from Fiber Channel port bypass section 23 ₁ fails or is removed by Director 20 ₁ off over the path between Port A of Director 20 ₁ , the Port B Bypass Card 34 ₂ from Fiber Channel bypass section 23 ₁ and port B of the disk drives in set 14 ₁ on the sentence 14 ₁ be accessed from disk drives. Likewise, if the card from port B bypass 34 ₂ from Fiber Channel port bypass section 23 ₁ fails or is removed by Director 20 ₀ off over the path between Port A of Director 20 ₀ , the Port-A-Bypass 34 ₁ from Fiber Channel bypass section 23 ₁ and Port A of the disk drives in set 14 ₁ on the sentence 14 ₁ be accessed from disk drives. If the port A bypass card 34 ₁ from Fiber Channel port bypass section 23 ₂ fails or is removed by Director 20 ₁ off via the path between Port B of Director 20 ₁ , the Port B Bypass Card 34 ₂ from Fiber Channel bypass section 23 ₂ and port B of the disk drives in set 14 ₂ on the sentence 14 ₂ be accessed from disk drives. Similarly, if the port B bypass 34 ₂ from Fiber Channel port bypass section 23 ₂ fails or is removed by Director 20 ₀ off via the path between Port B of Director 20 ₀ , the Port-A-Bypass 34 ₁ from Fiber Channel bypass section 23 ₂ and Port A of the disk drives in set 14 ₂ on the sentence 14 ₂ be accessed from disk drives.

The Port A Bypass Card 34 ₁ and the Port B bypass card 34 ₂ are identical in structure. Port A bypass selector or multiplexer card 34 ₁ has the task of Port A of Director 20 ₀ (via I / O adapter 22 ₀ by a first fiber channel containing one or more of the plurality of fiber channel connections 29 _A1 - 29 _AB serially to a selected one or selected ports A of the plurality of disk drives 36 ₁ - 36 ₈ in sentence 14 ₁ and the Fiber Channel Port Bypass Multiplexer Card 34z The job is to have the A-Port of Director 20 ₁ (via the I / O adapter 22 ₁ ) through Fiber Channel connections 29 _B1 - 29 _B8 serially to a selected or selected one of the plurality of disk drives 36 ₁ - 36 ₈ in sentence 14 ₁ as illustrated, in a manner briefly described below and described in detail in co-pending application Serial No. 09 / 343,344, filed June 30, 1999.

PORT BYPASS CARD

In 3 to which reference is now made, the exemplary FC Port Bypass Card 34 ₁ multiplexer 39 ₁ - 39 ₁₁ and a control section 40 on (it can be assumed that the number of multiplexers is determined according to the required memory requirement). Each of the multiplexers 39 ₁ - 39 ₁₁ has a pair of input ports (ie, an A input and a B input) and an output port, wherein input port A or input port B is selectively selected according to a respective control signal C ₁ -C ₁₁ from the control section as shown 40 is attached to it, is coupled to the output port. The operation of the control section 40 is described in detail in copending application Serial No. 09 / 343,344, filed on Jun. 30, 1999, of the same assignee as the present invention, the entire subject matter of which is incorporated herein by reference. The normal operating mode as well as other operating modes are described comprehensively in the abovementioned patent application 09 / 343,344. For convenience, the normal mode will be described below, assuming that the Port B By matching card 34 ₂ the same structure as the port A bypass card 34 ₁ Has.

NORMAL BUSINESS. BUSINESS AS USUAL

During normal operation, Port A is by Director 20 ₀ through disk drives 36 ₁ - 36 ₄ from sentence 14 ₁ over ports A of these disk drives 36 ₁ - 36 ₄ serially coupled and Port B by Director 20 ₁ is through disk drives 36 ₅ - 36 ₈ from sentence 14 ₁ over ports B of these disk drives 36 ₅ - 36 ₈ coupled serially. This is done by the control signals C ₁ -C ₁₁ from Director 20 ₀ on bus 45 ₀ and equivalent control signals from Director 20 ₁ on bus 45 ₁ on Port B bypass card 34 ₂ which couple one of the A and B ports of the multiplexers coupled to the outputs of such multiplexers, as fully described in the aforementioned patent application Ser. No. 09 / 343,344.

For example, in terms of port A bypass card 34 ₁ , during normal operation, the A inputs are the multiplexers 39 ₁ - 39 ₆ coupled to their outputs, while the B inputs of the multiplexer 39 ₇ - 39 ₁₁ are coupled to their outputs. During normal operation, the data is run by Director 20 ₀ / I / O adapter 22 ₀ on Fiber Channel transmission line 41 ₁ therefore sequentially by multiplexer 39 ₁ to the A port of disk drive 36 ₁ through multiplexer 39 ₂ to the A port of disk drive 36z through multiplexer 39 ₃ to the A port of disk drive 36 ₃ through multiplexer 39 ₄ to the A port of disk drive 36 ₄ and then sequentially through multiplexers 39 ₅ , Multiplexer 39 ₇ , Multiplexer 39 ₈ , Multiplexer 39 ₉ , Multiplexer 39 ₁₀ , Multiplexer 39 ₁₁ , Multiplexer 39 ₆ to the Fiber Channel transmission line 41 ₁ to I / O adapters 22 ₀ / Director 20 ₀ , Port B by-pass card 34 ₂ works as described above to dock the A port of Director 20 ₁ / I / O adapter 22 ₁ to the B ports of disk drives 36 ₅ - 36 ₈ in response to the control section in it.

In the event of a failure in one of the disk drives 36 ₁ - 36 ₈ become the control sections 40 from the Directors 20 ₀ and 20 ₁ via control lines 45 ₀ respectively. 45 ₁ notified about this failure. Take for example a failure in disk drive 36 ₃ at. If such a failure is detected during normal operation, the control section changes 40 the logic state on control line C ₄ , thereby the input port A of multiplexer 39 ₄ from its output, and couples input port B from multiplexer 39 ₄ to its output, causing the disk drive 36 ₃ from the Fiber Channel transmission line sections 41 ₁ . 41 ₀ is bypassed. Likewise, if there is a failure in the disk drive 36 ₇ if such an error has been detected during normal operation, control section 40 (not pictured) in Port B Bypass Card 34 ₂ the logical state on a control line therein to thereby drive the disk drive 36 ₇ from the I / O adapter 22 ₁ / Director 20 ₁ decouple.

FAILURE OF DIRECTOR 20 ₀ or 20 ₁

As stated above, Director 20 ₀ during normal operation to the A ports of the disk drives 36 ₁ - 36 ₄ coupled and director 20 ₁ is to the B ports of the disk drives 36 ₆ - 36 ₈ coupled. In case of a failure in Director 20 ₀ becomes director 20 ₀ of disk drives 36 ₁ - 36 ₄ disconnected and Director 20 ₁ gets to the B ports of the disk drives 36 ₁ - 36 ₄ and remains attached to the B ports of the disk drives 36 ₆ - 19 ₈ coupled. Likewise, if there is a failure in Director 20 ₁ Director 20 ₁ of disk drives 36 ₅ - 36 ₈ disconnected and Director 20 ₀ goes to the A ports of the disk drives 36 ₅ - 36 ₈ and remains attached to the A ports of the disk drives 36 ₁ - 36 ₄ coupled. This is achieved (for example, removing the failed director 20 ₁ ) by the control signals coupling one of the A and B ports of the multiplexers coupled to the outputs of such multiplexers, as comprehensively described in the aforementioned patent application Ser. No. 09 / 343,344.

CONNECTION BETWEEN SYSTEM BACKPLANE AND PLATE BACKPLANE

In 1 and 4 to which reference is now made, the I / O adapters 22 ₀ - 22 ₁₅ to the front of a system backplane 50 connected and the directors 20 ₀ - 20 ₁₅ and the upper and lower memories 18H . 18L are at the back of the system backplane 50 connected shown. The arrangement is shown and described in more detail in the aforementioned co-pending application Serial No. 09 / 224,194. The I / O adapters 22 ₀ - 22 ₃ and 22 ₁₂ - 22 ₁₅ are with the Port A bypass card 34 ₁ and the Port B bypass card 34 ₂ the port bypass sections 23 ₁ to 23 ₈ connected as above in connection with 2 is discussed. Further, the port bypass sections 23 ₁ to 23 ₈ as noted above, in pairs, each pair being a corresponding one of the redundant Fiber Channel networks 25 ₁ - 25 ₄ is. Therefore, looking at an example of the redundant Fiber Channel networks 25 ₁ - 25 ₄ , here redundant Fiber Channel network 25 ₁ , and with reference to 4 to note that the I / O adapters 22 ₀ . 22 ₁ this redundant Fiber Channel network 25 ₁ by cable 52 ₀ respectively. 52 ₁ with the back of a board backplane board 54 are connected. These cables 52 ₀ . 52 ₁ be in contact with 5 described in detail. Here it is enough to say that each of the cables 52 ₀ . 52 ₁ is carried as a carrier for Fiber Channel signals and for non-Fiber Channel signals.

To the front of the plate backplane 54 are the Port A bypass card 34 ₁ and the Port B bypass card 34 ₂ of the redundant Fiber Channel network 25 ₁ connected. The back of the plate backplane 54 has slots 36 to record the disk drives 36 ₁ - 36 ₈ , as in 6 shown. An in 7 shown frame frame 56 preserves the disk drives 36 ₁ - 36 ₈ , the plate backplane 54 and the Port A and Port B bypass card 23 ₁ and 23z on. 7 shows only two disk drives 36 ₁ and 36 ₂ , where disk drive 36 ₂ Shown in a fully retracted position and disk drive 36 ₁ is shown in a partially inserted position. The in the 6 and 7 shown frame frame 56 is with twenty-four disk drive slots 36 and a slot 60 for recording two port bypass cards 36 ₁ and 36 ₂ configured. The plate backplane 54 is at the back of the frame 54 attached, as shown. The plate backplane 54 has eight electrical connectors 62 ( 8th ), each with a corresponding one of the slots 36 are accurate. The connectors are arranged to allow the disk drives 36 ₁ until here 36 ₈ to the electrical connectors 62 can be connected, it being understood that although there are eight disk drives 36 ₁ to 36 ₈ for illustrative purposes, but the system is designed for use with up to twenty-four disk drives. The disk drives are through unillustrated conductors in the disk backplane 54 electrically connected to each other.

In the 9 to 11 to which reference is now made, an exemplary of the housing 66 for disk drive 36 ₁ shown, wherein the disk drive in the 10 and 11 is shown in review, where 9 the housing 66 without the disk drive pointing. The disk drive carrier has a locking handle 68 on its front panel and screws 70 conventionally mounted on opposite sides thereof for engagement with the sides of the disk drive. Here's the disk drive case 66 but features of the invention, the decoupling occurring in the disk drive vibrations to the frame frame 56 and thereby the decoupling by the rack frame to the other disk drives in the rack frame 56 reduce. It was found that when there are many disk drives in the rack 56 are the vibrations through the rack 56 cause excessive vibration on the disk drives during operation of the drives that cause them to malfunction.

According to the invention, two features are used to decouple vibrations in the disk drive into the rack 56 to reduce. The first is the use of an elastic material, eg rubbery material 74 , on the housing 66 that with the frame 56 engages. Here is the case 66 with a majority, here four, of little legs 72 formed around each of the elastic material 74 is arranged as shown. As in 8th for the partially inserted disk drive 36 ₁ Most clearly, parts of the elate material protrude 74 over the sides of the case 66 out. It should be noted that the frame frame 56 ( 7 and 7A ) a plurality of horizontal elements 76 Has. Upper and lower pairs of horizontal elements 76 have vertically opposed pairs of recesses 72 in them. Each opposite pair of recesses 78 is for engaging the upper pair and the lower pair of legs 72 with the elastic material 74 around those little legs 72 configured around. This is in 7A more clearly illustrated. If the case 66 completely in the frame 66 is inserted, presses the elastic element firmly against the walls of the recesses 78 to dampen and thus suppress vibrations produced during operation of the disk drive, which may be decoupled to its housing so that it does not become the rack frame 66 be decoupled. That is, vibrations coupled out of the housing from the elastic shock-absorbing material 74 around the legs 72 be damped and that such vibrations thereby from the frame frame 56 be decoupled.

A second method used to decouple vibrations generated by the rack during operation of the disk drive 56 is used via the electrical interconnect arrangement used to connect the disk drive to the connector 62 ( 8th ) on the disk backplane 54 is used. In particular and also with reference to 9 becomes a flexible ribbon-type or strip-type electrical connector 57 ( 9 . 12 and 13 ) with a fastener attached thereto 59 ( 12 and 12A ) at the back of the tape-like connector 77 used. The fastener 59 has oval holes 61 ( 12A ) for receiving fixing screws 63 , The back of the case 66 is with a mounting plate 65 Mistake. The mounting plate 65 has a pair of screw-receiving devices attached thereto 67 for receiving the fixing screws 63 after the holes 61 on the devices 67 have been aligned. The screws 63 have a covenant 69 that the head the screw 63 from the fastener 59 spaced when the screw is firmly in the device 67 is screwed. The Bund 69 thereby causing a gap G1 between the fastener and the head of the screw 63 , Furthermore, the oval hole leaves 61 even after screwing the screw into the device 67 the lateral float back and forth 63 in the hole 61 to, with this reciprocation by the arrows A in 12A is shown.

The arrangement is designed to prevent when the fastener 59 with the screws 63 to the mounting plate 65 is screwed that the fastener 59 rigidly on the mounting plate 65 is attached. This is achieved by the fact that the screws 63 designed so that, when fully inserted into their proper threaded holes, the collar 69 and the oval holes 61 , In 13 to which reference is now made, the plug becomes 71 the flexible ribbon-type or strip-type electrical connector 57 with the plug 73 at the back of the disk drive 36 ₁ shown engaged. In such an arrangement, when decoupling vibrations in the drive to the rack and therefore to the tape fastener such oscillations are not coupled to the mounting plate, because the two are not rigidly interconnected due to the mechanism described above.

CABLE BETWEEN SYSTEM BACKPLANE AND PLATE DRIVE BACKPLANE

In the 5 . 5A and 5B to which reference is now made, an exemplary of the cables 52 ₀ . 52 ₁ containing the I / O adapters 22 ₀ - 22 ₃ and 22 ₁₂ - 22 ₁₅ connect, here cable 52 ₀ represented. As indicated above, the exemplary cable is 52 ₀ as carrier of both Fiber Channel and non-Fiber Channel signals. The Fiber Channel signals include the data for storage in the disk drives, and the non-Fiber Channel signals include the control signals described above for controlling the multiplexers in the Port Bypass cards, as well as other control signals for controlling the operation of the disk drives , Note that both the Fiber Channel and non-Fiber Channel signals pass through the same cable. Therefore, at each end of the cable, a single connector is used for both the fiber channel signals and the non-fiber channel signals.

In particular, and also with reference to 5A is shown that the cable 52 ₀ a central dielectric core 80 Has. The core is with the conventional quadrature pair of electrically insulated conductors 82a - 82d surrounded, which are arranged to transmit two pairs of differential fiber channel signals. A pair of signals (ie the signals from conductors 82a and 82b ), the data from the I / O adapter to the port bypass card, eg the data is on 41 ₁ in 3 and the other pair of signals (ie, the signals from conductors 82c and 82d ), the data from the port bypass card to the I / O adapter, ie the data on 41 ₀ in 3 , Around the quadrature pair of electrically insulated conductors 82a - 82d around is an inner conductive shield 86 arranged. Around the inner conductive shield 86 around is a plurality of, here ten, evenly spaced electrically insulated electrical conductors 88 arranged to transmit the non-Fiber Channel signals, eg for control signals. To the electrically insulated conductors 88 around is an outer conductive shield 92 arranged. To the outer conductive shield 92 around is a rubbery cladding 94 arranged.

The ends of the ladder 82a - 82d and the ends of the ten conductors 88 are with lugs or pins 85 with each of a pair of plugs 94a . 94b connected, as in 5B for plug 94a can be seen more clearly. In addition, the inner conductive shield 86 connected to one of the cable lugs and the outer conductive shield 92 is with the outer conductive housing 93 The plug 94a . 94b connected. It should be noted that each of the connectors here is a conventional 25-pin connector, which is why not all of the 25 pins are used here.

The Fiber channel data thus run through an internal electrostatic shielded region of the cable provided by the transmission medium and the control signals pass through an outer electrostatically shielded Region of the cable provided by the transmission medium. Further It should be noted that at each end of the cable for transmission the Fiber Channel signals and the non-Fiber Channel signals only one single plug is required.

RESILIENT MODE

In 14 to which reference is now made, is an alternative embodiment of the port bypass card 34 , here exemplary port A bypass card 34 ' ₁ , along with a B-port bypass card 34 ' ₂ and with the Port A and Port B bypass cards 34 ' ₁ and 34 ' ₂ coupled disk drive section 14 ₁ , as shown in the Detail shown. The port bypass cards 34 ' ₁ and 34 ' ₂ are each constructed identically. While looking at the Port A bypass card 34 ' ₁ therefore one sees that a failsafe controller 100 together with a fail-safe switch 102 is provided. The failover controller 100 the Port A bypass card 34 ' ₁ is used to detect a signal from the director 20 ₀ via the I / O adapter 22 ₀ used, indicating that the operation of the director 20 ₁ there is some "software" error, as opposed to a "hardware" error. For example, a type of "software" error could be in Director 20 ₁ cause that director 20 ₁ continued access to the disk drives in section 14 ₁ request, and such a strong "Busy condition" is by Director 20 ₀ recognized. After detecting such a "software" error in Director 20 ₁ gives the director 20 ₀ a failover command to the failover controller 100 in the A-port bypass card 34 ' ₁ out. In response to such a failover command, the failover controller generates 100 the A-port bypass card 34 ₁ a switching signal on line 104 for the fail-safe switch 102 in the Port B bypass card 34 ₂ , The desk 102 in the Port B bypass card 34 ' ₂ opens in response to the switching signal on line 104 and thereby couples the director 20 ₁ from the disk drives 36 ₁ to 36 ₈ in the disk drive section 14 ₁ from.

In particular, the switch 102 with the above in conjunction with 3 described bus 41 ₁ connected in series. This bus 41 ₁ is when switch 102 is normal (ie during normal non-default mode when switch is on 102 closed), with the A input of multiplexer 39 ₁ coupled as above in connection with 3 has been described. During failover mode when Director 20 ₀ a "software" failure in Director 20 ₁ detects, the switch opens 102 in the Port B bypass card 34 ' ₂ in response to the switching signal on line 104 to the director 20 ₁ from the B ports of the disk drives 36 ₁ - 36 ₈ in the disk drive section 14 ₁ decouple. Similarly, during a failover mode, eg when Director 20 ₁ a "software" failure in Director 20 ₀ detects the failover controller 100 the Port B bypass card 34 ' ₂ to recognize a signal from the director 20 ₁ via the I / O adapter 22 ₁ which indicates any "software" error, as opposed to a "hardware" error, in the operation of the director 20 ₀ is present. After detecting such a "software" error in Director 20 ₀ gives the director 20 ₁ a failover command to the failover controller 100 in the A-port bypass card 34 ' ₂ out. In response to such a failover command, the failover controller generates 100 the Port B bypass card 34 ₂ a switching signal on line 106 for the fail-safe switch 102 in the Port B bypass card 34 ₁ , The desk 102 in the Port A bypass card 34 ' ₁ opens in response to the switching signal on line 106 and thereby couples the director 20 ₁ from the disk drives 36 ₁ to 36 ₈ in the disk drive section 14 ₁ from.

It should be noted that the lines 104 and 106 in the disk backplane 54 ( 4 ) are arranged.

The failover controller 100 This ensures failover commands for port bypass control (eg reset and power control). This feature is provided to provide a smooth and reliable transition in the event of a Director failover when a director needs to be taken out of the Fiber Channel "loop." Here, the failover controllers 100 handle three commands: Card Reset, Card Power Off, and Card Power On. The order of these commands is as follows, with the example failsafe controller 100 the Port A bypass card 34 ₁ is considered: The command bus 108 the failover controller 100 the Port A bypass card 34 ' ₁ from its associated (ie, attached) director 20 ₁ must start at rest. When a command is to be executed, the associated director 20 ₀ issued a Command Verify command. Thereafter, one of the Action Commands (Reset, Card Power On, Card Power Off) is issued, followed by an Execute <Type> execution command, where <Type> is the desired action. If this order is met, then when the execute command is issued, the action is taken from the remote port bypass card, here the port B bypass card 34 ' ₂ , carried out. The bus 108 then returns to hibernation.

The command bus 108 that transmits these commands has three bits of data plus one parity bit. These four bits form sixteen codes, as described below:

The control sequence is designed to handle hardware failures in the control bus 108 to discover by forcing the bus state from idle (000) to command check (111) to start the command sequence. The actual command consists of the combination code and binary inversion (eg Card Reset <001> and Execute Reset <110>), which can detect all trapping errors, and a parity bit, which provides further protection against invalid codes. Any deviation from the above sequence sets the hardware of the failover controller 100 back and no action is taken. This sequence control protects against code errors or execution errors that unintentionally transfer data to the failover controller 100 write. The sequence state diagram is in 15 displayed.

REAR-END I / O ADAPTER HUB THE I / O ADAPTER FIBER CHANNEL HUBS

In 16 to which reference is now being made to alternative I / O adapters 22 _'0 . 22 ' ₁ and port bypass sections 23 ' ₁ . 23 ' ₂ for use in the redundant Fiber Channel networks 25 ₁ - 25 ₄ ( 1 ) shown here in 16 for the exemplary redundant Fiber Channel network 25 ' to be shown. It can therefore be seen that the I / O adapters 22 _'0 and 22 ' ₁ from network 25 ₁ one pair each of Fiber Channel switching hubs 80A . 80B has, as shown. The hubs 80A and 80B are identical in construction, with an example of this, here the hub 80A of I / O adapters 22 _'0 , shown in detail. This hub 80A has a Fiber Channel input 82 on that with the A-port of the director 20 ₀ connected is. It should be noted that the hub 80B of I / O adapters 22 _'0 to the B-Port of Director 20 ₀ coupled as shown. Equally, the hub 80A of I / O adapters 22 ₁ to the A-Port of Director 20 ₁ docked and the hub 80B of I / O adapters 22 ' ₁ is to the B-Port of Director 20 ₁ docked as shown. It should be noted that the number of disk drives in each disk drive section 14 ' ₁ and 14 ' ₂ here was doubled from eight to sixteen (ie disk drives 36 ₁ to _{16 16} ).

Again referring to the exemplary hub 80A of I / O adapters 22 _'0 Taking, such a hub with drivers 84 . 86 . 88 . 90 . 92 and 94 and multiplexers 96 and 98 shown, all of which are arranged as shown. One of the pair of input ports of the multiplexers coupled to its output 96 . 98 is through the on line 100 respectively. 102 applied control signal selected as shown. The control signal on line 100 is therefore connected to multiplexer 96 created and the control signal to line 102 gets to multiplexer 98 created. The control signals on lines 100 and 102 be from the director 20 ₁ for the hubs 80A and 80B in the I / O adapter 22 _'0 generated and the equivalent control signals for the hubs 80A and 80B the I / O adapter 22 ' ₁ be from the director 20 ₁ generated.

Regarding the port bypass sections 23 ' ₁ and 23 ' ₂ you can see first that they are identical in structure, with an example of this, here section 23 ' ₁ , shown in detail and a Port-A-By matching card 34 ' ₁ and a Port B bypass card 34 ' ₂ having. It should be noted that here is any port bypass card 34 ' ₁ and 34 ' ₂ two redundant of the above in conjunction with 3 has described port bypass cards. Here supplies the upper Port A bypass card 34 ' ₁ eight disk drives in disk drive section 14 ₁ and the lower port A bypass card 34 ' ₁ Supplies another set of here eight disk drives in the disk drive section 14 ' ₁ , While looking at the A port of the director 20 ₀ you notice that the hub 80A many different coupling configurations with the disk drive sections 14 ₁ and 14 ' ₁ allows, depending on the logical state of the Director 20 ₀ to the control lines 100 and 102 the multiplexer 96 . 98 applied signals. In a first configuration, the data is taken from the A port of Director 20 ₀ through drivers 84 , then by drivers 88 , then to the upper A-port bypass card 34 ₁ , then to driver 90 , then by multiplexer 96 and by drivers 86 back to the a-port of the director 20 ₀ passed, reducing the bottom port A bypass card 34 ₁ is bypassed.

In a second configuration, the data is taken from the A port of Director 20 ₀ through drivers 84 , then by multiplexer 98 , then by drivers 94 , then through the lower A-port bypass card 34 ₁ , then to driver 92 , then by multiplexer 96 and by drivers 86 back to the a-port of the director 20 ₀ passed, causing the upper port-A-bypass card 34 ₁ is bypassed.

In a third configuration, the data is taken from the A port of Director 20 ₀ through drivers 84 , then driver 88 , then through the upper A-port bypass card 34 ₁ , then by drivers 90 , then by multiplexer 98 , then by drivers 94 , then to the lower port A bypass card 34 ₁ , then by drivers 92 , then by multiplexer 96 , then by drivers 86 back to the a-port of the director 20 ₀ directed.

FRONT-END I / O ADAPTER HUB

In 17 to which reference is now made, an exemplary of the front-end I / O adapters 22 ₄ - 22 ₁₃ , here I / O adapter 22 ₄ , with a pair of ports P ₁ , P ₂ for coupling to Director 20 ₄ and a plurality of ports P ₃ -P ₆ , here four, for communication with the host computer, here with four host computer sections 12 ₁ - 12 ₄ the host computer 12 ( 1 ) through a Fiber Channel hub 201 shown. The hub 201 of I / O adapters 22 ₄ includes a plurality of electro-optic transceivers 200 ₁ - 200 ₄ each having a laser for transmitting data to the host computer section coupled thereto and a laser receiver for receiving data from such a coupled host computer section. transceiver 200 ₁ - 200 ₄ are thus to the respective host computer sections 12 ₁ - 12 ₄ coupled as shown. Each of the transceivers 200 ₁ - 200 ₄ is with a corresponding one of a plurality of switching sections 202 ₁ - 204 ₄ , here four, coupled. Each of the switching sections has a receiver retimer 204 , a send retimer 206 and a multiplexer 208 on, which are arranged as shown. Each of the multiplexers 208 in the sections 202 ₁ - 202 ₄ is controlled by control signals on respective lines L1-L4 as shown. The control signals on lines L1-L4 are from a multiplexer controller 210 created. The from the multiplexer controller 210 applied control signals are generated according to the instructions given by the Director 20 ₄ that is connected to I / O adapter 22 ₄ is coupled, generates applied control signal.

The arrangement determines the distribution between Director 20 ₄ and at least one selected one of the host computer sections 200 ₁ - 200 ₄ , In particular, and in relation to data from the Director 20 ₄ to data from the director 20 ₄ such data becomes an input to the multiplexer section 202 ₄ transfer. The data may be selectively sent to the transceiver in accordance with the control signal on line L4 200 ₄ or to the multiplexer section 202 ₃ to get redirected. Therefore, the control signal on line L1 selects port A from multiplexer 208 in section 202 ₄ off when communicating with host section 12 ₄ is desired. On the other hand, if such communication is not desired (ie

Host section 12 ₄ is to be bypassed), the control signal on line L4 causes the data on the B port of the multiplexer 208 such a multiplexer section 202 ₄ directly to the exit of this section 202 ₄ be directed.

It should also be noted that if port A is to allow communication with the host computer section 12 ₄ is selected, the data to the host computer section 12 ₄ via the send retimer 206 run and data from the host computer section 12 ₄ via the reception retimer 204 to run.

It is understood that each of the front-end directors has a pair of ports and therefore the I / O adapter associated with such a director has a pair of hubs 201 each paired to a corresponding one of the ports of the front-end director.

SIGNAL INTEGRITY TESTER

Regarding 18 Now a method for checking the signal integrity of the signals on the system backplane 50 ( 4 ). The Directors 20 ₀ - 20 ₁₅ and I / O adapters 22 ₀ - 22 ₁₅ again referring to 1 and 4 , are in an array of slots on opposite sides in the system backplane 50 plugged. The arrangement is described in the above co-pending patent application serial no. 09 / 224,194, filed December 30, 1998, entitled DATA STORAGE SYSTEM, inventor Mark Zani, in more detail.

In the 19 . 19A . 19B and 20 For the sake of simplicity, illustrations are shown in this co-pending patent application. You can see that the system backplane 50n a plurality of slots 32 ₀ - 32 ₁₉ with the slots in the front of it designed to accept the front-end and rear-end directors and the memory and the slots in the back of it to receive the front-end and rear-end I / O. A adapters are executed. Each slot has a large majority of pins to accommodate the directors, I / O adapters, and memory, as in the 19A and 19B shown. It should also be noted that the buses TH, TL, BH and BL appear as transmission lines for the high-speed data thereon.

The system backplane 50 , in relation to 20 so typically has several hundred pins for each Director slot. The following test procedure is to check the signal integrity at each of the slots. It should be understood that due to various loading effects at various slots along the buses, the waveform of the signals on a bus would appear slightly different from slot to slot. To verify that the signal integrity (ie, the waveform of the signal) at each slot of the backplane is acceptable, ie, within the prescribed values, is a test board or card 300 provided, this test board in 18 will be shown. The test board 300 The task is to replace each of the directors and memory during a test mode, thereby enabling the waveforms on the pins to be inspected in the slot occupied by such a director and memory slot.

Special is the test board 300 a plurality of transceivers 302 shown, each with each of the pins of the board 300 are coupled. The transceivers 302 are to a multiplexer section 304 coupled. Here, for ease of explanation, the multiplexer section has seven multiplexers 303 ₁ - 303 ₇ It should be understood that for several hundreds of pins, there would have to be a considerably larger number of multiplexers. In any case, the board has 300 a multiplexer control section 306 for each of the multiplexers in the multiplexer section 304 generates a control signal on line N ₁ -N ₇ . In response to the control signals, a selected one of the pins thereby becomes an output port P _{0 of} the test card 300 coupled. Thus, the signal at each of the pins can be selectively coupled to the output port P ₀ . The output port P ₀ is to an oscilloscope 310 coupled. A personal computer PC 312 is for controlling multiplexer control section 306 and oscilloscope 310 used.

So will be successively at each slot 32 ₀ - 32 ₁₉ ( 19 . 19A and 19B ) the signal on each of the pins with the oscilloscope 310 examined and in the PC 312 recorded.

During test mode is the test board 300 in one of the slots 32 ₀ - 32 ₁₅ , After testing the waveform on each of the pins at that slot, the test board becomes 300 plugged into another of the slots and the process repeated on the transposed test board. The process is repeated until the waveform on each of the pins in that slot and at each of the slots with the backplane 50 under full load conditions (ie, with the directors and stores except for the director and memory, which are usually in the slot that is being tested) and the I / O adapters attached to the system backplane.

Claims (4)

A method of transmitting fiber channel signals and non-fiber channel signals, comprising the steps of: providing a cable ( 52 ₀ ), the cable comprising: a pair of connectors ( 94a , b), one at one end of the cable, the other at the other end thereof, each of which has a plurality of pins ( 85 ), a first plurality of ladders ( 82a d), the ends of these conductors being connected to pins in each of the pair of connectors, and a second plurality of conductors (14) disposed around the first plurality of conductors (Figs. 88 ), wherein the ends of these conductors with pins in each of the pair of connectors ver and a conductive shield disposed between the first plurality of conductors and the second plurality of conductors (FIG. 86 ); Transmitting the fiber channel signals through the first plurality of conductors and transmitting non-fiber channel signals through the second plurality of conductors. The method of claim 1, wherein the first plurality of conductors comprises a quadrature pair of electrically isolated conductors ( 82a -d) for transmitting two pairs of differential fiber channel signals. Method according to Claim 2, in which the quadrature conductor pair are arranged around a central dielectric core ( 80 ) is arranged around. Method according to one of the preceding claims, in which an outer conductive shield ( 92 ) is arranged around the second plurality of conductors.