DE60025196D1 - Heterogenes programmierbares gatterfeld - Google Patents
Heterogenes programmierbares gatterfeldInfo
- Publication number
- DE60025196D1 DE60025196D1 DE60025196T DE60025196T DE60025196D1 DE 60025196 D1 DE60025196 D1 DE 60025196D1 DE 60025196 T DE60025196 T DE 60025196T DE 60025196 T DE60025196 T DE 60025196T DE 60025196 D1 DE60025196 D1 DE 60025196D1
- Authority
- DE
- Germany
- Prior art keywords
- array
- unstructured
- structured
- logic sub
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17736—Structural details of routing resources
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/1778—Structural details for adapting physical parameters
- H03K19/17796—Structural details for adapting physical parameters for physical disposition of blocks
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13314599P | 1999-05-07 | 1999-05-07 | |
US133145P | 1999-05-07 | ||
PCT/US2000/012478 WO2000069073A1 (en) | 1999-05-07 | 2000-05-05 | Heterogeneous programmable gate array |
Publications (2)
Publication Number | Publication Date |
---|---|
DE60025196D1 true DE60025196D1 (de) | 2006-02-02 |
DE60025196T2 DE60025196T2 (de) | 2006-09-07 |
Family
ID=22457222
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE60025196T Expired - Lifetime DE60025196T2 (de) | 1999-05-07 | 2000-05-05 | Heterogenes programmierbares gatterfeld |
Country Status (9)
Country | Link |
---|---|
US (1) | US6433578B1 (de) |
EP (1) | EP1177631B1 (de) |
JP (1) | JP2002544700A (de) |
KR (1) | KR100761328B1 (de) |
AT (1) | ATE314754T1 (de) |
AU (1) | AU5127600A (de) |
CA (1) | CA2371080A1 (de) |
DE (1) | DE60025196T2 (de) |
WO (1) | WO2000069073A1 (de) |
Families Citing this family (36)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6366120B1 (en) * | 1999-03-04 | 2002-04-02 | Altera Corporation | Interconnection resources for programmable logic integrated circuit devices |
US6686767B1 (en) * | 1999-05-07 | 2004-02-03 | Morphics Technology Inc. | Apparatus and method for controlling a three-state bus |
US7249242B2 (en) | 2002-10-28 | 2007-07-24 | Nvidia Corporation | Input pipeline registers for a node in an adaptive computing engine |
US7433909B2 (en) | 2002-06-25 | 2008-10-07 | Nvidia Corporation | Processing architecture for a reconfigurable arithmetic node |
US7624204B2 (en) * | 2001-03-22 | 2009-11-24 | Nvidia Corporation | Input/output controller node in an adaptable computing environment |
US6836839B2 (en) | 2001-03-22 | 2004-12-28 | Quicksilver Technology, Inc. | Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements |
US7962716B2 (en) | 2001-03-22 | 2011-06-14 | Qst Holdings, Inc. | Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements |
US20030054774A1 (en) * | 2001-03-22 | 2003-03-20 | Quicksilver Technology, Inc. | Method and system for managing hardware resources to implement system acquisition using an adaptive computing architecture |
US7653710B2 (en) | 2002-06-25 | 2010-01-26 | Qst Holdings, Llc. | Hardware task manager |
US7325123B2 (en) * | 2001-03-22 | 2008-01-29 | Qst Holdings, Llc | Hierarchical interconnect for configuring separate interconnects for each group of fixed and diverse computational elements |
US7752419B1 (en) | 2001-03-22 | 2010-07-06 | Qst Holdings, Llc | Method and system for managing hardware resources to implement system functions using an adaptive computing architecture |
US6577678B2 (en) | 2001-05-08 | 2003-06-10 | Quicksilver Technology | Method and system for reconfigurable channel coding |
US7046635B2 (en) | 2001-11-28 | 2006-05-16 | Quicksilver Technology, Inc. | System for authorizing functionality in adaptable hardware devices |
US6986021B2 (en) | 2001-11-30 | 2006-01-10 | Quick Silver Technology, Inc. | Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements |
US8412915B2 (en) | 2001-11-30 | 2013-04-02 | Altera Corporation | Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements |
US7644279B2 (en) * | 2001-12-05 | 2010-01-05 | Nvidia Corporation | Consumer product distribution in the embedded system market |
US7215701B2 (en) | 2001-12-12 | 2007-05-08 | Sharad Sambhwani | Low I/O bandwidth method and system for implementing detection and identification of scrambling codes |
US7403981B2 (en) | 2002-01-04 | 2008-07-22 | Quicksilver Technology, Inc. | Apparatus and method for adaptive multimedia reception and transmission in communication environments |
US7660984B1 (en) | 2003-05-13 | 2010-02-09 | Quicksilver Technology | Method and system for achieving individualized protected space in an operating system |
US7328414B1 (en) | 2003-05-13 | 2008-02-05 | Qst Holdings, Llc | Method and system for creating and programming an adaptive computing engine |
US7620678B1 (en) | 2002-06-12 | 2009-11-17 | Nvidia Corporation | Method and system for reducing the time-to-market concerns for embedded system design |
US7471643B2 (en) | 2002-07-01 | 2008-12-30 | Panasonic Corporation | Loosely-biased heterogeneous reconfigurable arrays |
US7461234B2 (en) | 2002-07-01 | 2008-12-02 | Panasonic Corporation | Loosely-biased heterogeneous reconfigurable arrays |
US7802108B1 (en) | 2002-07-18 | 2010-09-21 | Nvidia Corporation | Secure storage of program code for an embedded system |
US8108656B2 (en) | 2002-08-29 | 2012-01-31 | Qst Holdings, Llc | Task definition for specifying resource requirements |
US7502915B2 (en) * | 2002-09-30 | 2009-03-10 | Nvidia Corporation | System and method using embedded microprocessor as a node in an adaptable computing machine |
US7937591B1 (en) | 2002-10-25 | 2011-05-03 | Qst Holdings, Llc | Method and system for providing a device which can be adapted on an ongoing basis |
US8949576B2 (en) * | 2002-11-01 | 2015-02-03 | Nvidia Corporation | Arithmetic node including general digital signal processing functions for an adaptive computing machine |
US8276135B2 (en) | 2002-11-07 | 2012-09-25 | Qst Holdings Llc | Profiling of software and circuit designs utilizing data operation analyses |
US7225301B2 (en) | 2002-11-22 | 2007-05-29 | Quicksilver Technologies | External memory controller node |
US7609297B2 (en) * | 2003-06-25 | 2009-10-27 | Qst Holdings, Inc. | Configurable hardware based digital imaging apparatus |
US8296764B2 (en) | 2003-08-14 | 2012-10-23 | Nvidia Corporation | Internal synchronization control for adaptive integrated circuitry |
US7174432B2 (en) | 2003-08-19 | 2007-02-06 | Nvidia Corporation | Asynchronous, independent and multiple process shared memory system in an adaptive computing architecture |
JP3887622B2 (ja) * | 2003-10-17 | 2007-02-28 | 松下電器産業株式会社 | データ処理装置 |
US7987065B1 (en) | 2007-04-17 | 2011-07-26 | Nvidia Corporation | Automatic quality testing of multimedia rendering by software drivers |
JP5990466B2 (ja) | 2010-01-21 | 2016-09-14 | スビラル・インコーポレーテッド | ストリームに基づく演算を実装するための汎用複数コアシステムのための方法および装置 |
Family Cites Families (36)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2180382B (en) | 1985-09-11 | 1989-11-22 | Pilkington Micro Electronics | Semi-conductor integrated circuits/systems |
US4775942A (en) * | 1985-12-09 | 1988-10-04 | International Business Machines Corporation | Seed and stitch approach to embedded arrays |
US5452231A (en) | 1988-10-05 | 1995-09-19 | Quickturn Design Systems, Inc. | Hierarchically connected reconfigurable logic assembly |
US5329470A (en) | 1988-12-02 | 1994-07-12 | Quickturn Systems, Inc. | Reconfigurable hardware emulation system |
US5361373A (en) * | 1992-12-11 | 1994-11-01 | Gilson Kent L | Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfigurable instruction execution means and method therefor |
US5362999A (en) | 1993-03-18 | 1994-11-08 | Xilinx, Inc. | EPLD chip with hybrid architecture optimized for both speed and flexibility |
US5317212A (en) * | 1993-03-19 | 1994-05-31 | Wahlstrom Sven E | Dynamic control of configurable logic |
US5761484A (en) | 1994-04-01 | 1998-06-02 | Massachusetts Institute Of Technology | Virtual interconnections for reconfigurable logic systems |
US5572148A (en) * | 1995-03-22 | 1996-11-05 | Altera Corporation | Programmable logic array integrated circuit with general-purpose memory configurable as a random access or FIFO memory |
GB9508931D0 (en) * | 1995-05-02 | 1995-06-21 | Xilinx Inc | Programmable switch for FPGA input/output signals |
US5723984A (en) * | 1996-06-07 | 1998-03-03 | Advanced Micro Devices, Inc. | Field programmable gate array (FPGA) with interconnect encoding |
US5640107A (en) | 1995-10-24 | 1997-06-17 | Northrop Grumman Corporation | Method for in-circuit programming of a field-programmable gate array configuration memory |
US5943242A (en) | 1995-11-17 | 1999-08-24 | Pact Gmbh | Dynamically reconfigurable data processing system |
US5734582A (en) | 1995-12-12 | 1998-03-31 | International Business Machines Corporation | Method and system for layout and schematic generation for heterogeneous arrays |
US5914906A (en) * | 1995-12-20 | 1999-06-22 | International Business Machines Corporation | Field programmable memory array |
US5804986A (en) * | 1995-12-29 | 1998-09-08 | Cypress Semiconductor Corp. | Memory in a programmable logic device |
US5787007A (en) * | 1996-01-30 | 1998-07-28 | Xilinx, Inc. | Structure and method for loading RAM data within a programmable logic device |
US5677638A (en) * | 1996-02-02 | 1997-10-14 | Xilinx, Inc. | High speed tristate bus with multiplexers for selecting bus driver |
US5744980A (en) | 1996-02-16 | 1998-04-28 | Actel Corporation | Flexible, high-performance static RAM architecture for field-programmable gate arrays |
GB9604496D0 (en) * | 1996-03-01 | 1996-05-01 | Xilinx Inc | Embedded memory for field programmable gate array |
US5726584A (en) * | 1996-03-18 | 1998-03-10 | Xilinx, Inc. | Virtual high density programmable integrated circuit having addressable shared memory cells |
US5796269A (en) * | 1996-04-09 | 1998-08-18 | Xilinx, Inc. | Composable memory array for a programmable logic device and method for implementing same |
US5977791A (en) * | 1996-04-15 | 1999-11-02 | Altera Corporation | Embedded memory block with FIFO mode for programmable logic device |
US5825202A (en) * | 1996-09-26 | 1998-10-20 | Xilinx, Inc. | Integrated circuit with field programmable and application specific logic areas |
US5946219A (en) | 1996-10-30 | 1999-08-31 | Atmel Corporation | Method and system for configuring an array of logic devices |
DE19647181A1 (de) | 1996-11-14 | 1998-05-20 | Siemens Ag | Zur Abarbeitung von Softwareprogrammen ausgelegte integrierte Schaltung |
US6005410A (en) * | 1996-12-05 | 1999-12-21 | International Business Machines Corporation | Interconnect structure between heterogeneous core regions in a programmable array |
DE19654593A1 (de) | 1996-12-20 | 1998-07-02 | Pact Inf Tech Gmbh | Umkonfigurierungs-Verfahren für programmierbare Bausteine zur Laufzeit |
US5874834A (en) * | 1997-03-04 | 1999-02-23 | Xilinx, Inc. | Field programmable gate array with distributed gate-array functionality |
US6020759A (en) * | 1997-03-21 | 2000-02-01 | Altera Corporation | Programmable logic array device with random access memory configurable as product terms |
US6075380A (en) * | 1997-06-26 | 2000-06-13 | Altera Corporation | Programmable logic device with expandable-width memory regions |
US6195788B1 (en) | 1997-10-17 | 2001-02-27 | Altera Corporation | Mapping heterogeneous logic elements in a programmable logic device |
US6091263A (en) * | 1997-12-12 | 2000-07-18 | Xilinx, Inc. | Rapidly reconfigurable FPGA having a multiple region architecture with reconfiguration caches useable as data RAM |
US7389487B1 (en) | 1998-04-28 | 2008-06-17 | Actel Corporation | Dedicated interface architecture for a hybrid integrated circuit |
US6020776A (en) | 1998-06-22 | 2000-02-01 | Xilinx, Inc. | Efficient multiplexer structure for use in FPGA logic blocks |
US6154052A (en) * | 1999-02-04 | 2000-11-28 | Xilinx, Inc. | Combined tristate/carry logic mechanism |
-
2000
- 2000-05-05 CA CA002371080A patent/CA2371080A1/en not_active Abandoned
- 2000-05-05 AU AU51276/00A patent/AU5127600A/en not_active Abandoned
- 2000-05-05 EP EP00935880A patent/EP1177631B1/de not_active Expired - Lifetime
- 2000-05-05 WO PCT/US2000/012478 patent/WO2000069073A1/en not_active Application Discontinuation
- 2000-05-05 US US09/565,648 patent/US6433578B1/en not_active Expired - Lifetime
- 2000-05-05 KR KR1020017014233A patent/KR100761328B1/ko not_active IP Right Cessation
- 2000-05-05 DE DE60025196T patent/DE60025196T2/de not_active Expired - Lifetime
- 2000-05-05 AT AT00935880T patent/ATE314754T1/de not_active IP Right Cessation
- 2000-05-05 JP JP2000617558A patent/JP2002544700A/ja active Pending
Also Published As
Publication number | Publication date |
---|---|
JP2002544700A (ja) | 2002-12-24 |
US6433578B1 (en) | 2002-08-13 |
CA2371080A1 (en) | 2000-11-16 |
KR20020013539A (ko) | 2002-02-20 |
KR100761328B1 (ko) | 2007-09-27 |
EP1177631A4 (de) | 2002-07-03 |
ATE314754T1 (de) | 2006-01-15 |
EP1177631A1 (de) | 2002-02-06 |
WO2000069073A1 (en) | 2000-11-16 |
DE60025196T2 (de) | 2006-09-07 |
EP1177631B1 (de) | 2005-12-28 |
AU5127600A (en) | 2000-11-21 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |