DE60009732T2 - Ein arbitrierungsprotokoll für einen gemeinsamen daten-zwischenspeicher - Google Patents

Ein arbitrierungsprotokoll für einen gemeinsamen daten-zwischenspeicher Download PDF

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Publication number
DE60009732T2
DE60009732T2 DE60009732T DE60009732T DE60009732T2 DE 60009732 T2 DE60009732 T2 DE 60009732T2 DE 60009732 T DE60009732 T DE 60009732T DE 60009732 T DE60009732 T DE 60009732T DE 60009732 T2 DE60009732 T2 DE 60009732T2
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DE
Germany
Prior art keywords
common data
intermediate storage
data intermediate
arbitration protocol
arbitration
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60009732T
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English (en)
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DE60009732D1 (de
Inventor
Marc Tremblay
Andre Kowalczyk
S Tirumala
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Sun Microsystems Inc
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Publication of DE60009732D1 publication Critical patent/DE60009732D1/de
Application granted granted Critical
Publication of DE60009732T2 publication Critical patent/DE60009732T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5011—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
    • G06F9/5016—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals the resource being the memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0855—Overlapped cache accessing, e.g. pipeline
    • G06F12/0857—Overlapped cache accessing, e.g. pipeline by multiple requestors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0855—Overlapped cache accessing, e.g. pipeline
    • G06F12/0859—Overlapped cache accessing, e.g. pipeline with reload from main memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
DE60009732T 1999-10-01 2000-09-29 Ein arbitrierungsprotokoll für einen gemeinsamen daten-zwischenspeicher Expired - Lifetime DE60009732T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/411,470 US6704822B1 (en) 1999-10-01 1999-10-01 Arbitration protocol for a shared data cache
PCT/US2000/026813 WO2001025921A1 (en) 1999-10-01 2000-09-29 An arbitration protocol for a shared data cache

Publications (2)

Publication Number Publication Date
DE60009732D1 DE60009732D1 (de) 2004-05-13
DE60009732T2 true DE60009732T2 (de) 2005-04-21

Family

ID=23629068

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60009732T Expired - Lifetime DE60009732T2 (de) 1999-10-01 2000-09-29 Ein arbitrierungsprotokoll für einen gemeinsamen daten-zwischenspeicher

Country Status (6)

Country Link
US (1) US6704822B1 (de)
EP (1) EP1221095B1 (de)
JP (1) JP4714396B2 (de)
AU (1) AU7622300A (de)
DE (1) DE60009732T2 (de)
WO (1) WO2001025921A1 (de)

Families Citing this family (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1376348A3 (de) * 2002-06-27 2007-08-22 Fujitsu Limited Verfahren und Vorrichtung zur Erzeugung eines Lademoduls
EP2477109B1 (de) 2006-04-12 2016-07-13 Soft Machines, Inc. Vorrichtung und Verfahren zur Verarbeitung einer Anweisungsmatrix zur Spezifizierung von parallelen und abhängigen Betriebsabläufen
US8677105B2 (en) 2006-11-14 2014-03-18 Soft Machines, Inc. Parallel processing of a sequential program using hardware generated threads and their instruction groups executing on plural execution units and accessing register file segments using dependency inheritance vectors across multiple engines
US8639885B2 (en) * 2009-12-21 2014-01-28 Oracle America, Inc. Reducing implementation costs of communicating cache invalidation information in a multicore processor
US8195883B2 (en) * 2010-01-27 2012-06-05 Oracle America, Inc. Resource sharing to reduce implementation costs in a multicore processor
EP3156896B1 (de) 2010-09-17 2020-04-08 Soft Machines, Inc. Mehrfach verzweigte einzelzyklusvorhersage mit einem latenten cache für frühe und entfernte verzweigungsvorhersage
KR101636602B1 (ko) 2011-03-25 2016-07-05 소프트 머신즈, 인크. 분할가능한 엔진에 의해 인스턴스화된 가상 코어를 이용한 코드 블록의 실행을 지원하는 메모리 프래그먼트
WO2012135041A2 (en) 2011-03-25 2012-10-04 Soft Machines, Inc. Register file segments for supporting code block execution by using virtual cores instantiated by partitionable engines
KR101638225B1 (ko) 2011-03-25 2016-07-08 소프트 머신즈, 인크. 분할가능한 엔진에 의해 인스턴스화된 가상 코어를 이용한 명령어 시퀀스 코드 블록의 실행
KR101639854B1 (ko) 2011-05-20 2016-07-14 소프트 머신즈, 인크. 복수의 엔진에 의해 명령어 시퀀스들의 실행을 지원하기 위한 상호접속 구조
TWI666551B (zh) 2011-05-20 2019-07-21 美商英特爾股份有限公司 以複數個引擎作資源與互連結構的分散式分配以支援指令序列的執行
EP2783280B1 (de) 2011-11-22 2019-09-11 Intel Corporation Beschleunigter codeoptimierer für einen mehrmotor-mikroprozessor
WO2013077876A1 (en) 2011-11-22 2013-05-30 Soft Machines, Inc. A microprocessor accelerated code optimizer
US8930674B2 (en) 2012-03-07 2015-01-06 Soft Machines, Inc. Systems and methods for accessing a unified translation lookaside buffer
US9229873B2 (en) 2012-07-30 2016-01-05 Soft Machines, Inc. Systems and methods for supporting a plurality of load and store accesses of a cache
WO2014022115A1 (en) * 2012-07-30 2014-02-06 Soft Machines, Inc. Systems and methods for supporting a plurality of load accesses of a cache in a single cycle
US9916253B2 (en) 2012-07-30 2018-03-13 Intel Corporation Method and apparatus for supporting a plurality of load accesses of a cache in a single cycle to maintain throughput
US9740612B2 (en) 2012-07-30 2017-08-22 Intel Corporation Systems and methods for maintaining the coherency of a store coalescing cache and a load cache
US9710399B2 (en) 2012-07-30 2017-07-18 Intel Corporation Systems and methods for flushing a cache with modified data
US9430410B2 (en) 2012-07-30 2016-08-30 Soft Machines, Inc. Systems and methods for supporting a plurality of load accesses of a cache in a single cycle
US9678882B2 (en) 2012-10-11 2017-06-13 Intel Corporation Systems and methods for non-blocking implementation of cache flush instructions
WO2014150971A1 (en) 2013-03-15 2014-09-25 Soft Machines, Inc. A method for dependency broadcasting through a block organized source view data structure
WO2014150806A1 (en) 2013-03-15 2014-09-25 Soft Machines, Inc. A method for populating register view data structure by using register template snapshots
US9891924B2 (en) 2013-03-15 2018-02-13 Intel Corporation Method for implementing a reduced size register view data structure in a microprocessor
WO2014150991A1 (en) 2013-03-15 2014-09-25 Soft Machines, Inc. A method for implementing a reduced size register view data structure in a microprocessor
US9904625B2 (en) 2013-03-15 2018-02-27 Intel Corporation Methods, systems and apparatus for predicting the way of a set associative cache
CN105210040B (zh) 2013-03-15 2019-04-02 英特尔公司 用于执行分组成块的多线程指令的方法
US9811342B2 (en) 2013-03-15 2017-11-07 Intel Corporation Method for performing dual dispatch of blocks and half blocks
US10275255B2 (en) 2013-03-15 2019-04-30 Intel Corporation Method for dependency broadcasting through a source organized source view data structure
KR20150130510A (ko) 2013-03-15 2015-11-23 소프트 머신즈, 인크. 네이티브 분산된 플래그 아키텍처를 이용하여 게스트 중앙 플래그 아키텍처를 에뮬레이션하는 방법
US9569216B2 (en) 2013-03-15 2017-02-14 Soft Machines, Inc. Method for populating a source view data structure by using register template snapshots
US9886279B2 (en) 2013-03-15 2018-02-06 Intel Corporation Method for populating and instruction view data structure by using register template snapshots
US10140138B2 (en) 2013-03-15 2018-11-27 Intel Corporation Methods, systems and apparatus for supporting wide and efficient front-end operation with guest-architecture emulation
US9223716B2 (en) * 2013-10-04 2015-12-29 The Penn State Research Foundation Obstruction-aware cache management
GB2529180B (en) 2014-08-12 2021-07-14 Advanced Risc Mach Ltd Arbitration and hazard detection for a data processing apparatus
US9858373B2 (en) 2015-07-15 2018-01-02 International Business Machines Corporation In-cycle resource sharing for high-level synthesis of microprocessors
CN107025130B (zh) 2016-01-29 2021-09-03 华为技术有限公司 处理节点、计算机系统及事务冲突检测方法
US10552343B2 (en) * 2017-11-29 2020-02-04 Intel Corporation Zero thrash cache queue manager
CN109491785B (zh) * 2018-10-24 2021-01-26 龙芯中科技术股份有限公司 内存访问调度方法、装置及设备
FR3093197A1 (fr) * 2019-02-21 2020-08-28 Stmicroelectronics (Grenoble 2) Sas Procédé d’arbitrage d’accès à une mémoire partagée, et dispositif électronique correspondant

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5367678A (en) 1990-12-06 1994-11-22 The Regents Of The University Of California Multiprocessor system having statically determining resource allocation schedule at compile time and the using of static schedule with processor signals to control the execution time dynamically
JP3466212B2 (ja) * 1991-09-17 2003-11-10 インテル・コーポレーション コンピュータシステム
DE69323861T2 (de) * 1993-01-25 1999-10-07 Bull Hn Information Syst Multiprozessorsystem mit gemeinsamem Speicher
CA2115731C (en) * 1993-05-17 2000-01-25 Mikiel Loyal Larson Dynamically programmable bus arbiter with provisions for historical feedback and error detection and correction
EP0665501A1 (de) * 1994-01-28 1995-08-02 Compaq Computer Corporation Bus-Master-Arbitrierungsschaltung mit Wiederholungsmechanismus
US6026455A (en) * 1994-02-24 2000-02-15 Intel Corporation Architecture and method for providing guaranteed access for a retrying bus master to a data transfer bridge connecting two buses in a computer system
US5621897A (en) * 1995-04-13 1997-04-15 International Business Machines Corporation Method and apparatus for arbitrating for a bus to enable split transaction bus protocols
US5706446A (en) * 1995-05-18 1998-01-06 Unisys Corporation Arbitration system for bus requestors with deadlock prevention
US5664154A (en) * 1995-10-02 1997-09-02 Chromatic Research, Inc. M/A for optimizing retry time upon cache-miss by selecting a delay time according to whether the addressed location's dirty bit indicates a write-back
WO1997014103A1 (fr) * 1995-10-13 1997-04-17 Hitachi, Ltd. Systeme multiprocesseur
US5907862A (en) 1996-07-16 1999-05-25 Standard Microsystems Corp. Method and apparatus for the sharing of a memory device by multiple processors
DE69632634T2 (de) * 1996-12-13 2005-06-09 Bull S.A. Arbitrierungseinheit zum Multiprozessorsystembuszugriff mit Wiederholungsfähigkeit
US6062455A (en) * 1998-08-06 2000-05-16 Anthony C. Giannuzzi Cartridge strip magazine for powder-actuated fastener setting tool
US6289406B1 (en) * 1998-11-06 2001-09-11 Vlsi Technology, Inc. Optimizing the performance of asynchronous bus bridges with dynamic transactions
US6330630B1 (en) * 1999-03-12 2001-12-11 Intel Corporation Computer system having improved data transfer across a bus bridge
US6272580B1 (en) * 1999-03-16 2001-08-07 Compaq Computer Corp. Apparatus and method for dynamically elevating a lower level bus master to an upper level bus master within a multi-level arbitration system
US6401175B1 (en) * 1999-10-01 2002-06-04 Sun Microsystems, Inc. Shared write buffer for use by multiple processor units

Also Published As

Publication number Publication date
AU7622300A (en) 2001-05-10
US6704822B1 (en) 2004-03-09
EP1221095B1 (de) 2004-04-07
DE60009732D1 (de) 2004-05-13
WO2001025921A1 (en) 2001-04-12
EP1221095A1 (de) 2002-07-10
JP2003511755A (ja) 2003-03-25
JP4714396B2 (ja) 2011-06-29

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