DE50206838D1 - METHOD FOR SYNCHRONIZING A MEMORY WITH THE MAIN MEMORY OF A DATA SYSTEM - Google Patents
METHOD FOR SYNCHRONIZING A MEMORY WITH THE MAIN MEMORY OF A DATA SYSTEMInfo
- Publication number
- DE50206838D1 DE50206838D1 DE50206838T DE50206838T DE50206838D1 DE 50206838 D1 DE50206838 D1 DE 50206838D1 DE 50206838 T DE50206838 T DE 50206838T DE 50206838 T DE50206838 T DE 50206838T DE 50206838 D1 DE50206838 D1 DE 50206838D1
- Authority
- DE
- Germany
- Prior art keywords
- memory
- synchronizing
- data system
- main memory
- main
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/14—Protection against unauthorised use of memory or access to memory
- G06F12/1408—Protection against unauthorised use of memory or access to memory by using cryptography
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0804—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Security & Cryptography (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Storage Device Security (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE50206838T DE50206838D1 (en) | 2001-11-28 | 2002-10-31 | METHOD FOR SYNCHRONIZING A MEMORY WITH THE MAIN MEMORY OF A DATA SYSTEM |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10158393A DE10158393A1 (en) | 2001-11-28 | 2001-11-28 | Memory for the central unit of a computer system, computer system and method for synchronizing a memory with the main memory of a computer system |
DE50206838T DE50206838D1 (en) | 2001-11-28 | 2002-10-31 | METHOD FOR SYNCHRONIZING A MEMORY WITH THE MAIN MEMORY OF A DATA SYSTEM |
PCT/DE2002/004066 WO2003048943A2 (en) | 2001-11-28 | 2002-10-31 | Memory for the central unit of a computer, corresponding computer, and method for synchronising a memory with the main memory of a computer |
Publications (1)
Publication Number | Publication Date |
---|---|
DE50206838D1 true DE50206838D1 (en) | 2006-06-22 |
Family
ID=7707285
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE10158393A Withdrawn DE10158393A1 (en) | 2001-11-28 | 2001-11-28 | Memory for the central unit of a computer system, computer system and method for synchronizing a memory with the main memory of a computer system |
DE50206838T Expired - Lifetime DE50206838D1 (en) | 2001-11-28 | 2002-10-31 | METHOD FOR SYNCHRONIZING A MEMORY WITH THE MAIN MEMORY OF A DATA SYSTEM |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE10158393A Withdrawn DE10158393A1 (en) | 2001-11-28 | 2001-11-28 | Memory for the central unit of a computer system, computer system and method for synchronizing a memory with the main memory of a computer system |
Country Status (6)
Country | Link |
---|---|
US (1) | US7181576B2 (en) |
EP (1) | EP1449091B1 (en) |
JP (1) | JP4047281B2 (en) |
DE (2) | DE10158393A1 (en) |
TW (1) | TW200301856A (en) |
WO (1) | WO2003048943A2 (en) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7386676B2 (en) * | 2005-01-21 | 2008-06-10 | International Buiness Machines Coporation | Data coherence system |
US7533135B2 (en) * | 2005-07-01 | 2009-05-12 | Sap Aktiengesellschaft | Methods and systems for reducing database accesses in an object-oriented system |
US20070005552A1 (en) * | 2005-07-01 | 2007-01-04 | Udo Klein | Methods and systems for reducing transient memory consumption in an object-oriented system |
US7765398B2 (en) * | 2005-07-07 | 2010-07-27 | At&T Intellectual Property I, L.P. | Method of promulgating a transaction tool to a recipient |
JP2008293378A (en) * | 2007-05-25 | 2008-12-04 | Panasonic Corp | Program rewriting device |
US8443150B1 (en) * | 2008-11-04 | 2013-05-14 | Violin Memory Inc. | Efficient reloading of data into cache resource |
US7591019B1 (en) | 2009-04-01 | 2009-09-15 | Kaspersky Lab, Zao | Method and system for optimization of anti-virus scan |
JP5353828B2 (en) | 2010-06-14 | 2013-11-27 | 富士通セミコンダクター株式会社 | Processor and processor system |
US10360393B2 (en) * | 2017-04-28 | 2019-07-23 | International Business Machines Corporation | Synchronizing write operations |
US10915463B2 (en) | 2017-04-28 | 2021-02-09 | International Business Machines Corporation | Synchronizing requests to access computing resources |
Family Cites Families (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4319079A (en) * | 1979-09-13 | 1982-03-09 | Best Robert M | Crypto microprocessor using block cipher |
US4573119A (en) * | 1983-07-11 | 1986-02-25 | Westheimer Thomas O | Computer software protection system |
US4700330A (en) * | 1985-10-30 | 1987-10-13 | Digital Equipment Corporation | Memory for a digital data processing system including circuit for controlling refresh operations during power-up and power-down conditions |
US5045996A (en) * | 1986-11-12 | 1991-09-03 | Xerox Corporation | Multiprocessor cache memory housekeeping |
JPH01154261A (en) | 1987-12-11 | 1989-06-16 | Toshiba Corp | Information processor |
EP0325421B1 (en) * | 1988-01-20 | 1994-08-10 | Advanced Micro Devices, Inc. | Organization of an integrated cache unit for flexible usage in supporting multiprocessor operations |
EP0330425B1 (en) * | 1988-02-23 | 1995-12-06 | Digital Equipment Corporation | Symmetric multi-processing control arrangement |
GB8814077D0 (en) * | 1988-06-14 | 1988-07-20 | Int Computers Ltd | Data memory system |
US5081675A (en) * | 1989-11-13 | 1992-01-14 | Kitti Kittirutsunetorn | System for protection of software in memory against unauthorized use |
JPH03216744A (en) | 1990-01-22 | 1991-09-24 | Fujitsu Ltd | Built-in cache memory control system |
US5224166A (en) * | 1992-08-11 | 1993-06-29 | International Business Machines Corporation | System for seamless processing of encrypted and non-encrypted data and instructions |
US5481610A (en) * | 1994-02-28 | 1996-01-02 | Ericsson Inc. | Digital radio transceiver with encrypted key storage |
FR2728980B1 (en) * | 1994-12-30 | 1997-01-31 | Thomson Csf | SECURITY DEVICE FOR INFORMATION SYSTEMS ORGANIZED AROUND MICROPROCESSORS |
US6009498A (en) * | 1995-02-16 | 1999-12-28 | Fujitsu Limited | Disk control unit for holding track data in cache memory |
US5778427A (en) | 1995-07-07 | 1998-07-07 | Sun Microsystems, Inc. | Method and apparatus for selecting a way of a multi-way associative cache by storing waylets in a translation structure |
KR19980032776A (en) * | 1996-10-16 | 1998-07-25 | 가나이 츠토무 | Data processor and data processing system |
US6157999A (en) * | 1997-06-03 | 2000-12-05 | Motorola Inc. | Data processing system having a synchronizing link stack and method thereof |
WO1999028887A2 (en) * | 1997-12-01 | 1999-06-10 | Siemens Aktiengesellschaft | Method for reducing storage space requirements for a first electronic key and coding/decoding arrangement |
TW417048B (en) * | 1999-03-03 | 2001-01-01 | Via Tech Inc | Mapping method of distributed cache memory |
EP1118941B1 (en) * | 2000-01-18 | 2008-01-02 | Infineon Technologies AG | Microprocessor system and arrangement in order to operate a microprocessor system |
DE10101552A1 (en) * | 2001-01-15 | 2002-07-25 | Infineon Technologies Ag | Cache memory and addressing method |
US6745294B1 (en) * | 2001-06-08 | 2004-06-01 | Hewlett-Packard Development Company, L.P. | Multi-processor computer system with lock driven cache-flushing system |
-
2001
- 2001-11-28 DE DE10158393A patent/DE10158393A1/en not_active Withdrawn
-
2002
- 2002-10-31 JP JP2003550068A patent/JP4047281B2/en not_active Expired - Fee Related
- 2002-10-31 DE DE50206838T patent/DE50206838D1/en not_active Expired - Lifetime
- 2002-10-31 WO PCT/DE2002/004066 patent/WO2003048943A2/en active IP Right Grant
- 2002-10-31 EP EP02791592A patent/EP1449091B1/en not_active Expired - Lifetime
- 2002-11-11 TW TW091133021A patent/TW200301856A/en unknown
-
2004
- 2004-05-27 US US10/857,617 patent/US7181576B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP1449091A2 (en) | 2004-08-25 |
TW200301856A (en) | 2003-07-16 |
WO2003048943A2 (en) | 2003-06-12 |
US20050005071A1 (en) | 2005-01-06 |
US7181576B2 (en) | 2007-02-20 |
EP1449091B1 (en) | 2006-05-17 |
JP2005512192A (en) | 2005-04-28 |
DE10158393A1 (en) | 2003-06-12 |
WO2003048943A3 (en) | 2004-04-08 |
JP4047281B2 (en) | 2008-02-13 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |