DE4432725C1 - Forming three-dimensional components on surface of semiconductor chips etc. - Google Patents

Abstract

The invention concerns a method of producing a three-dimensional component or group of components, particularly on surfaces of already processed <u>semiconductor chips</u>. The production of three-dimensional features on chip surfaces is based on the stucturing of thick photosensitive resists and subsequent formation of the surface features by galvanic etching. Prior art methods merely use a thick photoresist and interposed galvanic starting layers to form three-dimensional features. The production of complex features is only possible with considerable difficulty owing to the low stability of the photoresist. The method proposed for the production of three-dimensional features uses, in addition to the galvanic etching of e.g. UV-structured photoresist layers with build-on metal films (16), etching using metal auxiliary films which are later removed again (sacrificial layers) (13). These metal auxiliary films lying in the resist layers are also used, in multi-layer features, as galvanic starting layers for additional build-on levels. The three-dimensional features which can be made by the method described enable, for example, e.g. coils and transformers to be manufactured, in a form in which they could not be manufactured previously, for integration on chip surfaces.

Description

The invention relates to a method for producing a three-dimensional Component or a group of components, especially on surfaces of already processed semiconductor chips.

Micromechanical or microelectronic components such as three dimensional micro coils or transformers directly on surfaces of to be able to manufacture fully processed electronic components besides further miniaturization of the overall structure, the production is also previously unrealizable systems while reducing costs in the Production.

By using the latest technologies in the manufacture of electronics accelerated ex expansion of this promising market. To keep up with technical progress The ability to implement computer technology is a rapid development automatic communication interfaces required. Use that for that Radio Frequency ID (RF-ID) systems work on a radio frequency basis and are increasingly turning into complex information systems with bidirectional lem data exchange. The basic structures of known RF-ID systems exist consisting of two hardware components, an information medium and one Base station, as well as two physical interfaces between the compo nenten. The data exchange takes place via a magnetic or electro  high frequency magnetic field. Frequencies around 125 kHz and a few MHz. Systems that work without internal energy supply work in the information carrier. these can run much smaller and also have a higher one Lifespan. These systems receive the necessary energy to function also over the radio frequency field. The data transmission takes place via ver different modulation methods. Passive systems stand out active through an extended temperature range. The one for their function necessary transmission energies are in the range of a few µW (up to 100 µW) for loosely coupled systems for longer ranges and more than 1 mW for systems with fixed coupling.

Of particular interest for the future development of these RF-ID systems is responsible for the design of the communication interface, d. H. the design the transmitting and receiving antennas. In the case of a channel-separated structure, there are several coordinated circles per interface necessary. The energy wins Information carrier about transformer decoupling, d. H. he owns as Receiving antenna a coil. The voltage transmission grows with it the transmission frequency and the maximum achievable resonant circuit quality. Since high power consumption lowers the quality, future systems have to have low energy consumption and the highest possible carrier frequencies. Modern CMOS technology creates the conditions for this.

The trend is towards increasing miniaturization and ultimately to a full integration of the information carrier a silicon chip, with all previously used assembly technologies become superfluous. However, there is a need in addition to those already capacities and Integrate coils. With integrated production, a 6 inch Si Wafer about 1000 RF-ID systems manufactured simultaneously and the piece price can be greatly reduced.

In known systems, the complete monolithic integration of the Information carrier thereby achieved that planar coils  Chip surfaces realized using conventional CMOS metallization will. Because the metallization is usually for electrical wiring The circuit elements on the chip can be used in the coils areas no active components can be accommodated. Another The disadvantage is the limited low impedance of the conductor tracks. With the usual specific material resistance results on a 4 mm chip at 50 Turns ohmic resistances of a few kΩ. This high resistance causes a poor quality of the input resonance circuit and leads to im Chip structure occurring parasitic capacitances to low-pass attenuation high carrier frequencies.

A process developed from the assembly and connection technology, which here Remedies, realizes the coil structure with other metals, above all Gold and copper. However, the coils are always in planar training and manufactured without inductor-improving coil cores (R. Jurisch, Elek tronik 9 (1993) 86-92).

Basis for well-known three-dimensional structures on chip surfaces forms the structuring of thick photoresists and the subsequent galvanic Impression of these lacquer structures. Simple structures based on this method have been produced, for. B. B. Lochel et al., Microelectr. Enginee ring 21 (1993) 463-466. In G. Engelmann et al., Proc. MEMS 92, Travemünde, (1992) 93-98, uses this process to make planar Coils used.

A method for producing free-standing microstructures is e.g. B. from DE 43 38 423 A1, in which dielectric sacrificial layers are known as Spacer layers between a substrate surface and the microstructure used and removed after completion of the structure.

From C.H. Ahn et a., J. Micromech. Microeng. 3 (1993) 37-44, is known to be a planar three-dimensional coil to manufacture with a core, wherein  the coil windings are arranged in two superimposed levels and are surrounded by the core material. The coil core increases the inductance of the Coil advantageously. The different levels of the coil structure are made by repeated application and structuring of thick photo paints and subsequent electroplating of these paint structures  generates a galva before the galvanic deposition of each level nikstart layer must be sputtered on.

• S. Kawahito et al., Sensors and Materials 5 (1994) 241-251, provides a method for the production of a three-dimensional coil with core on a silicon chip before, which has the disadvantage of a planar structure, i. H. especially the limited number of coil windings per surface element, eliminated. The coil axis runs parallel to the surface of the chip. When ver The core is driven by electrodeposition in a polyimide layer embedded, which serves the isolation from the coil windings. The Spu Oil windings are opened by means of sputtering and subsequent structuring the chip surface (lower coil area) or on the polyimide layer (upper and side coil areas).

The sputtering of the coil windings, however, causes only small structural heights hen the windings of 1-2 µm, so that the realizable qualities and usable amperages are correspondingly low and therefore the users limit the range of applications.

In B. Löchel et al., Microelectr. Engineering 23 (1994) 455-459, is a process Ren for the production of a three-dimensional coil on chip surfaces described, the basis of which is also the structuring of thick photoresists (10-60 µm Structure height) and the subsequent galvanic impression of this Lacquer structures forms. The different levels of the coil structure who the here by repeated application and structuring of the photoresists and galvanic impression is generated, with one prior to the deposition of each level Electroplating start layer must be sputtered on if it is not through a lower electroplating layer can be replaced.

Examples of an application of this method to the production of others Micromechanical components are described in B. Loechel et al., Proc. ACTUATOR 94, Bremen, (1994) 109-113, or in G. Engelmann et al., SPIE 2045 (1994) 306-313.  

However, the methods mentioned only use thick photoresist and intermediate electroplating layers for the formation of the three-dimensional nale superstructures. The construction of more complicated structures can only be increased possible effort.

This is due in particular to the fact that the usable paints are not sufficient are physically, chemically and thermally stable. So z. B. the paint in Vacuum, d. H. for example when sputtering an electroplating start layer brü chig or there are gas bubbles from escaping solvent, so that no flat surfaces over larger areas (mm area) for subsequent layer structures are more available. The sputtered gal Vanik star layer seals the underlying lacquer layers. On further off gas can lead to deformation and destruction of the overlying gal Vanik star layers come. Different coefficients of thermal expansion clients also support the formation of cracks in the overall structure. The too reliable production of complicated multilayer structures is therefore not possible Lich.

The problem is particularly caused by the need to apply new gal Vanik star layers for each component level on the underlying paint strata reinforced, which also leads to an increase in the number of procedures steps.

The object of the present invention is therefore to provide a method for the production of a three-dimensional component or a component group with which complicated structures in a simple and reliable way Chip surfaces can be integrated.

The object is achieved with the features of the method according to claim 1. Special features of the process are the subject of the sub claims.

The method according to the invention uses for the three-dimensional structures in addition to the galvanic impression of, for example, UV structured  Photoresist layers with build-up metal layers also take the impression metallic auxiliary layers to be removed later (sacrificial layers). These metallic auxiliary layers lying in the lacquer layers are used Multi-layer structures can also be used as electroplating start layers for others building levels used.

The procedure is for all microelectronic or micromechanical components le suitable, which have individual areas, which by galvanic Layer deposition can be produced, ie they are electrically conductive.

The three-dimensional components or component groups are in the fiction contemporary method on a surface, e.g. B. the surface of a chip, built up in layers. For the production of electrically conductive areas between those in the finished component there is a defined free (i.e. without solid matter) there should be a space, for example between two plates a capacitor or between two opposite walls Cooling channel, the first area is initially on the surface or on already applied layers or component areas are galvanically deposited. For this an electroplating start layer is necessary, which can be sputtered on beforehand. It is of course not necessary to apply the starting layer, if there is already an electrically conductive layer as a base. To this Electroplating start layer then becomes a structurable layer (e.g. photoresist) applied and structured according to the shape of the first area. The Structure must be part of the side or below depending on the component geometry Expose the adjacent electroplating start layer so that the desired shape of the first area by the subsequent galvanic deposition in the Structure can be created. The shape of the first area is determined by the Shape of the structure and the thickness of the deposited layer are determined.

Adjacent to the first area already applied, a metal is now The sacrificial layer is galvanically deposited, covering the space between the one already applied (first) and the one (s) to be applied (second) areas. So z. B. the distance between the two plates Capacitor determined by the thickness of the metallic sacrificial layer that is on  one of the plates is deposited. As an electroplating start layer for the deposition the metallic sacrificial layer is served by the already applied electrically conductive hige (first) area. The shape of the metallic sacrificial layer is also given that the deposition is structured accordingly Layer (e.g. photoresist, see above) takes place. On the metallic sacrificial layer finally the second area of the component is galvanically deposited, whereby again the shaping by means of a structurable layer analogous to The first area is deposited. Serves as a galvanic starting layer here, however, the metallic sacrificial layer, so that no additional galva nikstartschicht must be applied. For making more, this time Areas which are spaced apart from the second electrically conductive region can now be formed in in the same way another metallic sacrificial layer on the second layer applied and the process continued accordingly. By how Repeated application of the process steps shown is the production complex component structures.

The structurable layers and the metallic sacrificial layers are at the latest after completion of all areas of the component or the component Group selectively removed. When the process is complete, a component is thus ready available that has electrically conductive areas that are characterized by exact defined free spaces are spaced apart.

The procedure described here uses three-dimensional structures for example coils and transformers for integration on chip surfaces ready, which were previously not possible in this form. Allows thus completely new approaches due to an increased range of variations in inductance when executing information carriers.

An advantage of the method according to the invention is in particular that the metallic auxiliary layers that have the double function of a victim layer and an electroplating start layer have a very high stability sen, so that smooth stable surfaces are provided on which further levels can be built up without any problems.  

Electroplated layer surfaces (such as the surfaces of the metalli sacrificial layers) by varying the deposition parameters (Current strength, pulse duration, temperature) in their properties, such as roughness and reflectivity. This can be used to more even exposures of the photoresist with different thicknesses to achieve (claim 12). Heavily structured surfaces like those on the building electroplating process, have the consequence that paint thicknesses fluctuations in a plane to be exposed must be dealt with. The Reduction of reflection under thin layers of paint on rougher surfaces Chen leads to a lower exposure effect, whereas strongly reflect de smooth surfaces favor the exposure of thick layers of lacquer. This enables large differences in lacquer thickness to be equalized. The Roughness of the electroplating surfaces can also be caused by chemical intermediates actions such as immersion baths in acids. In addition to the change The reflectivity of the surfaces requires an increased roughness of a verb Removal of paint adhesion.

With the method can also be compared to the previously known Ver drive save process steps, since no additional electroplating start layers needed for each additional level.

Furthermore, with the method it is possible to set minimal distances between un different areas of the component or component group with high Ge to produce accuracy.

The method can advantageously be carried out directly on the processed chip surfaces that have previously been covered with a chemically resistant insulation layer hen were carried out (chip-on technology), and thus enables the Integration of electrical components such as B. coils, transformers or Kon capacitors without using bonding techniques.

For this purpose, contact holes are opened in the insulation layer of the chip the component with the components of the chip via these contact holes for example electrically via galvanically separated supply lines contacted (claim 3).

The method according to the invention is described below with reference to the embodiment examples and the drawings explained in more detail.

Show:

Fig. 1a-p is an example of the preparation of a three-dimensional coil having a core with the inventive method,

Fig. 2 is a side view of a manufactured with the inventive method three-dimensional coil with a core, integrated on a fully processed chip surface,

Fig. 3a-r an example of the production of a rectangular cylinder with piston according to the invention, and

Fig. 4a-b is an example of the use of Rauhigkeitsunterschieden electroplating on surfaces for adjusting the exposure action in very different coating thicknesses.

In a first embodiment, a three-dimensional coil is used a core integrated on a chip surface. Preparatory work for such on built on chips are necessary due to the stacked construction and the used materials conditionally. These preparations must be made at the Kon design of the microsystem and can be used for CMOS Manufacturing to be carried out. So z. B. a barrier layer between CMOS structure and overlying system structure are introduced, the the diffusion of harmful metal ions (e.g. gold) into the ones below prevent this chip. In addition, it is sufficiently thick (a few 100 nm to 1 µm), chemically sealed electrical insulation layer (e.g. silicon nitride layer) between the chip structure and the metallic layers above the components necessary.  

The three-dimensional coils or transformers according to the invention, such as them in the interfaces for contactless identification and communication systems that can be used are manufactured according to the following procedure posed:

• - The passivating and insulating protective layer on the chips 1 is opened at the electrical contact points to the chip (not shown in FIG. 1).
• - An electroplating start layer 2 , which is applied by sputtering and, depending on the structure of the chip, can consist of a layer of silicon nitride / gold, titanium / nickel or only platinum, is deposited over the entire surface of the chip surface ( Fig. 1a).
• - With a suitable method, e.g. B. in the centrifugal process, a layer of highly viscous, UV-structurable photoresist 3 is applied to the Galva nikstartschicht 2 and dried ( Fig. 1b). Depending on the photoresist used, the drying process must be carried out in such a way that the lacquer dries well, but no cracks occur when it cools down. After a possibly necessary paint aftertreatment (for Novolack systems, light-protected storage at room temperature and normal clean room climate for several hours to days), the first photoresist layer 3 is structured by exposure to a UV exposure unit and subsequent development using the dipping or spraying method ( Fig . 1c).
• - After drying at room temperature, the supply lines (not shown in FIG. 1) are formed to the open contact points and the lower coil level 5 by galvanic layer deposition in the lacquer structures 4 . The thickness of the lower lacquer layer 3 is determined by the desired thickness of the lower coil plane ( Fig. 1d).
• - The galvanized wafers are rinsed well and dried at room temperature. A further approximately 10 μm thick photoresist layer 6 is then applied to the lower layer ( FIG. 1e). It should be noted that the entire process is designed so that unintentional UV exposure (daylight, microscope) is excluded. This is followed by the exposure of a central region 7 along the axis of the coil to be produced over the entire coil length ( FIG. 1f). The lower coil windings 5 and between them the underlying electroplating start layer 2 are thus exposed in the exposed area. In this Lackstruktu ren 7 a less noble sacrificial metal 8 is deposited than that used for the coil structure ( Fig. 1g). Copper is a suitable sacrificial material for gold coils. B. Zinc. An additional electroplating layer is not necessary at this point.
• - After the first sacrificial metal deposition, the lacquer 3 , 6 is completely removed and a new 40-60 μm thick photoresist layer 9 is applied ( FIG. 1h). This is followed by a further lithography step 10 , which is likewise along the coil axis, but longer and narrower than the sacrificial layer, exposes the anchors for the coil core and defines the structure of the coil core itself ( FIG. 1i).
• - In the subsequent electroplating step, a NiFe alloy (permalloy) 11 of the desired thickness (for example 10-100 μm) is deposited in the now exposed areas ( FIG. 1j). This layer is outside the coil windings with the electroplating start layer 2 and thus connected to the chip 1 itself and inside the coil by the previously applied sacrificial layer 8 separated from the coil turns 5 underneath. After electroplating, cleaning and drying take place.
• In the next step, the same lacquer layer 9 is structured 12 in such a way that the side walls of the core 11 are exposed and the core is completely covered with a sacrificial layer 8 , 13 by a new galvanic molding (FIGS . 1j and 1k).
• - After complete stripping, a further lacquer layer 14 of appropriate thickness is applied in order to structure 15 the still missing top and side areas of the coils (bridges) ( FIG. 11).
• - The subsequent galvanic impression with 10-20 µm coil metal (gold, copper) forms the upper and the lateral coil areas 16 ( Fig. 1m).
• - In the next step, the entire paint structure 9 is removed with solvents (acetone) ( Fig. 1n).
• - Then the entire sacrificial layer 8 , 13 is removed with a suitable selective etchant which does not attack the chip structure, for example ammonia with a small addition of hydrogen peroxide in the case of copper as the sacrificial layer material and a gold coil with Ni / Fe core ( FIG. 10).
• - In order to be able to operate the coil functionally, the metal parts of the electroplating start layer 2 in the entire wafer area must finally be removed ( FIG. 1p). Since this must also take place between the windings, only a wet chemical etching step is again possible. For a silicon nitride / gold starting layer, this can be done by etching with suitable etching solutions (e.g. KJ / J) without noticeable thickness losses in the gold windings 5 , 16 or in the NiFe core 11 must be accepted.
• - After a final cleaning, the surface coil 17 is functionally contacted to the chip 1 and ready for use.

A side view of a three-dimensional coil with core 17 integrated in this way on a chip surface with CMOS components 1 is shown in FIG. 2.

In a second embodiment, a rectangular cylinder with a Piston on a wafer surface with the following process steps represents:

• - On the surface of the wafer 18 , a nickel layer 19 is applied as a galvanic nikstartschicht ( Fig. 3a). With a suitable method, e.g. B. in the centrifugal process, an approximately 50-60 microns high layer of UV-structurable photoresist 20 (z. B. highly viscous novolac) is applied to the Galvanikstartschicht 19 and dried. After any necessary post-treatment of the lacquer (for Novolack systems, light-protected storage at room temperature and normal clean room climate for several hours to days), the first photoresist layer is structured according to the shape of the bulb (bulb width and bulb length) by exposure to a UV exposure unit and subsequent development in the Dip or spray process ( Fig. 3b). A metallic auxiliary layer 22 (here: copper) is first electroplated into the structure 21 thus formed up to a defined height ( FIG. 3c; in plan view: FIG. 3d). The height of the auxiliary layer 22 defines the distance between the piston and the wafer surface.
• - The piston material 23 (here: Fe / Ni alloy) is then galvanized to a thickness of approximately 40 μm over the auxiliary layer 22 in the same lacquer structure 21 ( FIG. 3e).
• - The paint 20 is completely removed. A new, approximately 60 μm thick photoresist layer 24 is then applied. This is followed by a further lithography step, which exposes an area 25 which is longer and wider than the piston 23 (cf. FIG. 3f; in plan view: FIG. 3g).
• In the subsequent electroplating step, a further metallic auxiliary layer 26 is deposited on the piston 23 and in the exposed areas between the piston 23 and the photoresist 24 in a thickness which defines the distance between the piston 23 and the cylinder wall. After this step, the piston is completely (about 5-10 μm thick) coated with sacrificial metal 22 , 26 (auxiliary metal layer) ( FIG. 3h; in plan view: FIG. 3i).
• - The complete removal of the lacquer 24 follows, after which a new approximately 60 μm thick photoresist layer 27 is applied. This is followed by a further lithography step, which exposes an area 28 which is wider than the previous structure 25 , but shorter than the piston 23 , so that it is covered on one side by the lacquer 27 (cf. FIG. 3j; in plan view FIG . 3k).
• - In the subsequent electroplating step, a NiFe alloy (permalloy) is deposited in the desired thickness of the cylinder walls 29 in the now exposed areas 28 ( Fig. 3l; in plan view Fig. 3m).
• - In the next step, the entire paint structure 27 is removed with solvents (acetone) ( Fig. 3n; in plan view Fig. 3o)).
• - The entire metallic sacrificial layer 22 , 26 is then removed with a suitable selective etchant. The result is shown in FIG. 3p in cross section, 3q in side view and 3r in top view. The lower cylinder wall is formed by the wafer 18 with the electroplating start layer 19 .

Since the sacrificial metal 22 , 26 defines the distance between the piston 23 and the cylinder wall 29 , distances of a few micrometers can be achieved.

For the movement of the piston, for example, from the back of the Wafers etched holes in the bottom wall of the cylinder and then the piston be moved with pressure. Forming the piston assembly so that two the cylinder described can be realized, the piston can be pneumatic moved and the mechanical force can be used in microsystems.

An example of the use of roughness differences on electroplating surfaces to adjust the exposure effect in paints with strongly under different paint thicknesses is shown schematically in FIGS . 4a and 4b.

FIG. 4a shows galvanic structures 30 with different structure heights, was applied to a photoresist layer 31. To produce a lacquer structure, as shown in FIG. 4b, a smooth surface 32 of the low electroplating structure and a rough surface 33 (particularly emphasized in FIG. 4b) of the high electroplating structure are used in the exposure of the photoresist layer 31 . The reduction in the reflection on the rough surface 33 leads to a lower exposure effect of the thin lacquer layer lying on top, whereas the highly reflective smooth surfaces 32 promote the exposure of the thick lacquer layer above. Since the exposure dose is matched to the different coating thicknesses. The different roughnesses can be generated during the galvanic deposition by varying the deposition parameters (current strength, pulse duration, temperature) or after the deposition by chemical intermediate treatments, such as immersion baths in acids.

The exemplary embodiments presented naturally only show one Small section from the multitude of methods using the method according to the invention producible components. The process is for making many more microelectronic (e.g. capacitors) and / or micromechanical (e.g. Cooling channels, waveguides, gears on axes, etc.) components with each other spaced areas applicable.

It also enables multi-level wiring to be implemented in one level, whereby crossings of conductor tracks are prevented by that at these points air bridges the wiring levels against each other isolate.

The entire microsystem created from the components can be used if required encapsulated in plastic after completion and thus mechanically and electrically stabilized and largely removed from environmental influences be.

Claims (14)

1. A method for producing a three-dimensional component or a component group, in which electrically conductive areas ( 5 , 11 , 16 ) of the component ( 17 ) or the component group are applied to a surface ( 1 ) by galvanic layer deposition, with structurable layers ( 3 , 6 , 9 , 14 ) are deposited and structured, the structures ( 4 , 10 , 15 ) of which at least partially determine the shapes of regions of the component or the component group, the galvanic deposition takes place in these structures, and the structurable layers at the latest after completion of all Areas of the component or group of components are selectively removed, characterized in that prior to the galvanic deposition of electrically conductive areas ( 11 , 16 ) of the component or group of components to be applied, those of an already applied electrically conductive area ( 5 , 11 ) by a free Gap are spaced, e Ine metallic sacrificial layer ( 8 , 13 ) is galvanically deposited adjacent to the already applied Be, which defines the space between the already applied and the areas to be applied and serves as a galvanic starting layer for the deposition of the areas to be applied, the metallic sacrificial layer at the latest after Completion of all areas of the component or the component group is selectively removed. 2. The method according to claim 1, characterized in that a base metal is used for the metallic sacrificial layer ( 8 , 13 ) than for the electrically conductive regions ( 5 , 16 ) of the component. 3. The method according to any one of claims 1 or 2, characterized in that the surface ( 1 ) is the passivated surface of a chip which already contains processed components, with contact holes being opened to the components of the chip and the component via these contact holes the components of the chip are electrically contacted by conductor tracks applied to the chip. 4. A method for producing a three-dimensional coil ( 17 ) having a lower coil area ( 5 ), lateral coil area ( 16 ), an upper coil area ( 16 ) and a core ( 11 ) as electrically conductive areas, characterized in that the following process steps are carried out:

• - Applying an electroplating start layer ( 2 ) to the surface ( 1 );
• - Applying a first structurable layer ( 3 ) to the electroplating layer;
• - Structuring the first structurable layer in accordance with the shape of the lower coil region such that an interface of the structure is formed by the electroplating start layer ( 2 );
• - Galvanic deposition of the lower coil region ( 5 ) into the structure of the first structurable layer ( 3 );
• - Applying a second structurable layer ( 6 ) to the lower coil area;
• - Structuring the second structurable layer in a central region along the coil axis such that the structure between the inter mediate space between the lower coil area and the core, and an interface of the structure is at least partially formed by the adjacent lower coil area ( 5 );
• - Galvanic deposition of the metallic sacrificial layer ( 8 ) into the structure of the second structurable layer ( 6 );
• - Application of a third structurable layer ( 9 ) adjacent to the metallic sacrificial layer ( 8 );
• - Structuring the third structurable layer in such a way that the structure at least partially defines the shape of the core, and an interface of the structure is formed by the adjacent metallic sacrificial layer ( 8 );
• - Galvanic deposition of the core ( 11 ) in the structure of the third structurable layer ( 9 );
• Further structuring of the third structurable layer ( 9 ) such that the structure defines the space between the core and the lateral coil regions and between the core and the upper coil region, and an interface of the structure is formed by the adjacent core;
• - Galvanic deposition of the metallic sacrificial layer ( 13 ) into the structure, so that the core ( 11 ) is completely covered by metallic sacrificial layers ( 8 , 13 ) perpendicular to the coil axis;
• - Applying a fourth structurable layer ( 14 ) adjacent to the metallic sacrificial layer ( 13 );
• - Structuring the fourth and underlying structurable layers such that the shape of the lateral coil regions and the upper coil region ( 16 ) is at least partially defined by the structure, and an interface of the structure is formed by the adjacent metallic sacrificial layer ( 13 );
• - Galvanic deposition of the lateral and upper coil area ( 16 ) in the structure of the fourth and underlying structurable layers;
• - Selective removal of the structurable layers ( 3 , 6 , 9 , 14 );
• - Selective removal of the metallic sacrificial layers ( 8, 13 );
• - Selective removal of the electroplating start layer ( 2 ) at the exposed locations.

5. The method according to claim 4, characterized in that after the application of the metallic sacrificial layer ( 8 ), which is arranged between the lower coil region ( 5 ) and core ( 11 ), the first ( 3 ) and the second structurable layer ( 6 ) removed becomes. 6. The method according to any one of claims 4 or 5, characterized in that as materials for the upper ( 16 ), lower ( 5 ) and the lateral coil regions ( 16 ) gold or copper, for the core ( 11 ) a Ni / Fe Alloy and copper or zinc can be used for the metallic sacrificial layer ( 8 , 13 ). 7. The method according to any one of claims 4 to 6, characterized in that one layer of silicon nitride / gold or titanium / nickel or platinum is applied for the electroplating start layer ( 2 ). 8. The method according to any one of claims 4 to 7, characterized in that the thickness of the individual structurable layers ( 3 , 6 , 9, 14 ) is selected between 10 and 100 microns. 9. A method for producing a rectangular cylinder with a piston, which has the cylinder walls ( 29 ) and the piston ( 23 ) as electrically conductive regions, characterized in that the following method steps are carried out:

• - Applying an electroplating layer ( 19 ) to the surface ( 18 );
• - Applying a structurable layer ( 20 ) to the electroplating start layer ( 19 );
• - Structuring the structurable layer according to the shape of the piston such that an interface of the structure is formed by the galvanic nikstarttschicht;
• - Galvanic deposition of a metallic sacrificial layer ( 22 ) in the structure of the structurable layer ( 20 ), so that the sacrificial layer defines the distance between the piston ( 23 ) and the surface ( 18 )
• - Galvanic deposition of the piston ( 23 ) on the metallic sacrificial layer ( 22 ) in the structure of the structurable layer ( 20 );
• - Structuring the structurable layer ( 20 ) such that the structure of the piston and a region of the electroplating start layer ( 19 ) around the piston are exposed;
• - Galvanic deposition of the metallic sacrificial layer ( 26 ) in the structure, so that the piston is completely encased by metallic sacrificial layers ( 22 , 26 ) which define the distance to the cylinder walls ( 29 );
• - Removing the structurable layer ( 20 , 24 );
• - Application of a further structurable layer ( 27 ) to the electroplating layer and the sacrificial layer;
• - Structuring the further structurable layer ( 27 ) such that part of the sacrificial layer around the piston and a region of the electroplating start layer around the piston are exposed through the structure;
• - Galvanic deposition of the cylinder walls ( 29 ) into the structure of the further structurable layer ( 27 );
• - Removing the further structurable layer ( 27 );
• - Selective removal of the metallic sacrificial layers ( 22 , 26 );
• - Selective removal of the electroplating start layer ( 19 ) at the exposed locations.

10. The method according to claim 9, characterized in that after the deposition of the piston ( 23 ), the structurable layer ( 20 ) is removed and a new structurable layer ( 24 ) is applied. 11. The method according to any one of claims 1 to 3, characterized, that as structurable layers UV-structurable photoresist layers used and this by means of UV radiation and subsequent development be structured in the immersion or spray process. 12. The method according to any one of claims 1-3, characterized, that by suitable choice of the deposition parameters in the electroplating or by post-treatment, roughness differences on the galvanic deposited layers are generated, which are the approximation of the Exposure dose of overlying lacquer layers with different Allow paint thicknesses. 13. The method according to any one of claims 1-3, characterized, that the photoresist is removed with a solvent. 14. The method according to any one of claims 1 to 3, characterized, that the metallic sacrificial layer with a selective etchant that the Chip assembly does not attack, is removed.