DE4427042A1 - Method for controlling a sequence of accesses by a processor to an associated memory - Google Patents

Description

The processing power of microprocessor systems, esp especially in communication systems, depends on the one hand on the internal processing speed of the processor and others connected by the speed of access to one read memory, especially working memory. Because the current microprocessor systems, for example 486 DX from Intel, very high, internal processing speeds point, the processing power of the microprocessors in the essentially through the access times to the connected Memory limited. For the design of work store for microprocessors especially in communication systems, d. H. Telecommunications switching systems, so far dynamic RAM memory chips (DRAM) used, which a relatively small external cache memory is connected upstream. In A cache memory is the most common depending on the strategy or most recently used memory addresses and / or data saved. Such memory concepts are for Per sonalcomputer applications advantageous and achieve an ak acceptable processing performance; a memory concept tion with properties described below for communication However, cation systems cannot be achieved.

A working memory for a communication system, in particular Another communication system should have the following properties exhibit:

• - The main memory for time-critical, switching technology Programs and data are in the range of a few MByte up to 50 Mbytes;  
• - The mediation-related programs or sub-programs are played out with almost the same probability leads;
• - The program has frequent interruptions, i. H. lan More sequential program parts occur in reduced order catch;
• - The number of data access cycles is in relation to Program access cycles very high;
• - Access to data is usually statistically independent gig and find with equal probability on all be rich memory instead;
• - Most of the time, a sequence of accesses has a few dependent access cycles on - e.g. B. three to eight.

In microprocessor systems with the known cache memories are in the majority of access cycles to the Memory wait cycles required to pass through the access time is not too low step, within the framework of an access cycle in the microprocess system are formed. This means a significant re reduction of processing power, especially of modern times microprocessor systems, their internal processing areas increasing speed.

The invention is therefore based on the object of a method to control a sequence of accesses by a processor an assigned working memory taking into account ei ner particularly advantageous storage concept for communica tion systems such that the processing line especially when accessing the RAM is increased. The task is characterized by the features of the patent spell 1 solved.  

The method according to the invention is based on a division the memory to which the microprocessor has the shortest access grip times should access, in at least two by stati partial memory implemented. With a pre given sequence of accesses - e.g. B. four accesses the first time one of the partial memories is accessed Memory address to the addressed partial memory and for the other partial stores starting from the first store the memory sequence addresses are immediately formed and sent to the partial stores - with two partial stores at the other - controlled. The first and subsequent accesses will Date present at the addressed partial memory sen or saved and according to the specified Se sequence of accesses, one memory sequence address each formed that the partial memory successively cyclically, d. H. at two partial memories alternately, before the actual access of the processor and according to the status each have a date from the respective partial file read or stored in memory or in the memory cher is written. The read or to be saved Data is clocked with the help of a buffer according to and processor cycle according from memory to the processor or transferred from the processor to the memory.

The number of partial memories is advantageous Embodiment of the invention depending on the difference limit amount (n-m) of the number n of processor clocks of an im Memory (SP) running read or write cycle and the Number m of processor clocks one via the processor bus (B) controlled access cycle to memory determined - On saying 2. In a number of applications, one open is sufficient division of the memory into two partial memories in order to achieve the through the processor controlled maximum access speed to reach the partial stores. Here, with a Se quenz with four accesses the partial memories with the help of Address bits of value 2² and 2³ before the access of the Processor, d. H. in the case of two partial stores, each before  outgoing access, alternately addressed. For the formation of the Sequence addresses are created based on the first memory the address bits with the value 2² and 2³ - Claim 5. The formation of the memory sequence addresses with the help of the address bits with the valency 2² and 2³ allows the control logic to be implemented economically. The memory sequence addresses are also in the control logic to form according to processor clock and memory access cycle to control according to the memory. Current microprocessors perform an access cycle to memory minimally in one or in two processor cycles, with the first to handle cycle of a sequence in the control logic the number the processor clocks matched to the memory access time is and for the further accesses of a sequence processor moderate access cycles are provided - claim 6. In the An Control logic is for a processor clock and access cycle appropriate control of access to the memory processor clocked buffers and logic circuits provided.

When the processor accesses the memory with a memory The successor address is the one in the control logic formed memory sequence address of a sequence to match mung checked. If they match, the sequence from Zu continued and if there is a mismatch, the Sequence of accesses ended - claim 7. In Ansteuerlo gik the sequence of accesses is ended by no additional partial memory is addressed and consequently no data ten more are transferred to the buffer. Of the The processor represents this termination due to the lack of data with the planned following access cycles fixed and ini tializes corresponding error messages or troubleshooting measures. Also a repetition of a sequence from Zu handles can be provided.

A partial memory by means of a stati is particularly advantageous Read / write memory implemented - Claim 9. Stati Read / write memories have shorter access times  compared to dynamic read / write memories, which means a division of the memory into a few partial memories or Memory banks processor-appropriate, short memory access cycles can be reached.

Further advantageous embodiments of the invention are the further claims.

In the following the method according to the invention and a he arrangement according to the invention using two block diagrams and a flowchart explained in more detail. Show

Fig. 1, the processor and memory design nikationssystem in a Kommu,

Fig. 2 shows the structure of the control logic and

Fig. 3 with the help of a flowchart, the function of the control logic.

Fig. 1 shows a processor and memory design uses a block diagram of a communications system KS, in particular sondere a telecommunication exchange in which the dung OF INVENTION modern method is realized. A microprocessor or a microprocessor system MP is connected to a control logic ALS via a processor bus B formed by address / data and status lines, the part of the processor bus B transmitting the data d being transmitted by lines and the part of the processor bus B transmitting the address information ai is indicated by dashed lines. The processor bus B has, for example, a bus width of 32 bits and a processor clock speed of 33 MHz. A microprocessor system MP with such bus properties is, for example, the microprocessor system 486 DX from Intel. The outputs A of the control logic representing the processor bus B are connected to two static partial memories SRAM 0, 1, in which, for example, the switching technology program one Telecommunications switching system is stored. A control device ALD for dynamic memories DRAM is also connected to processor bus B. With the help of this commercially available control device ALD, the writing and reading of data to or from a dynamic memory DRAM is controlled. The static partial memory SRAM 0, 1 and the dynamic memory DRAM together form the working memory SP of the microprocessor system MP, those static programs d or data d being stored in the static partial memory SRAM 0, 1, for which very short access times are provided . In the dynamic memory DRAM, data d with longer access times in particular are stored in telecommunications switching systems. When accessing the dynamic memory DRAM, waiting information is formed in the microprocessor MP, with the aid of which access is delayed, since access to the dynamic memory DRAM is not possible within the shortest access time by the microprocessor MP is. Since the method according to the invention is based on the static partial memory SRAM 0, 1, access to the dynamic memory DRAM is not explained in more detail below.

The two static partial memories SRAM 0, 1 are by two static memory banks SRAM 0, 1 formed, each of the Static partial memory SRAM 0, 1 separately via processor bus is controlled according to realized inputs E. About an in the control logic AS contained buffer ZSP, the both with the static partial memories SRAM 0, 1 and with is connected to the dynamic memory DRAM, the in read the memories SRAM 0, 1, DRAM or ge of these Read commands d or data d cached. The two Schenschpeicher ZSP is advantageous due to a four-way intermediate memory (4-way bus exchange buffer) implemented processor-controlled for both static parts SRAM 0, 1 and the dynamic memory DRAM as well Microprocessor MP causes the temporary storage. This two Storage is especially important for the processor clock  right handing of commands d or data d to the memory cher DRAM, SRAM 0, 1 required.

Furthermore, the control logic ALS shown in detail in FIG. 2 contains a clock and logic circuit TLS. In the clock and logic circuit TLS, the processor bus B is routed to an address buffer ASP, an address controller AST and a buffer controller ZSPS. In the intermediate address memory ASP, the address information given by the microprocessor MP, represented by binary information ai4. . . n of the address lines 4 to n, temporarily stored in the execution example 4 to 31 and together with the address information ai2, 3 formed in the address control AST, the second and third address lines ADL 2, 3 memory-accessible or processor clock-oriented to the two static partial memories SRAM 0, 1 laid. Here, address information ai2, 3 is formed in the address control AST for each partial memory or each memory bank DRAM 0, 1 and separately via the address lines ADL 2, 3 to the two partial memories SRAM 0, 1. The address information ai of the address lines ADL 2 to n together form the memory address with which the partial memory SRAM 0, 1 and a memory location in the respective partial memory SRAM 0, 1 is addressed in the sense of reading or writing a date. For signal regeneration and transmission via the address lines ADL 0 arranged after the clock and logic circuit TLS. . . 31, a line driver circuit T is inserted into each of these.

Furthermore, a buffer control ZSPS is provided in the clock and logic circuit TLS, with the aid of which the data or commands are written to the static partial memories SRAM 0, 1 in accordance with the processor clock or read from the static partial memories SRAM 0, 1. For this purpose, the intermediate storage control ZSPS is connected to the intermediate storage ZSP via a control line SL. The function or the. Operation of the clock and logic circuit TLS is explained in more detail below using the flow diagram shown in FIG. 3.

In the flowchart shown in FIG. 3, a sequence Q of four memory accesses or accesses Z is used. The status information sti transmitted by the microprocessor MP via the processor bus B communicates the partial memories SRAM 0, 1 and the buffer memory ZSP Whether in the four memory accesses Z of a sequence Q data d or commands d are to be written into the partial memories SRAM 0, 1, ie to be stored or data d or commands d are read from the partial memories SRAM 0, 1 - not shown in FIG. 3 poses. For the four memory accesses Z, the three memory sequence addresses sfa1. . . 3, based on the address information ai of the first memory address sa1 of the first access Z according to an algorithm predefined both for the microprocessor MP and for the clock and logic circuit TLS. In the exemplary embodiment, starting from the logical information of the address bit with the value 2² of the first memory address sa1, the first memory sequence address sfa1 with the complementary logical information of the address bit with the value 2² is formed. The second memory sequence address sfa2 is formed with the address bit of significance 2² of the first memory address sa1 and with the complementary logical information of the address bit of significance 2³. At the third memory sequence address sfa3, the complementary logical information of the address bits with the value 2 2 and the value 2 3 of the first memory address is used.

At the beginning of a sequence Q, it is checked whether a static partial memory SRAM 0, 1 is addressed and whether a sequence Q is possible. After these checks, a sequence Q of four memory accesses or accesses Z is started and, starting from the first memory address sa1, the memory success addresses sfa1. . . 3 in accordance with FIG. 3, wherein in the control logic ALS, after recognizing the first memory address sa1, the first memory address sa1 is controlled or placed on the addressed partial memory SRAM 0, 1 and approximately the same time the first memory sequence address sfa1 is formed and the other, not partial memory SRAM 0, 1 addressed or controlled by the first memory address sfa1. It should be noted here that the partial address of the first memory address sa1 addressing a memory location within a partial memory SRAM 0, 1 remains unchanged. After the first memory address sa1 or the first memory sequence addresses sfa1 have been applied to the two partial memories (SRAM 0, 1, reading or writing a date d in both partial memories SRAM 0, 1 is carried out in accordance with the status information - for example reading data d from the memory SP The first access to the memory SP or to a partial memory SRAM 0, 1 takes place at the memory access speed, ie the processor MP has to delay the access cycle, for example by inserting waiting cycles - known in the art as "wait-state" cycles During the first memory access, the data d read in the example is transferred to the buffer memory ZSP and transferred to the processor MP and then the second memory sequence address sfa2 is formed and sent to the address lines ADL 2... n via the address lines ADL 2.. first memory address sa1 addressed partial memory SRAM 0, 1 controlled or set and made to measure Reading or writing a date d is initiated in the status information. The control logic ASL then controls the partial memory SRAM 0, 1 addressed by the first memory sequence address sfa1 - with the aid of the first memory sequence address sfa1 - and the data d read, for example, is transferred to the buffer memory ZSP and transferred to the processor MP in accordance with the process cycle and the process cycle and the third memory sequence address sfa3 is formed, controlled or applied to the respective partial memory SRAM 0, 1 and reading or writing of a date d is initiated in accordance with the status information sti.

Subsequently, the data d, for example read in the partial memory SRAM 0, 1 addressed by the second and third memory sequence address sfa 2, 3, is transferred according to the processor clock and access cycle via the intermediate memory ZSP to the processor MP. The two similar partial sequences shown in FIG. 3 result as a function of the partial memory addressed in the first memory address sa1 (SRAM 0, 1).

Through the successive cyclical distribution of the memory access fe Z on the two partial memories SRAM 0, 1 - even with more than two partial memories SRAM 0, 1 - are Z after the first access on the memory SP processor-appropriate memory access speeds attainable, d. H. the accesses are with the in Microprocessor MP possible speed - e.g. B. within of a processor clock - feasible, although the memory grip time of the static partial memory SRAM 0, 1 essential lies above the usual one of the microprocessor MP. Before everyone first access Z following access Z of the processor to the Memory SP or a partial memory SRAM 0, 1 is in the Clock and logic circuit TLS formed memory sequence address sfa1. . . 3 with the memory film formed in the microprocessor MP address sfa1. . . 3 compared and if there is agreement, the Sequence Q of accesses Z continued. If there is no over Sequence Q ends in tune.

The method according to the invention according to FIG. 3 can be implemented both per gram and in terms of circuitry, with circuitry implementation being preferred in the currently available microprocessors MP with high processing speeds. It should be noted here that the formation of the memory sequence addresses sfa1. . . 3 and the alternating control of the partial memory SRAM 0, 1 is carried out in accordance with the microprocessor clock. An arrangement for carrying out the method according to the invention is consequently to be provided with a clock component to be coordinated with the processor speed and the number of processor clocks per access. These are, in particular, processor clock-controlled takeover registers or logic logic elements. A detailed description of a circuit design variant appears to be superfluous, since a variety of training courses are possible depending on the intended implementation using commercially available, user-programmable or customer-specific circuits.

Claims (13)

1. Method for controlling a predetermined sequence (Q) of accesses (Z) of a processor (MP) via a processor bus (B) to an associated memory (SP) formed by individually addressable partial memories (SRAM 0, 1), in which the Data (d) are each transferred via an access cycle-controlled data buffer (ZSP) from or to the processor (MP) and an access cycle (Z) controlled via the processor bus (B) to the memory (SP) m processor clocks as well as one in the memory (SP) running read or write cycle comprises n processor clocks, n being greater than m,

• - In which a sequence (Q) of accesses (Z) is initiated by at least a first memory address (sa1) formed by the processor and by reading or writing data (d) from or into the memory (SP) indicating status information (sti) becomes,
• - With the control logic (ASL) inserted between the processor (MP) and the partial memories (SRAM 0, 1)
• - After the presence of a first memory address (sa1), this is controlled to the addressed partial memory (SRAM 0, 1) and a memory sequence address (sfa1) is formed for each of the additional partial memories (SRAM 0, 1) in accordance with the specified sequence (Q) and each on the further partial memory (SRAM 0, 1) is controlled, whereby a read or write cycle is initiated in all partial memories (SRAM 0, 1) in accordance with the status information (sti), and
• - Starting from the partial memory (SRAM 0, 1) addressed by the first memory address (sa1), the partial memories (SRAM 0, 1) are cyclically controlled successively and according to the access cycle according to the sequence (Q), with one control
• - In accordance with the status information (sti), a date (d) present on the controlled partial memory (SRAM 0, 1) is transferred to the intermediate memory (ZSP) according to the processor clock and is controlled according to the processor cycle to the processor (MP) or one of the Processor (MP) is stored in the respective processor clock-controlled buffer (ZSP) via the mean data (d) and is led to the addressed partial memory (SRAM 0, 1), and,
• - if provided in accordance with the sequence (Q) of accesses (Z), the current memory address (sa1, sfa1, 2) changed, led to the controlled partial memory (SRAM 0, 1) and an access in accordance with the status information (sti) ( Z) is initiated on the respective partial memory (SRAM 0, 1).

2. The method according to claim 1, characterized, that the number of partial memories (SRAM 0, 1) is dependent from the difference amount (n-m) of the number n of processors clocks of a read or write running in the memory (SP) cycle and the number m of processor clocks one over the Processor bus (B) controlled access cycle (Z) on the memory cher (SP) is determined. 3. The method according to any one of claims 1 or 2, characterized, that the first memory address (sa1) by one, one of the Part memory (SRAM 0, 1) addressing memory address be is true. 4. The method according to any one of the preceding claims, characterized in that after the first, several address bits with the value 2 ^x comprehensive memory address (sa1) in the control logic (ASL) for the successive cyclic addressing of the partial memory (SRAM 0, 1) provided Memory sequence addresses (sfa1... 3) according to the given sequence (Q) of accesses (Z) to the address bits address information (ai) representing logical information (0, 1) are assigned in such a way that the partial memories (SRAM 0, 1) are successively assigned are addressed cyclically. 5. The method according to claim 4, characterized in that with two partial memories (SRAM 0, 1) and a sequence (Q) of four access cycles (Z) with a processor bus width of 32 bits for a successive cyclic addressing of the partial memory (SRAM 0, 1) starting from the address information (ai) representing logical information (0, 1) of the address bits of the first memory address (sa1) with the valency 2 2 and 2 3 three memory sequence addresses (sfa1... 3) are formed, whereby

• - the first memory sequence address (sfa1) with the complementary logical information (0, 1) of the address bit with the value 2 2,
• - The second memory sequence address (sfa2) with the complementary logical information (0, 1) of the address bit with the value 2³, and
• - The third memory sequence address (sfa3) each with the complementary logical information (0, 1) of the address bits with the value 2² and 2³

is formed. 6. The method according to any one of the preceding claims, characterized, that a processor access cycle (Z) within two or three processor clocks is performed, with the first access cycle (Z) of a sequence (Q) the number of Processor clocks depend on the access time to the memory (SP) is correct and for the further access cycles (Z) of a Se quenz (Q) processor-specific access cycles (Z) are provided. 7. The method according to any one of the preceding claims, characterized, that in the control logic (ASL) after a check on Agreement in the processor (MP) and in the control loop gik (ASL) formed memory sequence addresses (sfa1... 3) Match the sequence (Q) of accesses (Z)  leads and in case of mismatch the sequence (Q) of Zu handles (Z) is ended. 8. Arrangement for controlling a predetermined sequence (Q) of accesses (Z) of a processor (MP) via a processor bus (B) to an associated memory (SP) formed by individually addressable partial memories (SRAM 0, 1), in which the Data (d) can be transferred from or to the processor (MP) via an access cycle-controlled intermediate memory (ZSP) and an access cycle (Z) controlled via the processor bus (B) to the memory (SP) in processor cycles as well as one in memory (SP) ongoing read or write cycle comprises n processor clock cycles, n being greater than m and a sequence of accesses by at least one first memory address (sa1) formed by the processor and by reading or writing data from or into the memory (SP) indicating status information (sti) is initiated,

• - In which one between the processor (MP) and the part store (SRAM 0, 1) inserted control logic (ASL) is designed such that
• - After a first memory address (sa1) is present, it is controlled to the addressed partial memory (SRAM 0, 1) and a memory sequence address (sfa1) is formed for each of the additional partial memories (SRAM 0, 1) in accordance with the specified sequence (Q) and each is switched on the further partial memory (SRAM 0, 1) is controlled, whereby a read or write cycle is initiated in all partial memories (SRAM 0, 1) in accordance with the status information (sti), and
• - Starting from the partial memory (SRAM 0, 1) addressed by the first memory address (sa1), the partial memories (SRAM 0, 1) are cyclically controlled successively and according to the access cycle according to the sequence (Q), with one control
• - In accordance with the status information (sti), a date (d) present on the controlled partial memory (SRAM 0, 1) is transferred to the buffer memory (ZSP) according to the processor clock and is controlled according to the processor cycle to the processor (MP) or one of the Processor (MP) is stored in the respective processor clock-controlled buffer (ZSP) via the average date (d) and is led to the addressed partial memory (SRAM 0, 1), and,
• - If provided in accordance with the sequence (Q) of accesses (Z), the current memory address (sa1, sfa1, 2) changes ge, leads to the controlled partial memory (SRAM 0, 1) and in accordance with the status information (sti) Access (Z) to the respective partial memory (SRAM 0, 1) is initiated.

9. Arrangement according to claim 8, characterized, that a partial memory (SRAM 0, 1) by a static Read / write memory (SRAM 0, 1) is realized. 10. Arrangement according to claim 9, characterized, that a partial memory (SRAM 0, 1) by at least one stati The read / write memory circuit is formed. 11. Arrangement according to one of claims 8 to 10, characterized in
that the control logic (ASL) by means of a clock and logic circuit (TLS) and the access cycle and processor clock-appropriate transfer of memory (SP) to read or write to the memory (SP) data (d) effecting intermediate storage ( ASP) is formed,
that the clock and logic circuit (TLS)

• - Has an address buffer (ASP) and is connected to those address lines (ADL4... n) of the processor bus (B), the address information (ai) of which is to be forwarded unchanged to the partial memory (SRAM 0, 1), with the processor-clocked address buffer memory (ASP) the address information (ai) is buffered and the access cycle is controlled according to further address lines (ADL4... N) to the partial memory (SRAM 0, 1), and
• - Equipped with an address control (AST) and connected to those address lines (ADL 2, 3) of the processor bus (B), the address information (ai) during the first access cycle (Z) to the addressed partial memory (SRAM 0, 1) and passed on Sequence address information (ai) in the following access cycles (Z) of a sequence (Q) in the address control (AST) is formed, checked and controlled to the relevant partial memory (SRAM 0, 1), and
• - Is formed by a buffer control (ZSPS) controlling the buffer (ZSP).

12. Arrangement according to one of claims 8 to 11, characterized, that the microprocessor (MP) and the buffer ZSP with a control device (ALD) for dynamic memories (DRAM) is connected, and that the control device (ALD) and the buffer (ZSP) in the sense of reading and Writing data (d) with a dynamic memory (DRAM) is connected, the dynamic memory being opposite to DRAM the static partial memories (SRAM 0, 1) have longer access times having.