DE4424709A1 - Input=output control circuit for, e.g. SRAM, memory chip - Google Patents

Input=output control circuit for, e.g. SRAM, memory chip

Info

Publication number
DE4424709A1
DE4424709A1 DE19944424709 DE4424709A DE4424709A1 DE 4424709 A1 DE4424709 A1 DE 4424709A1 DE 19944424709 DE19944424709 DE 19944424709 DE 4424709 A DE4424709 A DE 4424709A DE 4424709 A1 DE4424709 A1 DE 4424709A1
Authority
DE
Germany
Prior art keywords
circuit
input
lines
data
memory chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE19944424709
Other languages
German (de)
Inventor
Friedrich Lauter
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to DE19944424709 priority Critical patent/DE4424709A1/en
Publication of DE4424709A1 publication Critical patent/DE4424709A1/en
Withdrawn legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus

Abstract

The control circuit is provided in a memory chip. The circuit includes lines for the chip address, data, and control, as well as the coupling lines of the circuit. These lines are directly linked to a microcontroller. The data processing is controlled by a stored program. Pref. the same circuit is used for different input and output modes, e.g. serial or parallel, according to the required use. The controller is distinguished in the same circuit between bit-serial and byte-parallel modes by a control pin.

Description

Die Erfindung betrifft eine Schaltung, mit der die Ein-/Ausgabe von Speicherchips anwenderspezifisch durchgeführt werden kann.The invention relates to a circuit with which the input / output of user-specific memory chips can be.

Nach dem derzeitigen Stand der Technik werden zum Beispiel bei Speicherkarten die Leitungen der darin enthaltenen Spei­ cherchips für Adressen, Daten und Steuerung einzeln herausge­ führt, im allgemeinen unter Zwischenschaltung von Schutz­ schaltkreisen und die Zusammenführung dieser Leitungen der Anwenderschaltung überlassen. Die Vielzahl dieser Leitungen (typisch 30 . . . 60) erfordert einen nicht unerheblichen Auf­ wand bei der Entwicklung und für die Dimensionierung des fer­ tigen Produkts.For example, according to the current state of the art in the case of memory cards, the lines of the memory contained therein cherchips for addresses, data and control individually selected leads, generally with the interposition of protection circuits and the merging of these lines of Leave user circuit. The multitude of these lines (typically 30 ... 60) requires a not inconsiderable opening wall in the development and dimensioning of the fer term product.

In Anwendungen, in denen eine absolute Parallelverarbeitung aus zeitlichen Gründen nicht zwingend erforderlich ist, kann der Einsatz eines Mikrocontrollers die anwenderspezifische Schaltung von Standardaufgaben entlasten und den Schaltungs­ aufwand für das fertige Produkt reduzieren. Darüber hinaus kann dieselbe Schaltung je nach Programmablauf unterschiedli­ che Anwenderschaltungen unterstützen, wie serielle oder par­ allele Ein-/Ausgabe mit typisch 4-6 beziehungsweise 16-18 Leitungen.In applications where absolute parallel processing is not absolutely necessary due to time constraints the use of a microcontroller the user-specific Relieve switching from standard tasks and the circuit reduce effort for the finished product. Furthermore the same circuit can differ depending on the program sequence support user circuits, such as serial or par  allele input / output with typical 4-6 or 16-18 Cables.

Ohne externen Schaltungsaufwand kann damit ein einfacher Da­ tentransfer vorgenommen werden, wenn ein gepuffertes Spei­ chermodul einerseits zum Lesen/Laden an einen Druckerport ei­ nes Personal Computers angeschlossen wird und andererseits nach einfachem Umstecken in einem anderen (Klein-)Rechner zur Abfrage/Verarbeitung dieser Daten dient.A simple da can be done without external circuitry transfer can be made when a buffered memory chermodule on the one hand for reading / loading to a printer port personal computer is connected and on the other hand after simply plugging it into another (small) computer Query / processing of this data is used.

Der Mikrocontroller übernimmt zusammen mit der Ansteuerung der Leitungen der Speicherchips auch die Sicherung der Daten durch potentialmäßige Trennung gegenüber der Anwenderschal­ tung.The microcontroller takes over together with the control the lines of the memory chips also secure the data due to potential separation from the user scarf tung.

Abb. 1 gibt eine Prinzipschaltung an für 8 SRAM Chips zu je 8×128 KB und einen bekannten Controller mit 32 bidirektiona­ len Portleitungen im Vergleich zu Abb. 2, welche eine be­ kannte Schaltung mit integrierten Schaltkreisen nach dem bis­ herigen Stand der Technik zeigt. Fig. 1 shows a basic circuit for 8 SRAM chips each 8 × 128 KB and a known controller with 32 bidirectional port lines compared to Fig. 2, which shows a known circuit with integrated circuits according to the prior art.

Der Controller (11) steuert die (im Beispiel 8) Speicherchips direkt über seine Portleitungen. Abb. 3 gibt eine Schaltungs­ variante an mit Anschluß der data out Leitung (8) an 4 Adreß­ leitungen (17), sowie der bekannten Beschaltung von Bustrei­ ber (24) und or-Gatter (25).The controller ( 11 ) controls the memory chips (in the example 8) directly via its port lines. Fig. 3 shows a circuit variant with connection of the data out line ( 8 ) to 4 address lines ( 17 ), as well as the known wiring of bus drivers ( 24 ) and or-gate ( 25 ).

Der Controller unterscheidet in der dargestellten Schaltung zwischen bitseriell und byteparallel anhand des Steuerpins X.The controller differs in the circuit shown between bit serial and byte parallel using the control pin X.

bitseriellbit serial

Übertragung von Adresse/Daten durch die Leitungen Clock und Data, während die Statusline die Übertragungsrichtung (Lesen/Schreiben), sowie Ende der Übertragung angibt. Transmission of address / data through the clock and Data while the status line is the direction of transmission (Read / write) and end of transmission.  

byteparallelbyte-parallel

Übertragung von Adresse/Daten out durch 8 bit Ausgabeport, sowie je 4 bit Dateneingabe durch Eingabeport, außerdem 4 Ausgabeleitungen, von denen 1 Leitung als clock dient und 1 weitere Leitung wie bei der bitserieller Übertragung die Übertragungsrichtung angibt beziehungsweise reset/Ende der Übertragung.Transfer of address / data out through 8 bit output port, as well as 4 bit data input through input port, also 4 Output lines, 1 of which serves as the clock and 1 further line as in bit serial transmission Direction of transmission indicates or reset / end of Transmission.

Über die low power Leitung (6) kann durch Anhalten der Pro­ zessor clock der Stromverbrauch auch bei eingeschalteter Spannung auf ein Minimum von wenigen Mikroampere gesenkt wer­ den. Der Wiederanlauf erfordert allerdings vor der nächsten Transaktion eine Wartezeit von typ. 1 Millisekunde.Via the low power line ( 6 ), stopping the processor clock can reduce the current consumption to a minimum of a few microamps, even when the voltage is switched on. However, the restart requires a waiting time of typically 1 millisecond before the next transaction.

BezugszeichenlisteReference list

1 master seriell
2 master parallel
3 clock
4 data in/out
5 status
6 low line
7 data out/Adressen
8 data in
9 Steuerleitung
10 Kennung parallel/seriell
11 slave controller
12 Speicherchips
13 chip enable
14 read
15 write
16 chip select
17 Adreßleitungen
18 Datenleitungen
19 master
20 pullup-Widerstand
21 data buffer
22 Adreß-buffer/decoder
23 Control bus buffer
24 Bustreiber
25 AND-Gatter
1 master serial
2 masters in parallel
3 clock
4 data in / out
5 status
6 low line
7 data out / addresses
8 data in
9 control line
10 ID parallel / serial
11 slave controller
12 memory chips
13 chip enable
14 read
15 write
16 chip select
17 address lines
18 data lines
19 master
20 pullup resistor
21 data buffer
22 address buffer / decoder
23 Control bus buffer
24 bus drivers
25 AND gates

Claims (2)

1. Schaltung zur Ein-/Ausgabesteuerung von Speicherchips, dadurch gekennzeichnet,
  • - daß die Adreß-/Daten- und Steuerleitungen eines Speicher­ chips sowie die Anschlußleitungen der Anwenderschaltung grundsätzlich direkt an einen Mikrocontroller angeschlossen sind und die Verarbeitung vom gespeicherten Programm gesteu­ ert wird.
1. Circuit for input / output control of memory chips, characterized in that
  • - That the address / data and control lines of a memory chip and the connecting lines of the user circuit are basically connected directly to a microcontroller and the processing of the stored program is controlled.
2. Schaltung zur Ein-/Ausgabesteuerung von Speicherchips, dadurch gekennzeichnet, daß dieselbe Schaltung je nach Anwendung für unterschiedliche Ein-/Ausgabeformen (seriell oder parallel) eingesetzt werden kann.2. Circuit for the input / output control of memory chips, characterized, that the same circuit for different applications Input / output forms (serial or parallel) can be used can.
DE19944424709 1994-07-13 1994-07-13 Input=output control circuit for, e.g. SRAM, memory chip Withdrawn DE4424709A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE19944424709 DE4424709A1 (en) 1994-07-13 1994-07-13 Input=output control circuit for, e.g. SRAM, memory chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19944424709 DE4424709A1 (en) 1994-07-13 1994-07-13 Input=output control circuit for, e.g. SRAM, memory chip

Publications (1)

Publication Number Publication Date
DE4424709A1 true DE4424709A1 (en) 1996-01-18

Family

ID=6523043

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19944424709 Withdrawn DE4424709A1 (en) 1994-07-13 1994-07-13 Input=output control circuit for, e.g. SRAM, memory chip

Country Status (1)

Country Link
DE (1) DE4424709A1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6948018B2 (en) 2000-12-22 2005-09-20 Siemens Aktiengesellschaft Method and system for exchanging data
EP2126915A1 (en) * 2006-12-12 2009-12-02 Mosaid Technologies Incorporated Memory system and method with serial and parallel modes

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5033027A (en) * 1990-01-19 1991-07-16 Dallas Semiconductor Corporation Serial DRAM controller with multi generation interface
DE4106983A1 (en) * 1990-03-05 1991-09-12 Mitsubishi Electric Corp MICROCOMPUTER

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5033027A (en) * 1990-01-19 1991-07-16 Dallas Semiconductor Corporation Serial DRAM controller with multi generation interface
DE4106983A1 (en) * 1990-03-05 1991-09-12 Mitsubishi Electric Corp MICROCOMPUTER

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
AMITAI,Z.: 1-Mbit DRAM controlles shuns com- plex timing and protocol to streamline high- speed systems. In: Electronic Design, 1.5.86, S.239-244 *
MOORWOOD,A.: Alle Steuerfunktionen integriert, moderne Controller-Chips vereinfachen Aufbau von DRAM-Systemen. In: Elektronik, 2/20.1.89, S.98-104 *
SCHMID,R.: CMOS-DMA-Controller 82C37B mit zu- sätzlichen Programmiermöglichkeiten. In: De- sign & Elektronik, Ausgabe 5 vom 1.3.88, S.94- S.97 *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6948018B2 (en) 2000-12-22 2005-09-20 Siemens Aktiengesellschaft Method and system for exchanging data
EP2126915A1 (en) * 2006-12-12 2009-12-02 Mosaid Technologies Incorporated Memory system and method with serial and parallel modes
EP2126915A4 (en) * 2006-12-12 2010-05-26 Mosaid Technologies Inc Memory system and method with serial and parallel modes
US8169849B2 (en) 2006-12-12 2012-05-01 Mosaid Technologies Incorporated Memory system and method with serial and parallel modes

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8139 Disposal/non-payment of the annual fee