DE4409672A1 - Converter to change video graphic array signals to television signals - Google Patents

Abstract

The VGA/PAL converter comprises an input (IN) for digital information signals, with between one and 625 line buffers (ZO, Z1). A controller (1) is connected to one of the line buffers to synchronise the VGA signals with the PAL signals, and a Digital/Analogue converter (2) is connected to the line buffer output to provide the television image output signal. The controller consists of a peel array, a programmable array or a gate array logic element, and includes a timing circuit (4) to generate timing signals for the relevant television standard. The VGA image refresh rate matches the required television standard image refresh rate and the VGA signals are assigned line by line to the line buffers.

Description

A VGA / PAL converter that digitizes is already known PC images converted into video images in PAL format. They are from marketed by the applicant under the product name MULTIVISION. It can be used to edit digital computer images on the PC changed, supplemented etc. and then on a TV monitor or one Video recorders can be played in television standard. In this way can be a computer image on one or more at the same time TV screens are played.

The computer image can either be derived directly from the PC (WINDOWS) or as a video overlay image using a conversion from PAL to VGA received. To do this, you set your own card, for example a.

The object of the invention is to create a VGA / PAL converter, that is as simple and compact as possible and that without Data loss when converting from VGA to PAL or another TV standard works.

A VGA / PAL converter with the Features of claim 1.

This ensures that a VGA image is sent to a television monitor  output and displayed by this. That from television monitor displayed image can also be an original television picture be that with a known circuit on a so-called called "multimedia card" converted to a VGA image and again was converted back into a television picture. The VGA image can edited on the PC, i.e. have been changed, for example by adding fonts, shadows, colors, magnifications, Superimposition of and with other images, etc. It is on it noted that the television picture obtained according to the invention also simultaneously transmitted to and from several television monitors can be displayed.

Advantageous embodiments of the invention are the subject of Subclaims.

The invention is described in more detail below with the aid of a drawing explains:

A VGA image signal, as it is used in a personal computer or a similar computer to build up the computer image, is applied to the input IN of the circuit according to the invention. Each line of the VGA image signal is represented by 16 bits, for example. The VGA image signal is transmitted to the inputs of two line buffers Z0 and Z1, which are controlled by a controller 1 . The two line buffers Z0 and Z1 are buffers known per se, for example bucket string memories, shift registers or video RAMs. The only thing that matters is that they record the digitized picture information of a VGA picture line in accordance with the VGA clock sequence of 56 Hz, 60 Hz or 70 Hz and output it with the frequency of the desired video picture, for example 50 Hz in the PAL process. For NTSC it would be 60 Hz, for SECAM it would be 50 Hz. The line buffer Z0 - controlled by controller 1 - receives the VGA image signal of a first line and the line buffer Z1 the VGA image signal of a line after next. The image signals for the odd lines are first written to the line buffers Z0 and Z1 one after the other and then, after a new image structure, the signals for the even lines are applied to the line buffers. In this way, two fields appear, as is usual for television pictures.

In detail, the VGA image signal is first written into line buffer Z0 for the first line and read out almost simultaneously, controlled by signals Enable 0 and Out 0 from controller 1 . With Enable 0 the writing into the line buffer Z0 is started, with Out 0 the reading out of the line buffer Z0. The line signal output by the line buffer Z0 is applied to a digital / analog converter 2 , which converts it into three analog color signals RGB and applies this to a circuit 3 , which, under the control of a timing generator 4 , generates one CVBS and two Y / C Signals generated.

Towards the end of the reading of the 1st line from the first line buffer Z0 is written the 3rd row of the VGA-image signal in the second Zeilenpuf fer Z1 and read out at the occurrence of a signal Out 1 by the controller 1 is also in the digital / analog converter. 2 Towards the end of reading out the 3rd line, the image signal for the 5th line of the VGA image is already written into the first line buffer Z0 and then read out immediately, the line signal for the 7th line then being read into the second line buffer Z1. The process continues until the last line of the VGA image. The VGA image signal of a new image structure is then processed line-by-line in a similar manner, but now not as a result of the odd lines, but rather as a result of the even lines two, four, six, eight, etc. The line buffers Z0 and Z1 are each written by applying an enable signal 0 or 1 from controller 1 . The controller 1 is actuated with a vertical synchronizing signal of the VGA picture in order in this way to time-control the enable signals for the line-by-line reading of the VGA picture lines. The timing generator 4 is also controlled with the VGA vertical synchronizing signal VSYNC and drives a clock generator (CLOCK), which generates a reset bit for the circuit 3 . This is also supplied with vertical and horizontal synchronization pulses for the television picture, for example in the PAL standard.

A programmable semiconductor circuit, for example of the type PA7024 from IDT, is used as controller 1 . Suitable programmable components are so-called peel arrays, PALs, GALs or ASICs. Such modules are familiar to the person skilled in the art.

The programming of the controller 1 has to be carried out in such a way that first all odd-numbered lines (1.Z, 3.Z, 5.Z,...) Of a VGA picture are written in succession and read out at the frequency of the television picture, followed by the writing of the even-numbered line signals (2.Z, 4.Z, 6.Z,...).

Claims (9)

1. VGA / PAL converter characterized by :

• - A signal input (IN) for a digital image information signal;
• - At least one line buffer (Z0, Z1) for the image information signal;
• - A controller ( 1 ) connected to the at least one line buffer (Z0, Z1) for the synchronization of the VGA signal with the PAL signal; and through
• - A D / A converter ( 2 ) which is connected to the at least one line buffer (Z0, Z1) and is used to output the television picture signal.

2. Converter according to claim 1, characterized in that two Line buffers (Z0 and Z1) are provided. 3. Converter according to claim 1, characterized in that up 625 line buffers are provided. 4. Converter according to claim 1, characterized in that the controller ( 1 ) is a programmable logic module. 5. Converter according to claim 4, characterized in that the controller ( 1 ) is a peel array, a programmable array logic or a gate array logic. 6. Converter according to one of claims 1 to 5, characterized in that a timing generator ( 4 ) is provided for generating timing signals for television standard. 7. Converter according to claim 6, characterized in that the timing generator is integrated in the controller ( 1 ). 8. A method for converting digital VGA signals into analog television signals, characterized in that

• - That the refresh rate of the VGA card (normally 56 Hz, also 60 and 70 Hz usual) is brought to the refresh rate of the desired television standard (e.g. 56 Hz → 50 Hz);
• - That the digitized VGA signal is applied line by line to one or more line buffers, first the odd lines and the next lines the even lines;
• - And that a line is written into the line buffer and is output almost simultaneously with a low frequency, with the next even or odd line being written into the line buffer towards the end of the output.

9. The method according to claim 8, characterized in that the Line signals alternately into a first and a second Line buffers are written.