DE4404129A1 - Conducting structure prodn. on topography of substrate - Google Patents

Abstract

Prodn. of a conducting structure having several pins on the topography of a starting substrate comprises: (a) forming 1st, 2nd and 3rd insulating layers (27,28,29) completely over the topography; (b) patterning and etching an opening (30) in the 3 insulating layers; (c) forming and planarising a conducting layer (31) by filling the opening; (d) creating an etching mask (33) by applying polysilicon having semispherical grain size for pattern transfer; (e) transferring an archipelago pattern over the etching mask onto the planar conducting layer; and (f) forming pins (34) to create the conducting structure having the several pins.

Description

The present invention relates to semiconductor circuit Storage devices, and more particularly relates to a method for Manufacture of high-density DRAM (Dynamic Random Access memory arrangements) used three-dimensional stack cell steering capacitors.

In dynamic semiconductor memory devices, it is essential that the cell plates of the storage node capacitors are large enough to to maintain an adequate charge. As with most inte semiconductor semiconductor circuits is the case, the circuit density decreases at a fairly constant rate. The point of view of the Maintaining storage node capacity is particularly important tion, since the density of DRAM devices for future generations storage devices continues to increase.

The ability to pack memory cells tightly while doing the necessary Maintaining capacity levels is a key requirement Semiconductor manufacturing technologies when future generations expand terter storage devices are to be successfully manufactured.

A method of maintaining and increasing memory node size in densely packed storage devices is in the Use of the "stack memory cell" structure. With this technology two or more layers of a conductive material, such as. B. polycrystalline silicon (hereinafter referred to as polysilicon), about an access device is applied to a silicon wafer, wherein dielectric layers sandwiched between each polysilicon layer to be ordered. A cell designed in this way is under the  Designation stacked capacitor cell (STC) known. Such a cell uses the space above the capacitor plate access device, has a low soft error rate (SER) and can connect with high insulating layers between the plates Dielectric constant can be used.

However, it is difficult with a conventional STC capacitor to achieve sufficient storage capacity because the storage elec area on the limits of its own cell area is restricted. Also maintaining good dielectri dielectric strength between polysilicon layers in the STC capacitor becomes a big problem once the thickness of the isola tors is appropriately dimensioned.

A study by J.H. Ahn et al. submitted article entitled "Micro Villus Patterning (MVP) Technology for 256Mb DRAM Stack Cell ", 1992 IEEE, 1992 Symposium on VLSI Technology Digest of Technical Papers, pages 12 and 13, by reference to an ingredient of the present application discusses the technology of Micro villus patterning (MVP or Micro Villus Patterning) for Development of a three-dimensional stack capacitor in the Storage node cell plate built-in vertical villi-like bars or pens.

However, the use of the MVP technology can lead to splinter problems (or flaking) in the storage node polysilicon if the MVP technology is used to form three-dimensional stack capacitors in the manner described by the cited document. As shown in FIG. 11, parallel word lines 12 shown in cross section have been produced on a silicon wafer 10 . Storage nodes 13 (which make contact with active areas 11 ) have been formed from storage node polysilicon 14 and polysilicon micro villus rods or pins 15 . As can be seen in this cross-section, the micro villi pins 15 are prone to splintering, which can result in overturning polysilicon chips, which could cause a short circuit to adjacent storage node polysilicon, thereby short-circuiting the adjacent memory cells and thereby rendering them unusable. When using hemispherical grain polysilicon, as is the case in Figure 11, the variable grain size also results in variable pin diameters, with a percentage of these pins having diameters less than 0.0100 µm which are even more susceptible to breakage and splintering .

If e.g. B. in a 64 Mb DRAM only one in 100,000 cells one Would have short circuit due to such splintering this results in 640 statistical errors in the 64 Mb DRAM, where these are more errors than could be repaired. As for the repair Only a limited number of redundant elements are available stands, the entire storage device would be unusable. It is therefore desirable to use the memory cell capacity Technologies, like MVP technology, increase while the same timely associated with the splintering of the storage node polysilicon problems are eliminated.

U.S. Patents 51 62 248 and 50 61 650 are incorporated by reference made part of the present application, since it ver drive to form container-like storage node cells.

The present invention develops conductive structures that can be used for storage node electrodes for storage cells. A first embodiment of the invention involves making a multi-pin conductive structure on the existing topography of a starting substrate using the following steps:
Forming a full-surface first insulating layer over the existing topography;
Patterning and etching an opening in the first insulating layer to form a container-like shape;
Forming and planarizing a first conductive layer to fill the container-like shape and thereby separate another adjacent storage node;
Forming a full-surface second insulating layer over the first conductive layer and the first insulating layer;
Forming a rugged surface over the second insulation layer; Transferring an archipelago pattern to the first planarized conductive layer; and
Formation of villi-like pins in the first conductive layer, resulting in the formation of the multi-pin conductive structure.

A second embodiment of the present invention involves making a multi-pin, conductive, container-like structure on the existing topography of a starting substrate using the following steps:
Formation of a full-surface first insulating layer over the existing topography;
Patterning and etching an opening in the first insulating layer to form a container-like shape;
Forming and planarizing a first conductive layer to fill the container-like shape;
Deepening the planarized first conductive layer;
Forming a full-surface second insulating layer over the first conductive layer and the first insulating layer;
Forming insulating spacers at the recessed edges of the first conductive layer;
Forming a rugged surface layer over the second insulating layer;
Transferring an archipelago pattern to the first planarized conductive layer; and
Form villi-like pins to form a plurality of pins located inside the conductive container-like structure.

A third embodiment of the present invention involves the fabrication of a multi-container conductive structure based on the topography of a starting substrate using the following steps:
Forming a full-surface first insulating layer over the existing topography;
Patterning and etching an opening in the first insulating layer, the opening defining a container-like shape;
Forming and planarizing a first conductive material to fill the container-like shape;
Deepening the planarized first conductive material;
Forming insulating spacer elements and conductive spacer elements in an alternating manner on the recessed upper surface of the first conductive material; and
Removing the plurality of conductive spacers and digging into the underlying first conductive material to form the multiple container structure.

Preferred developments of the invention result from the sub claims.

The invention and further developments of the invention are as follows based on the drawings of several embodiments explained in more detail. The drawings show:

Figure 1 is a cross-sectional view showing the results of process steps which are performed in a second embodiment of the present invention.

Fig. 2-4 cross-sectional views showing the results of process steps that are carried out in a first embodiment of the present invention;

Fig. 5-7 cross-sectional views showing the results of process steps which are carried out in the second embodiment of the present invention;

Fig. 8-10 cross-sectional views showing the procedural steps that are performed in a third exemplary embodiment of the present invention; and

Figure 11 is a cross-sectional view of a polysilicon storage node developed using micro villi technology.

The present invention is directed to maximizing the memory cell surface area in a manufacturing process for manufacturing high density / large volume DRAMs, as shown in FIGS. 1-10 .

A silicon wafer is manufactured using conventional manufacturing steps to the point where a capacitor cell is defined. At this point, the manufacture of word lines, associated active areas and optional digits completed for a capacitor over a digit line flow sen (the invention can also be used in stacked capacitor cells with condensers gate under the digit line flows). The procedure steps of the various embodiments of the present invention are explained below.

Figs. 2 to 10 show three embodiments of method steps illustrating the present invention in a series of cross-sectional views through parallel word lines. The Fig. 2 show a first embodiment, FIGS to 4. 5 to 7 a second embodiment, and FIG. 8 Guide for example to 10, a third stop, wherein these embodiments are all described starting from a cross-sectional view through the word lines.

Referring first to FIG. 2 of the first embodiment, word lines 25 extend between active areas 21 formed in substrate 20 to thereby form active transistors. The word lines 25 comprise a conductive layer 22 which is covered with dielectric 24 and is surrounded by dielectric elements 23 . Dielectric 27 has been applied and made planar, after which a dielectric layer 28 is applied (nitride or an oxide working with a low wet etching rate is preferred). A layer of dielectric material 29 (it is preferred to use oxide or an oxide that works at a high wet etching rate, such as, for example, borophosphosilicate glass, hereinafter referred to as BPSG for short) has been applied and made planar, after which a contact / container Exposure and etching is performed to create a contact / container opening 30 , thereby providing access to the active area 21 . If desired, a single layer 27 of thick dielectric material can be applied in place of layers 27 , 28 and 29 . After the contact / container opening 30 is formed, a polysilicon layer 31 doped in place is applied to completely fill the contact / container opening 30 . The polysilicon 30 is then formed planar (preferably by chemical mechanical planarization) in order to isolate the adjacent storage nodes from one another.

Referring to Fig. 3, a hard etch mask is formed by applying an oxide layer 33 (about 0.05 µm thick), followed by the application of hemispherical grain polysilicon. To complete the mask, a partial polysilicon plasma etching process of the polysilicon with hemispherical grain is carried out in order to transfer a rugged surface to the underlying oxide, whereupon a plasma oxide etching process of the oxide 33 takes place. After the hard etching mask has been formed, a time-controlled polysilicon etching process is carried out sufficiently long to transfer an “archipelago” pattern, which can be seen in FIG. 3, to the storage polysilicon 31 . Transfer of the "archipelago" pattern to polysilicon 31 results in the formation of very thin villous polysilicon rods or pins 34 , thereby creating a multi-pin storage node polysilicon structure 35 according to the present invention.

Referring to FIG. 4, a Zellendielektrikum is applied 41 over the storage node polysilicon 35, which takes place the deposition of polysilicon 42, to thereby form the second Kondensatorelek trode. From this point on, conventional method steps for the completion of the semiconductor device take place.

In a second embodiment, as shown in FIG. 5, the word lines 25 extend between active regions 21 that have been formed in the substrate 20 to thereby form active transistors. The word lines 25 include a conductive layer 22 , which is covered with dielectric 24 and is surrounded by dielectric elements 23 from . A dielectric 27 has been applied and planar, after which a dielectric layer 28 is applied (with nitride being preferred). A layer of dielectric material 29 (oxide is preferred) is deposited and planarized, followed by contact / container exposure and etching to create a contact / container opening 51 , thereby accessing the active one To create area 21 . After the contact / container opening 51 has been formed , a polysilicon layer 52 doped in place is applied such that the contact / container opening 51 is completely filled. The polysilicon 52 is then formed planar (preferably by chemical-mechanical planarization) in order to separate the adjacent storage nodes from one another. Next, the polysilicon 52 is etched to recess its planar surface so that it is below the planar surface of the oxide 29 . The next step is to apply an oxide layer 53 with a thickness of approximately 0.1 μm to cover the oxide 29 and the recessed polysilicon 52 .

Referring to FIG. 5A, a layer of hemispherical grain polysilicon 54 is applied and then partially etched, with polysilicon plasma etching on the hemispherical grain polysilicon 54 , leaving poly silicon with a fissured surface over the oxide 53 .

Referring to Fig. 5B, the rugged surface of the underlying oxide layer 53 is used for transmitting an oxide plasma etch process performed. The oxide plasma etching process on the oxide layer 53 leads not only to the transfer of the fissured surface to the oxide 53 , but also to the formation of oxide spacers 55 .

Referring to FIG. 6, a timed polysilicon etch is performed for a sufficient length of time to adequately transfer an "archipelago" pattern to polysilicon 52 . It is important that the oxide etch is also timed before the timed polysilicon etch so that the oxide etch does not penetrate through the oxide spacer. The transfer of the "archipelago" pattern to the polysilicon around 52 leads to the production of very thin villi-like polysilicon pins 61 , as a result of which a storage node polysilicon structure 63 having a plurality of pins is formed. In addition, a continuous polysilicon can 62 is formed which surrounds the villous pins 61 and prevents any of the villous polysilicon pins from falling over and causing a short circuit with any adjacent cell of the present invention. Next, hydrofluoric acid-based etching may optionally be performed to gain the outer surface of the storage node for an increase in surface area.

As can be seen with reference to FIG. 7, which corresponds to FIG. 1, a cell dielectric 71 is applied over the storage node polysilicon 63 , followed by the application of polysilicon 72 to thereby form the second capacitor electrode. From this point on, conventional method steps are used to complete the semiconductor device.

As can be seen with reference to FIG. 8, in which a third exemplary embodiment is shown, the word lines 25 extend between active regions 21 which have been formed in the substrate, to thereby form active transistors. The word lines 25 include a conductive layer 22 , which is covered with dielectric 24 and is surrounded by dielectric spacer elements 23 . Dielectric 27 has been applied and made planar, after which a dielectric layer 28 is applied (with nitride being preferred before). A layer of dielectric material 29 (preferably oxide) is applied and planar, after which a contact / container exposure and etching process is carried out to create a contact / container opening 81 , thereby accessing the active region 21 to accomplish. After the formation of the contact / container opening 81 , the application of a locally doped polysilicon layer 82 takes place in such a way that the contact / loading container opening 81 is completely filled. The polysilicon 82 is then formed planar (preferably by a chemical-mechanical planarization process) in order to separate the adjacent storage nodes from one another. Next, the polysilicon 82 is etched to deepen its planar surface below the planar surface of the oxide 29 (approximately 0.2 µm). This is followed by an oxide application (approx. 0.06 to 0.10 μm thick), and oxide spacer elements 83 are formed by a subsequent spacer element etching process. The next step is the application of polysilicon (approx. 0.06 to 0.15 μm thick), and polysilicon spacer elements 84 are formed by a subsequent spacer element etching process. This is followed by a second application of oxide (approx. 0.10 μm thick), and oxide spacer elements 85 are formed by a subsequent spacer element etching process. At this time, if desired, a plurality of polysilicon spacers (each separated by an oxide spacer) can be formed, which after performing a long polysilicon etch to form multiple (ie, two, three, etc.) containers in the storage node polysilicon 91 lead, as can be seen in the drawing.

As can be seen with reference to FIG. 9, oxide 29 is etched to expose the outer walls of double storage node container 91. At this point it is also possible to either leave the storage node polysilicon as it is , or to apply a layer of polysilicon with hemispherical grain. When polysilicon with hemispherical grain is applied, a full-surface etching of the polysilicon with hemispherical grain follows, which leads to the formation of polysilicon 92 (textured or fissured polysilicon) with hemispherical grain around the storage node polysilicon container 91 .

Referring to FIG. 10, cell dielectric 101 is deposited on the storage node container polysilicon 91 , after which the polysilicon 102 is deposited to form the second capacitor electrode. From this point, conventional method steps are carried out to complete the semiconductor device.

Although the preferred cell dielectric is nitride, any material with a high dielectric constant, e.g. B. Ta ₂ O ₅ or SrTiO ₃ could be used. For all the embodiments of the present invention described above and for any modifications thereof, the polysilicon deposited to form the second cell plate of the capacitor is doped to conductively, either n-type or p-type, this being the case for the active Area 21 desired conductivity type is dependent. From this point, conventional method steps are carried out to complete the semiconductor device.

Claims (11)

1. A method for producing a conductive structure having several pins on the existing topography of an initial substrate, characterized by the following steps:

• a) forming a full-surface first, second and third insulating layer ( 27 , 28 and 29 ) over the existing topography;
• b) patterning and etching an opening ( 30 ) in the first, second and third insulating layers;
• c) forming and planarizing a conductive layer ( 31 ) while filling the opening;
• d) creating an etch mask ( 33 ) by applying a semi-spherical grain polysilicon for a pattern transfer;
• e) transferring an archipelago pattern via the etching mask to the planarly formed conductive layer; and
• f) Forming villi-like pins ( 34 ) to create the multiple pin conductive structure.

2. The method according to claim 1, characterized in that the formation of the conductive layer ( 31 ) includes the application of a locally doped polysilicon layer. 3. Method for producing a conductive structure having several pins on the existing topography of an initial substrate, characterized by the following steps:

• a) forming a full-surface first, second and third insulating layer ( 27 , 28 and 29 ) over the existing topography;
• b) patterning and etching an opening ( 63 ) in the first, second and third insulating layers;
• c) forming and planarizing a conductive layer ( 31 ) while filling the opening;
• d) making a recess in the planarized conductive layer;
• e) forming a full-surface fourth insulating layer ( 53 ) over the recessed, planarized conductive layer and the third insulating layer;
• f) forming a jagged surface layer ( 54 ) over the fourth insulating layer by depositing silicon with hemispherical grain;
• g) transferring an archipelago pattern over the rugged surface layer and a surrounding ring ( 55 ) to the deepened, planarized conductive layer; and
• h) forming villi-like pins ( 61 ) to create the multi-pin conductive structure.

4. The method according to claim 3, characterized in that the formation of the conductive layer ( 52 ) includes the application of a locally doped poly silicon layer and the formation of the fourth insulating layer ( 53 ) includes the formation of an oxide layer. 5. The method according to claim 3 or 4, characterized in that the transfer of the archipelago pattern to the planarized conductive layer ( 52 ) comprises the following steps:

• a) performing a polysilicon plasma etch on the polysilicon ( 54 ) with hemispherical grain;
• b) performing an oxide plasma etch on the fourth insulating layer ( 53 ); and
• c) performing a timed polysilicon etch on the planarized conductive layer ( 54 ).

6. Method for producing a conductive structure having a plurality of pins on the existing topography of an initial substrate, characterized by the following steps:

• a) forming a full-surface first, second and third insulating layer ( 27 , 28 and 29 ) over the existing topography;
• b) patterning and etching an opening ( 91 ) in the first, second and third insulating layers;
• c) forming and planarizing a conductive layer ( 82 ) while filling the opening;
• d) making a recess in the planarized conductive layer;
• e) removing the third insulating layer exposing the outer walls of the conductive layer;
• f) forming insulating spacers ( 83 , 85 ) and conductive spacers ( 84 ) in alternating fashion on the recessed surface of the conductive layer; and
• g) removing the conductive spacers and digging into the underlying conductive layer to form the multiple pin structure.

7. The method according to claim 6, characterized in that the following additional steps take place between steps f) and g):
Forming a second conductive layer ( 92 ) on the exposed walls of the conductive layer and the exposed surfaces of the structure; and
Forming a textured surface on the second conductive layer, the textured surface adhering to the conductive layer. 8. The method according to claim 6 or 7, characterized in that the formation of the first conductive layer ( 82 ) includes the application of a poly silicon layer doped in place, that the formation of the textured surface ( 92 ) the application of polysilicon with a hemispherical Grain, and that forming the alternating insulating ( 83 , 85 ) and conductive ( 84 ) layers includes forming a first oxide spacer, forming a polysilicon spacer, and forming a second oxide spacer. 9. The method according to any one of claims 1, 3 and 6, characterized in that the planarization of the conductive layer ( 31 ; 82 ) is carried out by chemical-mechanical planarization. 10. Produced on the existing topography of a starting substrate, several pins, conductive, container-like structure, characterized by:
a patterned planar conductive layer ( 52 ) having a container-like structure ( 82 ) formed around the circumference of its patterned walls and having a plurality of villi-like pins ( 61 ) formed within the walls of the container-like structure , so that the container-like structure and the multiple villi-like pins thereby form the multiple-pin conductive container-like structure. 11. On the existing topography of a starting substrate, multiple-pin, container-like polysilicon memory cell ( 63 ), characterized by:

• a) a patterned, planarized, on-site doped first polysilicon layer ( 52 ) with a container-like structure ( 62 ) which is formed around the circumference of its patterned walls, and with inside the walls of the container-like Structure formed, a plurality of villi-like pins ( 61 ), wherein the container-like structure and the plurality of villi-like pins thereby form a conductive, container-like structure serving as a first storage cell electrode, having a plurality of pins;
• b) a cell dielectric ( 71 ) overlying the multiple pins on facing, conductive, container-like structure; and
• c) a conductively doped second polysilicon layer ( 72 ) which lies above the cell dielectric and thereby forms a second storage cell electrode.