DE4317175A1 - Self-test device for memory arrangements, decoders or the like. - Google Patents

Abstract

PCT No. PCT/DE94/00521 Sec. 371 Date Jan. 20, 1995 Sec. 102(e) Date Jan. 20, 1995 PCT Filed May 6, 1994 PCT Pub. No. WO94/28555 PCT Pub. Date Dec. 8, 1994A self-test device for memory arrangements, decoders or the like for use during on-line operation, the word lines and/or the column lines of a memory matrix being connected to a check matrix. An error detector which generates an error signal if more than one line is activated simultaneously is connected to the check matrix. Since multiple word lines or column lines are activated in the decoder for most errors which occur, a simple self-test can be performed during on-line operation by this check matrix which can be implemented in a relatively simple and cost-effective manner.

Description

State of the art

The invention relates to a self-test device for Memory arrangement, decoder or the like for use in online Line operation, with means for checking a variety of word lines are provided.

From IEEE Trans. On Computer-Aided Design, Vol. 9, No. 6, June 1990, pp. 567-572, "A Realistic Fault Model and Test Algorithms for Static Random Access Memories ", are Ver drive to the off-line test of memory arrays known. Some of these processes are also known as "built-in-self- Test "can be used, but because of the very many required test pattern and the destruction of the memory content only conditionally for the test during operation (quasi on- line) can be used. In addition, the required test length for use in the online test.

Furthermore, from "Defect and Fault Tolerance in VLSI Systems ", in Koren, Plenum Press, New York, 1989 (design of Fault-Tolerant DRAM with new on Chip ECC - Mazumber, P.) arrangements with coding data known, wherein different codes are used. One of the like coding only prevents a very small one Part of possible hardware errors in the one to be checked  Storage arrangement.

Finally, there are procedures that use a ROM the actually selected memory cell is determined and whose address is compared with the desired address.

In particular, row and column addresses are made out read and with the input address in a self checking-checker compared. Such procedures are at for example from "Self-checking Flash-EPROM", M. Nicolaidis, contribution to the JESSI SE 11 project, presentation to the lecture on September 16, 1992 in Grenoble, or from "Efficient ubist implementation for microprocessor sequencing parts ", M. Nicolaidis, June 1990, publication of In stituts IMAG / TIM 3, 46 Avenue F´lix Viallet, 38031 Greno ble, known. However, these self-test facilities are very complex circuitry and cover al just remove the decoder errors.

Overall, the known self-test facilities and -Procedure either very few mistakes opportunities, or they are very expensive Lich the required hardware or very time consuming so that they are not suitable for online operation.

Advantages of the invention

The self-test device according to the invention with the kenn drawing features of the main claim has in contrast the advantage that single to monitor the word lines A so-called 1-out-of-n tester is used, who an error message about an error in online mode detector emits if more than one word at the same time line is active. This will make most of them  Sources of error are detected in the decoder, and on the other hand this can be self Test carried out with very little effort and very quickly leads. Virtually all addressing errors are detected, provided that the coding of the Address with a suitable code in connection with con structural rules and a code check is that a single fault does not have two word lines in reversed direction. In addition, through the Choice of the data code to be ensured that at Activation of no word line is a faulty code is recognized.

By the measures listed in the subclaims are advantageous developments and improvements of self-test facility specified in the main claim possible.

A preferred embodiment of the 1- n tester is that each word line in the test matrix each with control connections of z switches one Switch matrix is connected through the z to a first Potential (Vdd) applied test lines accordingly the coding of the respective word line either with second potential (Vss) connections or with a sensor line can be connected, which also with the first potential (Vdd) is applied, the error detector connected to the sensor line and as a current or Voltage sensor is formed. Are two words active at the same time, the fault detector is activated two switches connected to the second potential, so that one increased current or a change in the potential can be put.  

The switches of the switch matrix are expediently as FET transistors formed, and the second Connections with potential (Vss) are ground Connections trained.

To increase test reliability, the test matrix is in advantageously even by a test facility checked the function of the switch the switch matrix tests. Doing so at larger intervals all switches checked sequentially.

An advantageous embodiment of this test device be is that the test leads in the test facility associated with tristate drivers, through each the one with the scarf to be checked and controlled ter connected test line according to the switch code either on the second potential (Vss) or is connectable to the sensor line. This allows the Functionality of all switches tested one after the other become.

In addition, means for Checking parallel to the word lines Supply lines can be provided that the first (Vdd) and / or the second potential (Vss). The review of the Ver applied with the second potential Supply lines can be similar to checking the scarf ter done by the test facility. For checking the supplier charged with the first potential (Vdd) supply lines are additional switches for controllable Connection of the supplier with this first potential supply lines provided with the sensor line, wherein these switches through the word lines and / or through too  additional control lines are controllable. Thereby will the discharge of the sensor line by testing the second potential supply lines at high ohmic output drivers of the test facility Charging the sensor cable after having closed the additional switch checked.

If the self-test setup for storage arrangements, for example RAM or ROM memories used, so expediently a first test matrix for the time len lines and a second test matrix for the column Lines used.

With the 1-out-of-n-tester according to the invention, addresses errors that increase the number of activations are recognized rer word lines. Incorrectly created addresses and word line / gap interchanged by a single defect This means that tendecoder lines cannot be recognized the. In order to recognize these possible errors, too the input addresses are encoded, and for verification is a Code checker provided. If a single De However, the negated and the non-negated value of a Address bits would change, so the code reviewer could the 1-out-of-n examiner does not recognize this. To make this mistake ability to grasp are those of the individual Address lines branching, ungrounded and the two lines that are negated by an inverter det realized from each other without common branch points. This practically excludes that simultaneous Interruptions in two lines due to a defect stand. The 1-out-of-n examiner can then do this Detect interrupted service. Everybody owns this lei connected gates to the same input  threshold, that is, all of these gates turn on finally the code checker at the same voltage level their output level, so short circuits between two lines can be detected. Since this requirement dimensioning is not always available fonts for the input inverters of the address lines and described the decoder gates and the code checker, by the in the event of short circuits between negated or un negated address lines either in the code checker or in the 1 out of n inspector an error is detected.

Even greater security can be achieved that both inverters with a current monitoring device are connected. Short circuits can then be made directly via a increased current through the current monitoring device be recognized.

An even more advantageous solution is that of each the address line initially spaced from each other and the ungrounded lines without a common branch point branch that the inverter for the negated branches Lines is connected in the address line, and that from negated area of the address line spaced apart and without common branch points the negated lines branch off. With these stricter design rules, he can be enough that one instead of the 1-out-of-n tester more flawless neighbor auditor can be used, the single checks whether two word lines are active at the same time, the neighboring addresses are assigned. Such one Neighbor checker is from "Error Detecting Codes, Self-checking Circles and Applications ", J. Waker ly, Elsevier, North Holland, 1978.

drawing

Embodiments of the invention are in the drawing shown and in the following description explained. Show it:

Fig. 1 is a block diagram of a memory array having row decoders and column decoders,

Fig. 2 is a schematic representation of a 1-of-n examiner

Fig. 3 is a schematic representation of a test facilities for processing the 1-of-n-auditor

Fig. 4 is a circuit diagram of a ROM-line for checking a precharge line of the sense amplifier and the read signals of the memory device,

Fig. 5 a modified 1-of-n-examiner for checking zusätz union to the word lines arranged in parallel supply lines,

Fig. 6 shows the geometrical arrangement of the address line from a branching non-inverted and negated lines,

Fig. 7 shows a similar arrangement with an additional current monitoring device,

Fig. 8 shows a further embodiment of the arrangement of geometric standpoint of a single address line branching negated and non-inverted lines,

Fig. 9 shows a similar arrangement with an additional current monitoring device and

Fig. 10 shows the schematic representation of a gate in static CMOS technology.

Description of the embodiments

The memory arrangement shown in FIG. 1 is, for example, a RAM memory and consists, in a manner known per se, of a memory matrix 10 , a row decoder 11 connected to it and a correspondingly connected column decoder 12 . The column decoder is connected via a sense amplifier 13 and a signature checker 14 to a data bus 15 for reading in and reading out data. An address bus 16 of width y + z bits, of which z bits are used for word line selection and y bits for column selection, is connected to row decoder 11 and column decoder 12 in order to be able to select n = 2 ^z row addresses and p - 2 ^y column addresses . The row decoder 11 is thus connected to the memory matrix 10 in a manner not shown in more detail via n row or word lines and the column decoder 12 via m × p (m = bit width of the data word) column lines. The n word lines of the memory matrix 10 are assigned a 1-out-of-n checker 17 and the p column lines that are generated in the column decoder 12 are assigned a corresponding 1-out-of-p checker.

The 1-out-of-n tester 17 is shown in more detail in FIG. 2. Of the n row or word lines, only the two word lines i and j are shown for simplicity. The word lines extend in parallel into a switch matrix 19 in which z test lines 20 run perpendicular to the n word lines. Outside the switch matrix 19 , a sensor line 21 runs parallel to the test lines 20 . The test lines 20 and the sensor line 21 are acted upon by a precharge device 22 with a first potential Vdd. Each word line is coded differently by FET transistors, and in the special case the coding can correspond to the address bits of the respective word line. For this purpose, each word line drives z of these FET transistors in parallel, which are connected to the z test lines 20 . For coding, the respective FET transistor connects the test line either to the sensor line 21 or to a connection at a lower potential Vss, in the exemplary embodiment the ground connection.

In the exemplary embodiment shown, the coding of the word line i has, for example, a 1 at the beginning and a 0 at the end. The corresponding first FET transistor 23 assigned to the first test line therefore connects this first test line 20 to the sensor line 21 , while the last, that is to say the z-th, FET transistor 24 connects the z test line to ground. The reverse is true for the word line j, where the first FET transistor 25 connects the first test line to ground, and the last FET transistor 26 connects the z test line to the sensor line 21 .

The sensor line 21 is connected to a current sensor 27 which detects indirectly by changing the potential on the sensor line 21 whether a current is flying via the test lines 20 to the lower potential Vss (in the exemplary embodiment from ground). Furthermore, a test device 28 is connected to the z test lines 20 and the sensor line 21 , which will be described in more detail in connection with FIG. 3.

Since each word line is coded differently in the switch matrix 19 , the sensor line 21 precharged to the potential Vdd is discharged when more than one word line is active. If, for example, both word lines i and j are active, the sensor charge 21 is discharged via the transistors 23 and 25 as well as via the transistors 24 and 26 . Since each word line is coded differently, a transistor combination is always inevitable, which brings about this discharge with two active word lines. Due to the discharge, a current is detected in the current sensor 27 and an error message is issued in a manner not shown. This indicates to the user that there is an error.

To check the column address, the 1-out-of-p checker 18 is used, with the difference that instead of n word lines, p column lines are now checked.

In Fig. 3, the testing device is shown in more detail 28th It essentially consists of z tristate drivers 29 , each tristate driver being connected to one of the test lines 20 . Furthermore, the sensor line 21 charged with the potential Vdd is connected to all the tristate drivers 29 . On the control side, a common test signal P and individual test signals T1 to Tz are applied to all Tristate drivers 29 .

Using this test device 28, all FET transistors tion capacity on their radio tested 23-26 of the switch matrix 19 in succession, with this test, both for a read / write access to which can be effected angespro chene word line (individual columns or all consecutively) or completely in Larger intervals in the event of an interruption in the storage arrangement.

The verification of the transistors 23 , 26 connected to the sensor line 21 is explained using the example of the transistor 23 . First, test signals P and T1 are generated, through which the first test line connected to transistor 23 is connected to the low potential Vss. A control signal is then applied to word line i. If the transistor 23 functions properly, it pulls through the potential of the sensor line 21 to Vss, so that the current sensor 27 responds. This response here means a confirmation signal for the proper function of this transistor 23rd

The test of the transistors 24 , 25 connected to ground is explained using the example of the transistor 24 . The z test line is connected to the sensor line 21 by corresponding test signals P and Tz. If a signal is now placed on the word line i, the transistor 24 in turn pulls the potential of the sensor line 21 to Vss when the transistor 24 is functioning properly, so that the current sensor 27 responds. In this way, all transistors can be checked one after the other. The generation of the required test signals P and T and the corresponding signals on the word lines is carried out by a signal sequence control (not shown) or a microcomputer (not shown). The entire 1-out-of-n-tester is tested with n × z test steps. The 1-out-of-p checker 18 can be checked in parallel.

A ROM line 30 shown in FIG. 4 can additionally be used during operational interruptions to check the pre-charge line for the memory matrix 10 , the sense amplifier 13 , the read signals and the non-activity of the write signals. In the exemplary embodiment, only a single ROM line 30 is shown, which consists of four FET transistors 31 , which line 32 can be controlled via a common control. Of the six column lines shown, three - via three of the FET transistors 31 - can be connected to ground, while the fourth FET transistor 31 enables the sensor line 21 to be connected to ground. The p-column lines (six of which are shown) are precharged to the potential Vdd by a precharging device 33 . Three of the column lines are pulled down to the potential Vss by a signal on the control line 32 . As a result, a different data word is activated by this ROM line 30 in each column in order to test the correct activation of the column decoder and the correct function of the sense amplifier and the output stages. Of course, several such ROM lines with different coding can also be provided, the data words given by these ROM lines not necessarily having to be code words in the event that the data are stored coded in the memory. In addition to the individual check of a column, there is the possibility of reading out all the ROM data words one after the other in a fixed sequence and comparing a signature formed above with a stored target signature. This takes place in the signature checker 14 shown in FIG. 1.

In the normal case, the Vdd and Vss supply lines in the memory matrix 10 are routed parallel to the bit lines (columns). Design measures and the bit assignment of the matrix ensure that the same supply lines are not used for several bits of the same data word. This decoupling is to be continued consistently up to the output stages of the memory arrangement. Common mode errors due to influences of the supply voltage lines in the matrix are thereby avoided. A column-by-column supply is assumed and the column decoder 12 selects the data bits for each bit location in the same order.

Should supply lines be routed parallel to the word lines in the special case, the possibility arises of testing by the circuit shown in FIG. 5. This largely corresponds to the circuit shown in FIG. 2, the same or equivalent components being provided with the same reference numerals and not being described again. A modified 1-out-of-n tester 17 'is obtained. In contrast to FIG. 2, two Vss lines and two Vdd lines are now routed parallel to word lines i and j (of course also to the other word lines, not shown). A Vss line is also led to the test device 28 . Each Vdd line is connected via the series connection of the switching paths of two FET transistors 34 , 35 and 36 , 37 to the sensor line 21 . The FET transistors 34 , 36 are controlled by the word lines i and j and the FET transistors 35 , 37 are controlled jointly by a control line 38 .

In addition to checking the word lines according to FIG. 2, the Vdd or Vss lines can also be checked here. The Vss lines are also checked up to a branching point when the test device 28 is activated after the correct word selection. This is done when testing transistors 24 and 25 . If the branch point is at the beginning of the memory matrix 10 , the entire line is also checked for an interruption in the Vss or ground line. For the word line with the address "1111 ... 1" there is no transistor on the ground line, so that this can also be tested by connection to the ground connection of the test device 28 , that is to the ground connection of the tristate drivers. In addition, the Vdd lines can also be tested. For this purpose, the control line 38 is activated in each case after the Vss test (discharged sensor line 21 ) in the case of high-resistance tristate drivers 29 of the test device 28 and the recharging of the sensor line 21 via the transistors 34 , 35 or 33 , 37 (depending on whether the Word line i or j is activated) checked.

The basis for the previous review of the storage arrangement or the word lines and column lines is the assumption that one or more word lines or column lines are additionally activated by an error in the row or column decoder 11, 12 . Errors that are based on an incorrectly created address and on an exchange of word lines / column lines caused by a single defect are therefore not recognizable. To detect such errors, the input address z. B. coded by a parity bit, this code being checked by a code checker, which may be included in the decoder, for example. In addition, certain geometrical precautions should be taken to prevent the negated and the non-negated value of an address bit from changing due to a single error without the address code checker noticing this change. This is achieved by the arrangement shown in FIG. 6.

For the sake of simplicity, only a single address line Ai is shown, which forms the address line Ai via the input inverter 43 and which, together with other address lines, not shown, is led to a code checker 39 in order to check the coding of the input address. In this way it can be recognized whether the address created is incorrect. An unguided line 40 and a line 42 negated by means of an inverter 41 branch off from this address line Ai. These lines then branch out again in a known manner and run to the gates of the row or column decoder 11 , 12 . The unguided line 40 and the line to the inverter 41 are kept at such a large distance from one another that no (point) defect can influence them together in such a way that both can assume a different potential than the line to the decoder 39 , or that this is at least unlikely. Star-shaped branches are excluded, that is, these two lines 40 , 42 are branched off from different spaced locations of the address line Ai.

The inverters 41 and 43 and the gates, not shown, on the branched lines 40 and 42 and the code checker 39 are dimensioned such that (for example, in the event of a short circuit between lines 40 and 42 ) all the gates which are not shown are connected to these lines 40 and 42 and the code checker 39 recognize the same logic level if exactly one input signal is not at high (Vdd) or low (Vss) potential. The gates (not shown) connected to the lines 40 and 42 and the code checker 39 and the inverters 41 and 43 are implemented, for example, in a conventional static circuit technology with complementary FET transistors according to FIG. 10 (MOS technology). In this technique, the P-channel branch 45 switches a current between the upper potential Vdd and the output 48 if the relevant inputs - only one input 47 shown here - are at a low potential (Vss). In contrast, the N-channel branch 46 conducts a current between the output 48 and the low potential (Vss) if the relevant inputs — shown here as input 47 — have a high potential (Vdd).

Are all of the lines 40 and 42 directly connected gates, ie the gates not shown and the gates in the code checker, for. B. realized so that only a single path in the N-channel branch 46 from the output 48 to the low potential Vss exists and this path is dimensioned by the size of the transistors so that more current flows when the output 48 is reloaded from the high potential Vdd than when reloading the output 48 from the low potential Vss through exactly any path in the P-channel branch 45 with a different input condition 47 , the condition must apply to the inverters 41 and 43 that the transistors in the P-channel branch 45th at the start of the discharge of the output 48 from the low potential Vss supply more current than the transistors in the N-channel branch 46 at the start of the discharge of the output 48 from the high potential Vdd. This condition is to be realized in the same way for all inverters 41 and 43 for all address bits Ai, as well as for all gates (not shown) on lines 40 and 42 and the code checker 39 for all address bits Ai the same dimensioning rule must apply.

The arrangement shown in Fig. 6 ensures that a point defect generally only a line can be cut or short-circuited in the manner described, so that due to this error more than one word line or no word line is activated, which in turn the 1-out-of-p inspector 17 , 17 'can be recognized.

Due to the arrangement shown in Fig. 7, short circuits between the lines can be detected even more reliably. Both inverters 41 , 43 are connected to a current sensor 44 . If there is now a short circuit between a negated line 42 and an unregulated line 40 , the current sensor 44 detects an increased current draw by the inverters 41 , 43 , since these then work against one another on the output side. This determined increased current value then leads to an error message. The current sensor can be assigned to the line to the upper potential (Vdd) or to the lower potential (Vss).

In Fig. 8, another alternative geometric layout is shown. Here, the inverter 41 is connected to the address line Ai, namely between a plurality of branches of unregulated lines 40 and a plurality of branches of negated lines 42 . Both the ne gated lines 42 and the non-alloyed lines 40 are spaced apart and each have their own branch points from the address line Ai, which are also spaced apart. The gates (not shown) connected to lines 40 and 42 and the directly connected gates of code checker 39 on the one hand and inverters 41 and 43 on the other hand are dimensioned for all address lines Ai, as described in the circuit of FIG. 6. Assuming individual defects of limited size, if these geometric rules are observed, either a word line / column line is additionally active, the address of which differs by exactly 1 bit from the desired address, or no word line / column line becomes active at all. Both are recognized by the 1-out-of-n tester 17 , 17 'and 1-out-of-p tester 18 . Since adjacent word lines / column lines can only be activated in terms of address, a simpler neighboring tester can also be used instead of a 1-out-of-n tester, as described in the prior art "Error Detecting Codes" mentioned at the beginning. Interruptions in the word line or the precharge line are also recognized. The neighboring tester not only requires less circuitry effort than the 1-out-of-n tester, but also a significantly reduced test effort for the power-on-test, in which the initial absence of errors must be verified.

In Fig. 9 the corresponding circuit with the current sensor 44 , similar to that in Fig. 7, is shown.

The self-test device described requires at Codie with a parity bit is just an additional one Total chip area expenditure of approx. 15%. Of that account for the coding (8-bit data word and a Parity bit) 12.5% for the 1-out-of-n checker at four KB RAM with 256 rows and 128 columns (+ 16 columns parity Bits, + 8 columns controller ROM), with a row Area ratio RAM: ROM = 10 additionally approx. 0.6%.  

In addition, there are test hardware and controls in addition approx. 1%, and the effort for the column checker, the row ROM, the additional hardware and control total about 0.8%. In contrast, using two Code bits already mean an extra effort of 25% where with the fault coverage without the additionally described measures according to the invention would be much worse.

It should also be noted that the described Self-test facility of course also for the ver Various storage arrangements can be used, such as. B. Read / write memory (RAM) and read-only memory (ROM, EPROM and Like.). Furthermore, this self-test facility can also be used alone for decoders.

Claims (18)

1. Self-test device for memory arrangements, decoders or the like. For use in online operation, means for checking a multiplicity of word lines and / or column lines being provided, characterized in that the word lines and / or column lines have a test matrix ( 17 , 18 ) are connected, and that an error detector ( 27 ) which generates an error signal when more than one line is activated is connected to the test matrix ( 17 , 18 ). 2. Self-test device according to claim 1, characterized in that each word line and / or column line in the test matrix ( 17 , 18 ) is in each case connected to control connections of z switches ( 23-26 ) of a switch matrix, through which z has a first potential ( Vdd) acted upon test lines ( 20 ) according to the coding of the respective word line and / or column line can either be connected to connections having a second potential (Vss) or to a sensor line ( 21 ) which is also acted upon by the first potential (Vdd), wherein the error detector ( 27 ) is connected to the sensor line ( 21 ) and is designed as a current or voltage sensor. 3. Self-test device according to claim 2, characterized in that the switches ( 23-26 ) of the switch matrix are designed as FET transistors. 4. Self-test device according to claim 2 or 3, characterized characterized in that the second potential (Vss) pointing connections are designed as ground connections. 5. Self-test device according to one of claims 2 to 4, characterized in that a test device ( 28 ) with the test matrix ( 17 , 18 ) for checking the function of the switch ( 23-26 ) of the switch matrix is connected. 6. Self-test device according to claim 5, characterized in that all switches ( 23-26 ) are checked sequentially. 7. Self-test device according to claim 5 or 6, characterized in that the test lines ( 20 ) in the test device ( 28 ) are connected to tristate drivers ( 29 ), through which in each case the switch ( 23-) to be checked and controlled for this purpose 26 ) connected test line ( 20 ) can either be connected to the second potential (Vss) or connected to the sensor line ( 21 ) according to the switch coding. 8. Self-test device according to one of claims 2 to 7, characterized in that means for checking arranged parallel to the word lines Supply lines are provided that the first (Vdd) and / or the second potential (Vss). 9. Self-test device according to claim 8, characterized in that additional switches ( 34-37 ) for the controllable connection of the first potential (Vdd) leading United supply lines with the sensor line ( 21 ) are provided, and that these switches ( 34-37 ) can be controlled by the word lines / column lines and / or by an additional control line ( 38 ). 10. Self-test device for memory arrangements according to one of the preceding claims, characterized in that a test matrix ( 17 ) for the row lines (word lines) and / or a test matrix ( 18 ) for the column lines of the memory matrix ( 10 ) of the memory arrangement are provided . 11. Self-test device according to claim 10, characterized in that at least one ROM line ( 30 ) for checking a precharge line of the memory arrangement, the sense amplifier ( 13 ) and the read signals during interruptions (test mode) is provided, with switches ( 31 ) of the ROM line ( 30 ) are activated in the columns of fixed data words which can be read out and checked. 12. Self-test device according to claim 10 or 11, there characterized in that the memory arrangement as Read / write memory (RAM) or as read-only memory (ROM) is formed. 13. Self-test device for memory arrangements, decoders or the like. For use in online operation, means for checking a plurality of word lines and / or decoder lines being provided, in particular according to one of the preceding claims, characterized in that the input addresses are encoded and for checking a code checker ( 39 ) are provided, and that the non-ignoring (40) branching off from the individual address lines (Ai) and the branching-off lines ( 42 ) negated by an inverter ( 41 ) are realized spaced apart from one another without common branching points that the Word lines are connected to a test matrix ( 17 , 18 ) and that an error detector generating an error signal is connected to the test matrix ( 17 , 18 ) when more than one word line is activated or at the same time two active addresses are assigned to two adjacent addresses. 14. Self-test device according to claim 13, characterized in that each address line also has an inverter ( 43 ) on the input side, and that both inverters ( 41 , 43 ) are connected to a current monitoring device ( 44 ). 15. Self-test device according to claim 13 or 14, characterized in that from each address line (Ai) initially spaced apart from one another and without common branching points branch off the non-ferrous lines ( 40 ) that the inverter ( 41 ) for the negated branching lines ( 42 ) is connected into the address line (Ai) and that the negated lines ( 42 ) branch off from the negated region of the address line (Ai) at a distance from one another and without common branch points. 16. Self-test device according to claim 12, characterized in that memory cells which are used to store different bits of a memory word are connected to different supply lines (Vdd and Vss) within the memory matrix ( 10 ) and that these supply lines only outside the memory matrix ( 10 ) are electrically connected to each other. 17. Self-test device according to claim 16, characterized in that the interruption of individual supply lines (Vdd and Vss) within the memory matrix ( 10 ) is detected by coding the data word. 18. Self-test device according to one of claims 13 to 15, characterized in that by a dimensioning regulation of all inverters ( 41 , 43 ) and all un directly to the lines ( 40 and 42 ) connected decoder gate and the code checker ( 39 ) bits for all addresses (Ai) Short circuits between any two lines ( 40 and 42 ) either in the code checker ( 39 ) or in the test matrix ( 17 , 18 ) can be detected.