DE4306464A1 - High voltage bipolar transistor - comprises high resistance collector layer formed on low resistance collector layer - Google Patents

Abstract

Bipolar transistor (I) comprises (a) a collector layer of low resitance; (b) a collector layer of high resistance, formed on the collector layer (a), whose resistance is higher than the resistance of (a); (c) a base region formed on (b); and (d) an emitter region formed on (c). Ratio (p/t) of resistance (p) (ohm.cm) of the layer (b) to film thickness (t) (microns) of (b) is 0.6 or lower. Also claimed are: (i) prodn. of (I); (ii) a Darlington transistor (II); and (iii) prodn. of (II). ADVANTAGE - High voltage characteristics are improved.

Description

The present invention relates to an improvement a comprehensive electrical characteristic including a high voltage characteristic and a low voltage characteristic in a high-voltage power darling ton transistor.

The invention also relates to extensive techno logic to improve a high voltage characteristic both a high voltage power transistor and egg Darlington transistor.

1. Arrangement of a Darlington transistor

Fig. 44 is a circuit diagram showing a configuration of a power transistor connected in a two-stage Dar lington circuit (Darlington transistor) connected angeord net. As shown in Fig. 44, the Darington transistor consists of two stages; the emitter of a bipolar transistor Q1 of the first stage is connected to a base of a bipolar transistor Q2 of a second stage, and the respective collectors of the transistors Q1 and Q2 are connected together. Resistors R1 and R2 are provided between emitters and bases of transistors Q1 and Q2, respectively.

Fig. 45 is a sectional view showing a configuration of the two-stage Darlington transistor. As shown in FIG. 45, a high resistance collector layer 11 is formed on a low resistance collector layer 12 . A base region 21 is formed in a region A1 in an upper part of the high resistance collector layer 11 , while a base region 22 is formed in a region A2 in the same part, and emitter regions 31 and 32 are selective in surfaces of the base regions 21 and 22 , respectively educated. A collector electrode 5 is formed on a surface of the low resistance collector layer 12 , a base electrode 6 is formed on the base region 21 of the transistor Q1, an emitter electrode 7 is formed on the emitter region 32 of the transistor Q2, and a base-emitter connection electrode 8 formed from the emitter region 31 of the transistor Q1 to the base region 22 of the transistor Q2. Reference numerals 4 , 18 and 19 each denote an oxide film, a protective ring and a channel stop.

Throughout this description, a resistance of the collector layer with high resistance 11 is referred to as "collector resistance ρN⁻", while a thickness of the collector layer with high resistance directly below the base regions 21 and 22 is referred to as "collector thickness tN⁻".

2. Available upper limit voltage of the transistor

The following is an assessment of an available top Limit voltage described in such a transistor.

Transistors have different types of rated voltage, each yet there is no accepted theory that can explain it all types of available Tran upper limit voltages sistors supplies. For the time being in larger De To explain tail, definitions are first different Types of nominal transistor voltages described.  

2-1. Nominal transistor voltage

The sizes that the nominal voltage of a transistor be writing include the following:

(1) BV _CBO

The characteristic quantity BV _CBO represents the voltage at which breakdown current begins to flow when the voltage between the collector and the base is slowly increased, with the emitter open. The breakdown current to be considered is approximately 0.1 mA for a power transistor. The size is referred to in this specification as "emitter opening breakdown voltage".

(2) BV _CEO

The BV _CEO characteristic is the voltage at which a breakdown current begins to flow when the voltage between the collector and the emitter slowly increases, with the base open. The breakdown current to be considered is approx. 10 mA for a power transistor. The size is referred to as "base opening breakdown voltage" in this description.

(3) V _CEO (SUS)

A voltage value in a state where a large amount of current flows and voltage is maintained is called a "holding voltage". There are two types of holding voltage, namely V _CEO (SUS) and V _CEX (SUS).

The withstand voltage V _CEO (SUS) is the emitter-collector voltage measured in a state in which no base current flows in the reverse direction IB2 of a transistor T1, but only base current in the forward direction IB1 in a circuit shown in FIG. 46 flows. The size is referred to in this description as "withstand voltage of the first type".

The question of how the measurement results of the withstand voltage of the first type V _CEO (SUS) should be interpreted often gives rise to confusion. The reason for this is explained below:

With many power transistors, a resistor is common Lich parallel between their bases and emitters. The main reason for this is that a front stage of one in Darlington connected transistor during their OFF time between the base and the emitter in Is biased in the reverse direction. Furthermore, the Ef expected to be stable operation in exchange for rapid voltage changes between the collector and emitter is enough. This refers to the fact that such a Voltage change causes a current to flow through a Capacitor between the collector and the base to the emitter to flow, which essentially means the same thing that the Current flows from the base to the emitter. In other words can divert the equivalent current from base to Emitter due to the unstable operation of the Transi Prevent stors when there is a resistor in parallel between the Base and the emitter is created.

For this reason, resistance is paral in many cases lel connected between the base and the emitter, and the resistance between the base and the emitter allows even flow of the mainly weak base currents in the reverse direction IB2, even if the external Ba Sisstrom in the reverse direction IB2 is zero. The reason this is because the emitter of the front stage transi stors during the ON time of the transistor at an endli potential is at a certain level and there  through it is possible that a current from the emitter through the Wi the flow to the base.

Therefore, a measured value of the holding voltage of the first type V _CEO (SUS) under low voltage can vary in the large wet rod, depending on the resistance value. The result of the measuring conditions is that the measured value of the holding voltage of the first type has a variation. However, such an influence is relatively reduced as soon as the measured current becomes larger.

A typical holding voltage of the first type V _CEO (SUS) is a value in the case when there is no resistance between the base and the emitter. In this case, the measured value of the holding voltage of the first type V _CEO (SUS) under constant current is theoretically equal to the basic opening breakdown voltage BV _CEO .

In contrast to the measurement of a holding voltage of the second type V _CEX (SUS) mentioned below, it has been shown experimentally that the measurement of the holding voltage of the first type V _CEO (SUS) can be carried out relatively safely with a low breakdown risk.

(4) V _CEX (SUS)

On the other hand, the holding voltage V _CEX (SUS) is measured by passing the base current in the reverse direction IB2 shown in FIG. 47 into the circuit shown in FIG. 46 after the base current is conducted in the forward direction IB1. Although V _CC in Fig. 47 is a low voltage of about 10 V up to several tens of volts, a high voltage is applied to a measured transistor, and a current flows that is almost the same as that flowing during its ON time because changing the load current causes the inductance of a load to induce an opposite electromotive force as soon as the transistor starts to turn off. If no terminal circuit is included in the measured transistor, the voltage across opposite terminals of the measured transistor increases up to a voltage holding capacity of the transistor. In the present description, this quantity is referred to as "holding voltage of the second type". The measurement of the _withstand voltage of the second type V _CEX (SUS) is an extremely precise test that would lead to the breakdown of most of the measured transistors if carried out simply. It is therefore a common practice to connect a capacitive power source, for which a lower voltage than the withstand voltage of the measured transistor is specified, and a diode connected in series therewith in parallel between the collector and the emitter, so that none above that at the power source predetermined voltage voltage is applied to the measured transistor.

2-2. Ways the voltage carrying capacity of transistors to represent

Although the "base opening breakdown voltage BV _CEO " or the "withstand voltage of the first type V _CEO (SUS)" were widely used as ways to indicate the voltage carrying capacity of transistors, there has been a tendency in recent years to use the "withstand voltage of the second type V _CEX (SUS) "because to replace. It is clear that the performance of existing products has become higher than the range defined by the conventional basic opening breakdown voltage BV _CEO or the holding voltage of the first type V _CEO (SUS), but there has been no recognized theoretical support for this. (Likewise, there is no accepted support for the theory that the base breakdown voltage BV _CEO or the withstand voltage of the first type V _CEO (SUS) is a limit for transistors.

2-3. Endurance unit of breakdown

The measured current of the conventional holding voltage V _CEX (SUS) or V _CEO (SUS) is in most cases independent of the nominal current in the measured transistor about 1 A, and such a value cannot guarantee the available upper limit voltage of the transistor. This is because the measurement of the _withstand voltage V _CEX (SUS) or V _CEO (SUS) is performed as a kind of property of the skill voltage, and the conventional nominal voltage in transistors leaves a concept of the "breakdown limit", which in situations, in that a coarse current flows, a guarantee for the operating voltage, completely miss.

2-4. Safe operating zone

The operating voltage in the situation in which a large current flows is shown in the drawing of a safe operating zone, which has nothing to do with a nominal voltage rating. The safe operating zone ( Fig. 48 illustrates the safe operating zone) is defined by an envelope which relates to current-voltage conditions under which the device is actually destroyed when measuring the circuit of Fig. 46, provided that a Load inductance and supply voltage (VCC) are determined so that a coarse current can fly. A vertical boundary line on the high voltage side and a horizontal boundary line on the high current side are not based on actual measurement of a breakdown. The upper limit on the high voltage side is set at the nominal voltage RV. The upper limit on the high current side is set at a value that is approximately twice the nominal current RC. Neither relates to the actual performance of a transistor, but the manufacturer guarantees a guaranteed zone for safe operation.

With transistors there is the unclear problem of the secondary Breakthrough, and therefore transistors were not for a long time suitable for general high-voltage operation. The safe one Operating zone was named not so long ago. (Even in the current phase, the safe operation zone not as nominal value, but rather as typical information Back then it was hard to imagine that Transisto ren as the main elements for an inverter in an Im would use pulse width modulation. You started however, transistors suitable for such an inverter are to be manufactured as general purpose products, and her short-circuit fatigue limit started serious in 1983 to prepare.

Strictly speaking, the "safe operating zone" is a "safe one" Operating zone of the reverse bias "what re Levant is for a breakthrough that occurs during the OFF time of a transistor is caused, which a switching operation. This will happen in nearby conditions the highest possible voltage and the highest possible nominal current measured.

Furthermore, the "safe operating zone" includes a "safe Forward Voltage Operating Zone ". This refers to a restriction of an operating zone, which is limited by local Temperature rise during the ON time of a transistor is caused and under conditions of approximate mean Voltage and mean current (e.g. measured under conditions between 10 and 100 V and a few A for a transistor with a practical application voltage of 200 V).  

2-5. Breakthrough fatigue limit due to short circuit

A breakthrough fatigue limit was relatively recently of the breakthrough widely known, not with the concept of "safe operating zone" can be expressed. Here it goes it is a "breakthrough fatigue limit by short "The breakthrough fatigue limit due to short circuit is a kind of fatigue limit under forward tension, under differs from the conventionally preferred "safe Forward tension operating zone "in tension and Current zones.

In particular, when a load short circuit occurs, a current four to six times the nominal current flees while a high voltage is applied that is approximately 80% of the withstand voltage of the first type of V _CEO (SUS) nominal value. An operating zone in this case is far superior to a conventional safe zone.

2-6. Conclusion on current understanding of the transistor breakdown phenomenon

As has been described, one can get a very rough lot see fold of phases of transistor breakdown. Currently is a state particularly in the neighborhood of the Span The threshold of the safe operating zone is still unknown.

Such an unclear situation can be proven by the fact that the essence of the phenomenon of through break of a high voltage high current area in a tran sistor has not yet been understood, being manufacturer and users just treat this as a phenomenon.

After all, the current state should ver as a state "empirical measurement is the al no reliable criterion ".  

2-7. Example in the case of transistors for a 220V AC line

At the moment, the "600 V" of a "600 V transistor" for a 220 V AC line represent a guaranteed value of the holding voltage of the second type V _CEX (SUS). When this product became commercially available several years ago, it had a 450 V guarantee on the withstand voltage of the first type V _CEO (SUS) and was called "450 V transistor". For use under 220 VAC supply voltage, a transistor is required which can withstand approximately 450 V voltage including increased voltage in rectification, surge, and a change in supply voltage, but at those times or earlier, the upper one was Operating voltage limit of transistors with the base opening breakdown voltage BV _CEO or the holding voltage of the first type V _CEO (SUS).

With the currently available transistors with 220 V AC line there is basically no problem and it seems that they have a long enough history of have practical use (more than ten years).

With 600 V transistors used for 220 V AC lines, it has been shown in the past that they have a sufficient breakdown limit with a collector film thickness tN⁻ up to 60 µm. In order to meet the nominal voltage rating of the first type V _CEO (SUS), the collector resistance ρN⁻ must be approximately 40 Ωcm or more, including manufacturing tolerances, using 40 to 60 Ωcm.

3. Transistors for higher voltage 3-1. Procedure for the determination of ρN⁻ and tN⁻

The following describes how to design a Higher voltage transistor based on the expe riments on the transistors for 220 V AC line the most significant collector resistance ρN⁻ and collector gate film thickness tN⁻ can be determined.

In the manufacture of a power transistor that is designed for the Use under high voltage turns out not just a static tensile stress property, but also a breakthrough limit as an obstacle. It is empirically well known that the breakthrough limit mei depends on the collector film thickness tN⁻, and that one Thickness is required, which is in proportion to that using voltage.

Fig. 49 shows a distribution of the electric field strength of the high resistance layer (the high resistance collector layer 11 in Fig. 45) at a point where the breakdown of a 220V AC line transistor and that of a double voltage transistor begins . A region 11 shows an electric field strength of the transistor for 220 V AC line, while a region I shows a voltage increase. An absolute value of an inclination of the electric field is in inversely proportional relationship to the collector resistance ρN⁻.

Although the collector film thickness tN⁻ must be doubled with regard to the breakdown limit, this is not sufficient to double the static strength stress (integrated value of the electric field strength). In other words, as can be seen in FIG. 49, the collector resistance must be doubled so that the integrated value of the electric field strength doubles.

In this way, transistors have traditionally been successful to make it suitable for use under high voltage, by basically t Kolle the collector film thickness and the Ver collector resistance ρN⁻ in relation to each other largest.

As a result, the transistor, which is for a 220th V-AC voltage line was used, with t⁻ from unge made about 60 µm and ρN⁻ from about 40 to 60 Ωcm was while the transistor, which is for a 440 V change power line was used, with tN⁻ of approximately 120 µm and ρN⁻ of approximately 80 to 120 Ωcm was produced.

In the Tran designed for high voltage as mentioned above sistor (i.e. the transistor for 440 V AC voltage However, a random breakthrough always occurs even more frequently than that with which he is in the transistor for 220 V AC line occurs. Although it must be expected that a voltage application rose itself caused some difficulties, but remains the possibility that the transistor for 440 V AC line is not yet optimized and that it is desirable is to improve it.

Accordingly, it is an object of the present invention Formulate principle, creating an available upper limit voltage of transistors is explained, and according to this Principle the high voltage property of a high chip Power transistor to improve.

It is a further object of the present invention to provide a comprehensive electrical property, including one High voltage property and a low voltage property shaft in a high voltage power Darlington transistor to improve.  

According to the present invention, a bipolar transistor on: a low resistance collector layer; a High resistance collector layer on the collector Gate layer is formed with low resistance and their Resistance is set higher than a resistance of the Kol low resistance detector layer; a basic area that in a surface of the collector layer with high Wi the status is formed; and an emitter region that is in egg a surface of the base portion is formed; thereby characterized in that a ratio ρ / t of a resistance ρ (Ωcm) of the collector layer with high resistance to one Film thickness t (µm) of the collector layer with high resistance just below the base area 0.6 or less wearing.

The bipolar transistor preferably also has one base electrode formed on the base region; and a emitter electrode formed on the emitter region.

The present invention also relates to a dar Lington transistor comprising: one on a first Semiconductor substrate formed first bipolar transistor; and one formed on a second semiconductor substrate th bipolar transistor; the first and second bipolar transistor are connected in a Darlington circuit and a front stage of the first bipolar transistor and one Have the second stage of the second bipolar transistor; the he bipolar transistor a first collector layer with low resistance, one on the first collector layer formed with low resistance first collector layer with high resistance, whose resistance turned higher is a resistance of the first collector layer with low resistance, one in a surface of it most collector layer formed with high resistance first Base area, and one in a surface of the first Ba first emitter region formed; the second  Bipolar transistor a second low collector layer Resistance includes, one on the second collector layer low resistance formed second collector layer high resistance whose resistance is set higher than a resistance of the second low collector layer Resistance, one in a surface of the second collector layer formed with high resistance second Basisbe rich, and one in one surface of the second collector layer formed with high resistance second Basisbe rich, and one in a surface of the second base richly formed second emitter region; thereby ge indicates that a resistance of the first collector layer with a high resistance is set higher than a counter was the second collector layer with high resistance.

A film thickness of the first collector layer is preferred with high resistance just below the first Base area set smaller than a film thickness of second collector layer with high resistance immediately below the second base area.

Preferably, first to Mth (an integer equal to 2 or larger) transistors connected in Darlington connection, with a transistor of the m-th stage (1 m <M) as the front stage transistor is provided; and a transistor the (m + 1) -th stage is provided as a step-down transistor.

Preferably M = 2 and m = 1; the resistance of one Be the first stage transistor of the front stage transistor carries 110 Ωcm and the film thickness 110 µm; and the resistance a transistor of the second stage of the reverse stage transi stors is 45 Ωcm and the film thickness is 160 µm.

Preferably N = 3 and m = 1; the resistance of one Be the first stage transistor of the front stage transistor carries 120 Ωcm and the film thickness 80 µm; and the resistance  a transistor of the second stage of the reverse stage transi stors is 45 Ωcm and the film thickness is 140 µm.

Preferably M = 4 and m = 3; the resistance of one Third stage transistor of the front stage transistor is 120 Ωcm and the film thickness is 80 µm; and the resistance a transistor of the fourth stage of the reverse stage transi stors is 45 Ωcm and the film thickness is 140 µm.

Preferably M = 4 and in = 2; the resistance of one Second stage transistor of the front stage transistor is 120 Ωcm and the film thickness is 80 µm; and the resistance a transistor of the third stage of the reverse stage transi stors is 45 Ωcm and the film thickness is 140 µm.

Preferably M = 4 and m = 1; the resistance of one Be the first stage transistor of the front stage transistor carries 120 Ωcm and the film thickness 80 µm; and the resistance a transistor of the second stage of the reverse stage transi stors is 45 Ωcm and the film thickness is 140 µm.

The present invention also relates to a method ren for the production of a bipolar transistor, which a first step to form a collector layer with high Resistance on a low resistance collector layer stood to set its resistance higher than a low resistance resistance of the collector layer was standing; a second step to form a base area in a surface of the collector layer with high resistance was standing; and a third step to form an emitter area in a surface of the base area; thereby ge indicates that a ratio ρ / t of a resistor r (cm) of the high resistance collector layer immediately below the base range is 0.6 or less.  

A method for producing a bi Polar transistor continues to follow the third Step a fourth step to form a base electrode trode on the base area; and a fifth step to Formation of an emitter electrode on the emitter area.

The first step preferably has the steps on the Manufacture of a single crystalline silicon rod; Radiation of the single crystalline silicon rod with neutrons in order to monocrystalline silicon rod an area with high resistance stood to form; Cutting the single-crystal silicon rod into a semiconductor substrate separated from the high wi the status is formed; Introduction of an impurity in the front and back surfaces of the semiconductor substrate, around a low resistance area in the front and Form the rear surface of the semiconductor substrate; and Cutting the ge in the surface of the semiconductor substrate formed low resistance area around the im Semiconductor substrate remaining area with high resistance was defined as a collector layer with high resistance ren, and around in the back surface of the semiconductor sub strats formed area with low resistance as Kol to define the low resistance detector layer.

Preferably the first step comprises the steps of position of a semiconductor substrate that consists of an area is formed with low resistance; and forming one Layer that consists of a high resistance area on the Semiconductor substrate formed by epitaxial growth is to the semiconductor substrate except for the layer mentioned to defi as the low resistance collector layer kidneys and the layer as the collector layer with high Define resistance.

Preferably the second step comprises the steps of Bil formation of an oxide film on a surface of the collector  high resistance layer; Structuring of the oxide film; and diffusing contamination of a given one Conductivity type to a certain depth in the High resistance collector layer in an oxidizing Atmosphere to form the base area.

Preferably the third step comprises the steps of Bil formation of an oxide film on a surface of the collector high resistance layer; Structuring of the oxide film; and diffusing a contamination of a conductivity type, which is different from that of the pre given to a certain depth in the collector layer with high resistance in an oxidizing atmosphere sphere to form the emitter area.

The present invention is also intended for a ver drive to manufacture a Darlington transistor, which comprises the steps of forming a first bipolar transistor stors in a first semiconductor substrate; to form a second bipolar transistor in a second semiconductor sub strat; and the arrangement of the first and second bipolar trans sistors in Darlington circuit, with a front stage of the first bipolar transistor and a return stage of the second Bipolar transistor; the step to form the first bipo lartransistors including the steps to form a first collector layer with high resistance on one he most collector layer with low resistance to their Wi the level higher than a resistance of the first Low resistance collector layer; Formation of a he most base area in a surface of the first collector high resistance layer; and formation of a first emit ter area in one side of the first base area; the Step to form the second bipolar transistor finally the steps to create a second college High resistance gate layer on a second col low resistance detector layer to increase their resistance  higher than a resistance of the second collector low resistance gate layer; Formation of a second Base area in a surface of the second collector high resistance layer; and forming a second Emitter region in a surface of the second base area empire; characterized in that a resistance of he most collector layer with high resistance set higher is as a resistance of the second collector layer with ho hem resistance.

A film thickness of the first collector layer is preferred with high resistance just below the first Base area less than a film thickness of the first High resistance collector layer immediately below of the second base area. According to the present invention keep the bipolar transistor according to claim 1 and the Bipo produced in a process according to claim 4 lartransistor the ratio ρ / t of the resistance ρ (Ωcm) the high resistance collector layer to the film thickness t (µm) of the high resistance collector layer immediately below the base range at 0.6 or less, and the the high-voltage property can be increased by half.

The Darlington transistor according to claim 2 and in a method produced according to claim 5 darling ton transistor have a resistance of the first collector layer with high resistance of the front stage bipolar transistor stors, which is higher than that of the second collector layer with high resistance of the regression bipolar transistor stors, and therefore it is possible to have a good breakthrough limit in a high voltage range without a fatigue limit against short circuit deteriorates.

In addition, the Darlington transistor according to Pa claim 3 and in a process according to Pa Claim 6 manufactured Darlington transistor a ge  thinner film thickness of the first collector layer with high Wi the level immediately below the first base area of the Front stage bipolar transistor than that of the second High resistance collector layer immediately below the second base region of the backstage bipolar transistor, and therefore the low voltage property (Saturation voltage) can be improved.

These and other features, aspects and advantages of this ing invention are explained in more detail in the following de waisted description of the present invention in ver binding with the associated drawings.

It shows:

Fig. 1 is a graph showing results of measuring a reverse voltage breakdown fatigue limit at which the base current is changed in the reverse direction;

Fig. 2 is a graph showing the internal electric field when a high voltage is applied between a collector and an emitter of an NPN transistor;

Fig. 3 is a circuit diagram showing an arrangement of a circuit for a short circuit breakdown test;

Fig. 4 is a waveform diagram showing a base current applied to a transistor shown in Fig. 3;

Fig. 5 is a graph showing the phenomenon of short-circuit breakdown in a transistor;

Fig. 6 is a graph showing the phenomenon of a short-circuit breakdown in a Darlington transistor;

Fig. 7 is a graph showing changes in breakdown voltage and breakdown current in an NPN transistor;

Fig. 8 is a sectional view showing an arrangement of a three-stage Darlington transistor of a first preferred embodiment of the present invention;

Fig. 9 is a plan view showing the Darlington transistor of the first preferred embodiment installed in a single package;

FIG. 10 is a graph of a measurement of a load limit Kurzschlußermü a Darlington transistor;

FIG. 11 is a diagram showing a method of manufacturing of the Darlington transistor according to the first preferred guide die;

Fig. 12 is a diagram showing a method of manufacturing the Darlington transistor of the first preferred embodiment;

FIG. 13 is a sectional view, the position of a process for the preparation of the Darlington transistor of the first preferred embodiment;

FIG. 14 is a sectional view, the position of a process for the preparation of the Darlington transistor of the first preferred embodiment;

FIG. 15 is a sectional view, the position of a process for the preparation of the Darlington transistor of the first preferred embodiment;

Fig. 16 is a sectional view showing a method for the manufacture of the Darlington transistor of the first preferred embodiment;

FIG. 17 is a sectional view, the position of a process for the preparation of the Darlington transistor of the first preferred embodiment;

FIG. 18 is a sectional view, the position of a process for the preparation of the Darlington transistor of the first preferred embodiment;

FIG. 19 is a sectional view, the position of a process for the preparation of the Darlington transistor of the first preferred embodiment;

FIG. 20 is a sectional view, the position of a process for the preparation of the Darlington transistor of the first preferred embodiment;

Fig. 21 is a sectional view showing a method for the manufacture of the Darlington transistor of the first preferred embodiment;

FIG. 22 is a sectional view, the position of a process for the preparation of the Darlington transistor of the first preferred embodiment;

FIG. 23 is a sectional view, the position of a process for the preparation of the Darlington transistor of the first preferred embodiment;

FIG. 24 is a sectional view, the position of a process for the preparation of the Darlington transistor of the first preferred embodiment;

FIG. 25 is a sectional view, the position of a process for the preparation of the Darlington transistor of the first preferred embodiment;

FIG. 26 is a sectional view, the position of a process for the preparation shows the Darlington transistor of the first preferred embodiment;

Fig. 27 is a sectional view, the position of a process for the preparation of the Darlington transistor of the first preferred embodiment;

FIG. 28 is a sectional view, the position of a process for the preparation of the Darlington transistor of the first preferred embodiment;

FIG. 29 is a sectional view, the position of a process for the preparation of the Darlington transistor of the first preferred embodiment;

FIG. 30 is a sectional view, the position of a process for the preparation of the Darlington transistor of the first preferred embodiment;

FIG. 31 is a sectional view, the position of a process for the preparation of the Darlington transistor of the first preferred embodiment;

FIG. 32 is a sectional view, the position of a process for the preparation of the Darlington transistor of the first preferred embodiment;

FIG. 33 is a sectional view, the position of a process for the preparation of the Darlington transistor of the first preferred embodiment;

Fig. 34 is a sectional view, the position of a process for the preparation of the Darlington transistor of the first preferred embodiment;

FIG. 35 is a sectional view, the position of a process for the preparation of the Darlington transistor of the first preferred embodiment;

FIG. 36 is a sectional view, the position of a process for the preparation of the Darlington transistor of the first preferred embodiment;

FIG. 37 is a sectional view showing an arrangement of a two-stage Darlington transistor of a second Favor th embodiment;

Fig. 38 is a sectional view showing an arrangement of a three-stage Darlington transistor of a third preferred embodiment;

FIG. 39 is a sectional view showing an arrangement of a four-stage Darlington-transistor of a fourth Favor th embodiment;

FIG. 40 is a sectional view showing an arrangement of a four-stage Darlington transistor a fifth Favor th embodiment;

FIG. 41 is a sectional view showing an arrangement of a four-stage Darlington transistor a sixth Favor th embodiment;

Fig. 42 is a sectional view showing an arrangement of a three-stage Darlington transistor of a seventh preferred embodiment;

FIG. 43 is a sectional view showing an arrangement of a four-stage Darlington transistor to an eighth preferred embodiment;

Fig. 44 is a circuit diagram showing an arrangement of a two-stage Darlington transistor;

FIG. 45 is a sectional view showing an arrangement of a two-stage Darlington transistor;

Fig. 46 is a circuit diagram for explaining the withstand voltage;

Fig. 47 is a waveform diagram for explaining the holding voltage;

Fig. 48 operating zone is a graph for explaining a safe Be; and

Fig. 49 is a graph showing a distribution of electric field strength of a collector layer having a high resistance.

1. Basic theory of the preferred embodiment

Before exemplary arrangements of preferred embodiments According to the present invention, Tatsa chen observed by the inventor of the present invention and theories based on their foundations which are explained in relation to an NPN transistor.

These theories are roughly divided into two groups, or in terms divided into three groups.

Theory of a general bipolar transistor

With an NPN transistor must

ρN⁻ (Ωcm) <0.6 × tN⁻ (µm) (1)

be fulfilled in its order.

In particular, the above equation (1), if one Rate "r" as

r = ρN⁻ (Ωcm) / tN⁻ (µm) (2)

is defined as follows:

0 <r <0.6 (3)

Theory 2 Theory of a Darlington transistor Theory 2-1

"A collector resistance ρN⁻ of a front stage of a Transistor connected in Darlington circuit should be greater than a collector resistance ρN⁻ its Reverse stage. "

Theory 2-2

"With a transistor connected in Darlington circuit should the above theory 2-1 be satisfied, and too in addition, there should be a collector film thickness tN⁻ in one front level of the transistor can be smaller than a collector film thick tN⁻ in its back stage. "

2. Explanation of Theory 1 and Theory 2 2-1. Measurement results

Fig. 1 shows results of a measurement in which a breakthrough limit by reverse voltage, which was measured in the circuit shown in Fig. 46, was measured while changing the base current in the reverse direction, the bright circle a locus of a holding waveform of a sample with ρN⁻ = 45 Ωcm;
the black circle is a breakthrough point of the sample with ρN⁻ = 45 Ωcm;
the light triangle is a locus of a holding waveform of a sample with ρN⁻ = 80 Ωcm; and
the black triangle is a breakthrough point of the sample with ρN⁻ = 80 Ωcm.

With these resistors, a linear waveform that is closest to a low voltage side is a hold voltage of the first type V _CEO (SUS). The collector film thickness t⁻ of both samples is about 140 µm. From the results of their measurement it follows that:
"Amplification of the base current in the reverse direction IB2 causes the holding waveform to bend backwards and also to move to a high voltage side."

A breakdown point of a relatively low voltage, which is represented by the dashed line inclined downward to the right, is caused by the so-called reverse current breakdown. The breakdown point represented by the horizontal chain line is a point at which the breakdown occurs while a current value that follows the sustain waveform is amplified. There have been almost no reports of the nature of the latter breakthrough point. However, it can only be seen by looking at FIG. 1 that a constant value is shown as a function of a resistance. The inventor of the present invention knew empirically that the breakdown in this mode is determined only by the resistance.

2-2. Theoretical explanation of the relationship between Breakthrough limit and ρN⁻

The following explains the relationship between the Breakthrough limit and a collector resistance ρN⁻.

The most significant factor leading to a current-voltage Ratio of a transistor in a high voltage range contributes is electron multiplication. A tension increase wax causes an increase in the production of electrical equipment holes and holes. Holes, which from the electron ver multiplication are generated and reach a basic area, are the factor that works just like the ge ordinary base current to turn the transistor ON. The Recombination of the electrons occurring in the base area and holes, however, suppresses such a transistor drifted. When the transistor is in a stable state these contradicting processes must be mutually exclusive be balanced.

Fig. 1 shows three kinds of states of a representative operating point of a V _CEO (SUS) waveform, (a), (b) and (c).

Fig. 2 shows an internal electric field in the event that a high voltage is applied between a collector and emitter of an NPN transistor. A vertical axis denotes an electric field strength, while a horizontal axis denotes emitter, base and collector layers. The solid line shows a state corresponding to the point (c) in Fig. 1, the dashed line a state corresponding to the point (b), and the broken line shows a state corresponding to the point (a). For the sake of simplicity, the reference numerals in Fig. 45 are used for corresponding parts in the following description.

When a voltage is applied between the collector and the emitter, a depletion layer extends from the interface of a PN junction of the base and the collector, where an electric field within the high resistance collector layer 11 has the greatest strength in the PN junction. An inclination of the electric field is shown by a solid line which is tilted to the right downward in relation to an N-type impurity concentration within the high resistance collector layer 11 . The electric field depends heavily on the electron multiplication feature. As soon as the voltage increases, sooner or later a large increase in the number of holes and electrons generated will begin to be caused. The holes created penetrate directly into a base region 2 ( 21, 22 ) and act as a base current. When the number of holes becomes larger than the number of holes consumed by recombining electrons and holes within the base region 2 , the collector current begins to flow. The state of point (c) lies in the critical point thereof.

Next, the state of the point (b) at which the collector current flows to some extent will be described. The collector current flows on the condition that the holes generated by the electron multiplication and the holes dissipated in the base region 2 are well balanced (it appears that a situation in which breakdown current flows will be understood as a special situation, but what in the Base area 2 is just exactly the same as in normal ON operation).

Electron multiplication is primarily caused in a section in which the strongest electric field is present (PN junction). Electrons that are generated in it lie in a depletion layer with a density that is related to a current value. The electrons electrically compensate for part of the positive ions of impurity atoms in the high resistance collector layer 11 . As a result, an inclination of the electric field in the high resistance collector layer 11 is moderated. This means that a transistor has a counter coupling mechanism against an increase in the collector current in the reverse direction (breakdown current). This negative feedback mechanism can explain a characteristic of the holding phenomenon that a stable state can be observed.

The inclination to the bottom right of the electric field in the high resistance collector layer 11 is related to an electric charge density in the depleted high resistance layer 11 , and thus the inclination becomes more and more moderate as the collector current increases.

In a state in which the collector current becomes increasingly stronger and in which the electrons of a component of the collector current and the impurity atoms become identical in intensity, the electric field in the high resistance collector layer 11 has one of those Dash line (a) shown in FIG. 2 flat distribution.

In this situation, the above-mentioned arrangement of the negative feedback disappears, which results in instability. For example, in the event that the current continues to increase, the flat distribution of the electric field tends to be tipped upward, but the holes created by electron multiplication tend to cause an electric field tapered downward. This results in a unique electric field distribution, in which the strength of the electric field on the opposite sides of the collector layer with high resistance 11 is very large, but is very small in its central part. The voltage applied is an integer value of the high resistance layer 11 . Thus, under the same applied voltage, the maximum strength of the electric field on the opposite sides of the high resistance collector layer II in the above-mentioned unique distribution is larger than that in the flat distribution of the electric field. The electron multiplication caused on the opposite sides of the high resistance collector layer 11 has a distribution of the electric field inclined to the bottom right on the PN⁻ junction side, while it has a distribution on the N⁻-N⁺ junction side of the electric field with an inclination towards the top right. Specifically, a positive negative feedback phenomenon is caused where the opposite sides drop steeply and deeply as soon as the above-mentioned unique distribution of the electric field has developed where the opposite sides gradually lower and the bottom part in between. Although all of this is simply observed within the high resistance collector layer 11 , an increase in the collector current caused by the holes produced as the base current must be considered in a practical transistor. It follows that a current value at which there is a flat distribution of the electric field is a critical point at which the stability of transistor operation deteriorates drastically. Such a transistor operation is the cause of breakdown, especially under the high voltage at which the holding phenomenon is caused. This is a breakthrough point shown by point (a) in FIG. 1.

Although an illustrative first type V _CEO (SUS) _withstand voltage situation where a base connection opens has been described, the same theory can be used to explain a second type (V _CEX (SUS) _withstand voltage situation The situation associated with the second type V _CEX (SUS) _withstand voltage is simply modified by the fact that the supply of base current in the reverse direction and the recombination of electrons cause dissipation of holes in the base area In particular, the collector current flees under the circumstance that the outflow of the holes from the base region (recombination of the holes + base current in the backward direction) and the excursion of the holes due to the electron multiplication are in good balance with one another.

The fact that a higher voltage has to be applied in order to achieve the electron multiplication well balanced with the amplified base current in the reverse direction while the base current is amplified in the reverse direction supports the tendency that the holding voltage of the second type V _CEX ( SUS) moves to a high voltage, while the base current is amplified in the reverse direction.

2-3. Measurement results and through theoretical analysis principle 3-3-1. Resistance and breakthrough limit

It is expected that there will be a holding zone in which cher the transistor works in a stable state, and gives a breakthrough zone a clear dividing line, and that the dividing line is marked in a current value that corresponds to a state in which the electron density the collector current and the impurity density in the col represents high resistance detector layer.  

Accordingly, the current value representing the barrier layer can be increased by increasing the impurity density in the high resistance collector layer 11 , that is, by reducing the resistance, and the breakdown limit can be improved considerably.

Like the impurity density in the high resistance collector layer 11 , the rising voltage (BV _CEO ) of the holding voltage falls from the first type V _CEO (SUS). There was simply empirically known a relationship between the first type V _CEO (SUS) with the operating limit, but it has been found that there is no less than several hundred volts difference between the rise voltage and the breakdown point. It has also been found that the rising voltage can be sharply raised by reverse biasing between the base and the emitter.

2-3-2. Breakthrough limit due to load short circuit

By setting a low resistance ρN⁻ the Kol However, the high resistance detector layer becomes a disadvantage exerted effect. This is the case when a load of the Darlington circuit is short-circuited.

If the load short circuit is caused, a flees over moderate current with the same voltage as the voltage, before the load short circuit was created so that the Transi carries out normal ON operation. The transistor must endure this situation for a time different from that Detection of such an abnormal condition until it has occurred Interruption of the base current (about a few tens of microseconds) lasts.

Figure 3 shows a short circuit breakdown test circuit.

The supply voltage of this circuit is set to a certain value and the transistor is supplied with a single shot of the base current with a fixed length of time (approximately 50 μs) in order to switch it ON. At this point, the maximum value of the collector current (IC) and the collector-emitter voltage (V _CE ) are read. Fig. 5 shows how this process is repeated, the supply voltage 0 is gradually increased until the moment of breakdown. The short-circuit breakdown in transistors can be divided into two types, in which the breakdown is caused by temperature rise in a chip, and in which the breakdown is caused at the moment when the applied voltage reaches a specified value. The measuring method shown here relates to the observation of the latter type. The breakpoint is identified by the symbol X.

It was found that the temperature rise caused short circuit breakdown at the suppressed put tension within a period of about meh reren ten µs would not occur.

Next, a case of a single transistor without Dar lington circuit will be described. A curve L1 in Fig. 5 represents measurement results in the case of a base current value (IB1) under ordinary use conditions.

Curves L2 and L3 in Fig. 5 are obtained when an extremely weak base current (IB1) is supplied; curve L2 is a result when the collector resistance ρN⁻ is small, while curve L3 is a result when the collector resistance ρN⁻ is on an ordinary rule.

One way to improve a breakdown limit by load short-circuiting is to suppress the collector current from being exceeded. As a way of doing this, these examples of curves L2 and L3 can be known as properties in extreme cases where some arrangement is used to make the base current short in the event of a short circuit. A waveform of curve L2 is substantially the same as a waveform of the first type V _CEO (SUS) withstand voltage in Fig. 1. Although the voltage rise of the first type V _CEO (SUS) withstand voltage is decreased while the collector resistance ρN ⁻ Is reduced, there is no risk of breakdown until the voltage and the current value reach the same level as when the above-mentioned holding phenomenon breaks. While the voltage which causes the breakdown phenomenon to breakdown is approximately equal to the nominal voltage, the voltage which causes the load short circuit is approximately equal to 80% of the nominal voltage. Consequently, the transistor can theoretically avoid short-circuit breakdown only by limiting the collector current. Consequently, with such an arrangement, the reduction of the collector resistance ρN⁻ theoretically has no adverse effect.

FIG. 6 shows results of a measurement of a transistor connected in a Darlington circuit, which correspond to the measurement in FIG. 5. A curve L4 expresses an example of a short circuit of a Darlington transistor with the base current (IB1) under the condition of ordinary use, a curve L5 expresses an example of a Darlington transistor with an extremely weak base current value (IB1), and a curve L6 expresses an example of a single transistor with a small base current value (IB1). A transistor connected in Darling ton circuit has a large current gain hFE, and therefore the collector current increases very quickly when the transistor is measured with the extremely weak base current value (IB1).

The reason for this is that a first stage of Darlington Transistors have an extraordinarily smaller collector current density has as its second stage. With the stopping phenomenon he  the withstand voltage increases as soon as the current density increases increases. This is because the collector density of the first Stage of the Darlington transistor 1 / hFE times as rough as the current density of its second stage, and the withstand voltage therefore hardly increases even if the collector current value increases in the first stage.

Even with a sophisticated arrangement of an external circuit of the transistor to improve the short-circuit limit, no short-circuit limit can be obtained which is more than a voltage value which corresponds to the base opening breakdown voltage BV _CEO .

In this way, when the resistance ρN⁻ of a high resistance layer is set to a relatively low value, there arises a problem that the upper limit voltage in the case that a short-circuit protection circuit is used is the base opening breakdown voltage value BV _{CEO is} limited.

However, it is possible that the limitation of fatigue limit for short circuit when the collector resistance is reduced stands is initiated.

This can be done with regard to the resistance of the layer high resistance of the collector can be achieved by the Resistance of the first stage of the transistor turned higher is presented as that of its last stage.

The breakthrough limit due to reverse voltage depends on the resistance stood the collector layer with high resistance of the last Step down and get bigger with decreasing resistance.

3. Details of Theory 1 3-1. Results of the variable ratio experiment nis r from ρN⁻ to tN⁻

Fig. 7 shows results of an experiment with a variable ratio r of the collector resistance t⁻ to the collector film thickness t⁻ in a single NPN transistor, where a value of the collector film thickness t⁻ is shown as a parameter. This breakdown is related to the first Type V _CEO (SUS) withstand voltage, and the breakdown voltage value is set for a chip arrangement that is equivalent to a nominal value of 150 A.

In Fig. 7, a curve L7 expresses a breakthrough current at the collector film thickness t⁻ = 140 µm (open circles);
a curve L8 expresses a breakthrough current at the collector film thickness tN⁻ = 120 µm (open checks);
expresses a curve L9 breakdown current for the collector film thickness tN⁻ = 140 µm (dark circles);
expresses a curve L10 breakdown current at the collector film thickness t⁻ = 120 µm (dark squares).

As can be seen from Fig. 7, the breakdown current increases and the breakdown voltage is reduced, as the ratio r becomes smaller.

3-2. Preferred range of the ratio r

As can be seen from Fig. 7, the breakdown current can be increased without lowering the breakdown voltage as much if the ratio r is in a range which is less than 0.6. In comparison to a ratio of the change in the breakdown current to a change in the breakdown voltage, the change ratio of the breakdown voltage is smaller. Consequently, it is possible that a high voltage property of a transistor, which relates to both the breakdown current and the breakdown voltage, is improved by the collector resistance ρN⁻ and the collector film thickness tN⁻ are set so that the ratio r as shown above is less than 0.6.

The lower limit of the ratio r is a positive one Value that depends on a value of the required Breakdown voltage is set.

4. Contents of preferred embodiments

An example of a currently representative bipolar oil sistors classified as 1000 to 1200 V and for one Inverter for 440 V AC line is used now in connection with various preferred embodiments forms of the present invention. Darlington Transistors in the preferred embodiments are like this formed that they both the <theory 2-1 <and the <Theory 2-2 <according to the present invention. Part of a majority of those in the Darlington transistors contained transistors is in accordance with <theory 1 <of the present invention configured.

In common use, conventional Darlington Transistors classified as 100 to 1200 V, three formed on an identical chip and in Darlington Circuit connected transistors.

In a Darlington transistor of this embodiment its front and back stage, however, with regard to the col lector resistance ρN⁻ different, and therefore it is difficult, both a front stage and a rear stage transistor in a single chip. Episode are the front stage transistor and the back stage train  sistor formed in various chips, which in turn are formed by Wiring are interconnected.

In general, when M is an integer of 2 or more, the first through m th transistors connected in Darlington circuit can be classified as follows:
Front stage transistor: a transistor of the first stage up to a transistor of the mth stage, and
Downstream transistor: a transistor of the (m + 1) th stage up to an M th transistor, where m is an integer that fulfills the following requirement:

1 m M (4)

In the embodiment according to the present invention the front stages defined in the above manner transistor formed in a first chip while the back stage transistor is formed in a second chip. Then should the following relationship between one to the front stage collector resistor ρN⁻ (F) and an the collector resistor ρN⁻ belonging to the step-down transistor (R) exist;

ρN⁻ (F) <ρN⁻ (R) (5)

and there should also be the following relationship between one to the Front stage belonging collector film thickness tN⁻ (F) and one there is a collector film thickness tN⁻ (R) belonging to the regression;

tN⁻ (F) <tN⁻ (R) (6)

With further classification it results that M Transi are classified into K groups (K 2), and the  Transistors in each group are in one or more chips formed to meet the following requirement;

ρN⁻ (i) <ρN⁻ (i + 1) (7)

and there is also the following relationship between that and Front stage associated collector film thickness tN⁻ (F) and the The stage of the collector film thickness tN⁻ (R);

tN⁻ (i) <tN⁻ (i + 1) (8)

where ρN⁻ (i) and tN⁻ (i) is the collector resistance ρN⁻ (i) and the collector film thickness tN⁻ (i) of the transistors in an (i) are group.

4-1. Arrangement of a device of a first preferred embodiment

A Darlington transistor of a first preferred embodiment form corresponds to a case in which M = 3 and m = 2 are.

Fig. 8 is a sectional view showing an arrangement of a three-stage Darlington transistor of the first preferred embodiment. As shown in FIG. 8, in a front-stage transistor chip TF, a high resistance collector layer 11 is formed on a low resistance collector layer 12 . In an upper portion of the high resistance collector layer 11 , a base region 21 of a transistor Q1 is formed in a region A1, while a base region 22 of a transistor Q2 is formed in a region A2, and emitter regions 31 and 32 each in a surface of the base regions 21 and 22 are formed selectively. A front-side collector electrode 51 is formed on a surface of the low resistance collector layer 12 , a front-side base electrode 61 is formed on the base portion 21 of the transistor Q1, a front-side emitter electrode 71 is formed on the emitter portion 32 of the transistor Q2, and a base -Emitter connection electrode 81 is shaped to extend from emitter region 21 of transistor Q1 to base region 22 of transistor Q2. The reference numeral 4 denotes an oxide film, the reference numeral 18 a protective ring, and the reference numeral 19 a channel stop.

In a reverse stage transistor chip TR, however, a collector layer with a high resistance 13 is formed on the collector layer with a low resistance 14 . In an upper portion of the high resistance collector layer 13 , a base region 23 of a transistor Q3 is formed in a region A3, and an emitter region 33 is selectively formed in a surface of the base region 23 . A downside collector electrode 52 is formed on an upper surface of the low resistance collector layer 14 , a downside base electrode 62 is formed on the base portion 23 of the transistor Q3, a return side emitter electrode 72 is formed on the emitter portion 33 of the transistor Q3. Numeral 4 denotes an oxide film, 18 a protective ring, and 19 a channel stop.

The front-stage emitter electrode 71 and the rear-side base electrode 62 are electrically connected to each other by wiring 41 , while the front-side collector electrode 51 and the rear-side collector electrode 52 are electrically connected by wiring 42 . Consequently, the front-side base electrode 61 acts as a base electrode of the three-stage Dar lington transistor, the back-side emitter electrode 72 acts as its emitter electrode, and the front-side collector electrode 51 and the back-side collector electrode 52 act as its collector electrodes.

The collector resistance ρN⁻ in the front stage Transi stor chip TF is set to 80 Ωcm, while the collector door film thickness tNicke is set to 120 µm, and the collector gate resistance ρN⁻ in the transistor chip TR is set to 45 Ωcm while the collector film thickness t⁻ is set to 160 µm. Hence the transistor Q2 of the second stage and transistor Q3 of the third stage Transistors, the <theory 2 <and <theory 2-1 and theory 2-2 <.

Regarding the third stage transistor Q3 in the Darlington transistor, the ratio r can be expressed as follows:
r = ρN⁻ (R) / tN⁻ (R)
= 45 (Ωcm) / 160 µm)
= about 0.28
and transistor Q3 corresponds to <theory 1 <.

These two chips TF and TR are installed in the same housing and arranged by wiring in a three-stage Dar lington circuit. Fig. 9 is a plan view showing an example of this. As shown in FIG. 9, an insulating substrate 121 is soldered to a metal base substrate 120 , and an outwardly extending collector electrode 55 , an outwardly extending base electrode 65 , an outwardly extending emitter electrode 75 , and an auxiliary electrode 123 are soldered separately to the insulating substrate 120 .

The front-stage transistor chip TF and the back-stage transistor chip TR are soldered onto the outwardly extending collector electrode 55 , an auxiliary electrode 85 is soldered to the insulating substrate 121 therebetween, and a freewheeling diode 116 is formed. In this step, the front stage transistor chip TF and the back stage transistor chip TR are provided with the collector electrodes 51 and 52 on their respective backs, and therefore the outward extending collector electrode 55 is electrically connected with the collector electrodes 51 and 52 . The front side of the freewheeling diode chip 116 is defined as the anode and its rear side as the cathode. Consequently, the cathode of the freewheeling diode is electrically connected to the outwardly extending collector electrode 55 .

An accelerating diode chip 114 ("speed-up diode chip") is soldered to an outwardly extending base electrode 65 , while an accelerating diode chip 115 is soldered to an auxiliary electrode 123 . The respective front sides of the acceleration diode chips 114 and 115 are defined as anodes and their rear sides as cathodes. Consequently, the cathode of the acceleration diode 114 is electrically connected to the outwardly extending base electrode 65 , while the cathode of the acceleration diode 115 is electrically connected to the auxiliary electrode 123 . In Fig. 9, base electrodes 661 and 62 , emitter electrodes 71 and 72 , and a base-emitter connection electrode 81 are actually formed, but are omitted for the convenience of explanation. Accordingly, the following explanation about the outside of the chip and the wiring is related to the base regions 21 to 23 and the emitter regions 31 to 33 , all of which are connected thereto.

The outwardly extending base electrode 65 is connected by a wiring 40 to the base region 21 of the front-stage transistor chip TF, and the emitter region 32 of the front-stage transistor chip TF is connected to an auxiliary electrode 85 by the wiring 40 .

On the other hand, the base region 23 of the reverse stage transistor chip TR is connected by the wiring to the auxiliary electrode 85 , and its emitter region 33 is connected by the wiring 40 to an outwardly extending emitter region 75 .

With the wiring through the wiring 40 , the front stage transistor chip TF and the back stage transistor chip TR represent the three-stage Darlington transistor.

The surface of the accelerating diode chip 114 is connected to the auxiliary electrode 123 by wiring, while the surface of the accelerating diode chip 115 is connected to the auxiliary electrode 85 by the wiring 40 . The result is that transistor Q1 of the first stage and transistor Q2 of the second stage each have their respective acceleration diodes between their base and their emitter.

The surface of the freewheeling diode is connected through the wiring 40 to the outwardly extending emitter electrode 75 , whereby the freewheeling diode can be seen between the emitter and the collector of the third stage transistor Q3.

As previously mentioned, the resistance of the high resistance collector layer is approximately 80 Ωcm in the front transistor and approximately 45 Ωcm in the last stage transistor. BV _CEO is approximately 950 V in the front stage transistor and approximately 650 V in the transistor of the last stage. The entire chip surface is approximately 800 mm ² , and the nominal current in such a voltage class is equivalent to approximately 150 A.

4-2. Characteristic of a device before the first preferred embodiment

As for this transistor, Fig. 10 shows a measurement example of the fatigue limit against short circuit similar to that in Fig. 6. In Fig. 10, curve L14 represents a case in which the base current IB1 is at an ordinary level, and curve L15 one Represents case in which the base current IB1 is very low.

In the measurement with the extremely weak base current, as shown by curve L15, the collector current increases near from a point just above a voltage of around 650 V, which is equivalent to BV _{CEO of} the downstep to a point of around 950 V, which is equivalent to BV _{CEO of} the front stage. A drastic increase in the collector current then occurs.

During a section in which the collector current increases linearly, it can be seen that the front stage does not work, but that the back stage alone allows current to flow. When the supply voltage reaches approximately 950 V, equivalent to BV _{CEO of} the front stage, a breakdown is caused between the collector and the emitter of the front stage, and the generated current acts as the base current on the back stage, and thereby occurs the drastic increase in electricity.

As already described, in the transistor according to the present invention a protection mechanism against short-circuit can be used in a way to reduce the collector current up to the voltage value of the BV _{CEO of} the front stage.

If front and rear stages have tN⁻ = approximately 140 µm, the current amplification factor hFE = approximately 200 below the collector current of 150 A in the transistor shown in FIG. 45, while if the front stage tN⁻ (F) = approximately 120 µm and the regressive tN⁻ (R) = approximately 140 µm, hFE = approximately 700 below the collector current of 150 A. When the collector film thickness tN⁻ (F) is reduced, a value of the base opening breakdown voltage BV _{CEO is} reduced , but increasing the collector resistance pN (F) can prevent the breakdown voltage from decreasing.

As for the regress, the resistance ρN⁻ of the high resistance collector layer is reduced, and r <0.6 is satisfied with respect to the ratio r (similar to the case of FIG. 1), the high voltage breakdown limit being considerable can be improved.

4-3. Method of manufacturing a device of the first preferred embodiment

The following is a method of making a three stage Darlington transistor of the first preferred off management form described.

First, a method of forming a collector layer described with high resistance.

As shown in Fig. 11, a monocrystalline Si (silicon) rod is exposed to 200 neutrons 210 to cause a nuclear reaction of a part of the silicon in N-type atoms. At this time, the resistance of the high resistance collector layer can be formed with high accuracy by controlling the amount of neutrons radiated by the density and irradiation time of the neutrons 210 .

The monocrystalline silicon rod 200 , to which an N-type impurity has already been added, is cut into wafers like a wafer 201 shown in FIG. 12. The wafer 201 is used as an N-type semiconductor substrate, and the N-type impurity is implanted in its front and back sides around N⁺ layers 202 and 203 with high concentration of an N-type impurity in the front and backside of the semiconductor substrate 201 as shown in FIG. 13.

The laminated layers are precisely cut off from a main surface of the N 202 layer 202 as the semiconductor substrate 201 , and consequently a film thickness t 'of the remaining semiconductor substrate 201 , which should act as a high resistance collector layer, as shown in FIG. 14 can be determined precisely. Furthermore, the N⁺ layer 203 should act as a collector layer with low resistance.

In this way, a precise resistance and a precise film thickness of the collector layer with high resistance can be achieved. Everything as the first method to manufacture position of a collector layer with high resistance is described.

The following is a description of a second method of manufacturing a high resistance collector layer. First, as shown in FIG. 15, an N⁺ semiconductor substrate 204 , which is said to act as a low resistance collector layer, and, as shown in FIG. 16, an N⁻ layer 205 , which as Collector layer with high resistance should act, formed by growing an epitaxial layer on the surface of the N⁺ semiconductor substrate (N⁺ wafer) 204 . At this point, a precise film thickness t ′ and a precise resistance of the N⁻ layer 205 must be achieved.

By the above-mentioned first or second method for producing a collector layer with a high resistance, a collector layer with a high resistance 13 , which has a relatively coarse film thickness ((160 + α) µm) and a relatively low resistance (45 Ωcm), and a low resistance collector layer 14 formed on a first chip as shown in FIG. 17. A method for the manufacture of a transistor on the first chip, which is to act as a step-down transistor chip, will be described in the following.

First, as shown in FIG. 19, an oxide film 104 is formed on surfaces of the high resistance collector layer 13 and the low resistance collector layer 14 by a thermal oxidation method, respectively.

Subsequently, according to FIG. 21, the oxide film 104 formed on the surface of the collector layer 13 with high resistance is structured by means of photolithography. In this step, the oxide film 104 formed on the surface of the low resistance collector layer 14 is completely removed.

Furthermore, according to FIG. 23, by means of an ion implantation of a P-type impurity or by means of diffusion in a gas containing an impurity, the P-type impurity is introduced into the surface of the collector layer 13 with high resistance and up to one Diffused depth α in an oxidizing atmosphere to form a base region 23 and a protective ring 18 . As a result, the thickness of the collector film tN⁻ (R) reaches 160 µm. The oxide film 104 is formed on the collector layer with high resistance 13 and the collector layer with low resistance 14 .

Thereafter, according to Fig. 25 of the oxide formed on the surface of the collector layer 13 having a high resistance film by means of photolithography structured. The oxide film 104 formed on the surface of the low resistance collector layer 14 is completely removed.

Furthermore, will Fig mutandis. 27 introduced an impurity of N-type in the surface of the collector layer 13 with a high reflection level and up to a predetermined depth β (<α) in an oxidizing atmosphere to form an emitter preparation ches 33 and diffused a channel stops 19th

The oxide film 104 is formed on the surfaces of the collector layer 13 with high resistance and the collector layer 14 with low resistance.

Then, according to FIG. 29, the oxide film 104 formed on the surface of the collector layer 13 with high resistance is structured by means of photolithography. The oxide film 104 structured in this way serves as oxide film 4 according to FIG. 8. The oxide film 104 formed on the surface of the collector layer 14 with low resistance is completely removed.

Then, as shown in FIG. 31, a metal layer 106 is formed above the entire surface of the collector layer 13 with high resistance by means of vapor deposition, sputtering, etc.

Next, FIG mutandis. 33, the metal layer 106 ver siselektrode by photolithography to form a back-side Ba 62 and a rear emitter electrode 72 structured.

Then, as shown in FIG. 35, a metal layer serving as a collector electrode 52 is formed above the entire surface of the low-resistance collector layer 14 , so that the step-down transistor is completed in this way.

On the other hand, by means of the above-mentioned first or second method for producing a high resistance collector layer, a high resistance collector layer 11 having a relatively small film thickness ((120 + α) µm) and a relatively high resistance (80 Ωcm) and a low resistance collector layer 12 formed on a second chip different from the first chip as shown in FIG. 18. In the following, a method for producing a transistor on the second chip, which serves as a front-stage transistor chip, is explained.

First, Figure 29, the oxide film 104 on the surfaces of the collector layer, in accordance with. 11 of high resistance and low resistance collector torschicht 12 formed by chemical Oxi dation.

Thereafter, according to Fig. 22 of the oxide formed on the surface of the collector layer 11 with a high resistance film 104 by means of photolithography structured. The oxide film 104 formed on the low resistance collector layer 12 is completely removed.

This is followed byFig. 24 by means of ion im plantation of a P-type or mediated impurity Diffusion in a gas containing an impurity P-type contamination in the surface of the collector High resistance gate layer11 introduced and up to egg ner depth α in an oxidizing atmosphere to form the Ba areas21st,22 and the guard ring18th diffused. As a result, the collector film becomes thick tN⁻ (F) of 120 µm. In this step the oxide film104   on the surfaces of the collector layer with high resistance was standing11 </ 45166 00070 552 001000280000000200012000285914505500040 0002004306464 00004 45047BOL <and the low resistance collector layer 12 formed. Next, as shown in FIG. 26, that on the surface of the High resistance collector layer 11 formed oxide film 104 structured by photolithography. At this step is the low on the surface of the collector layer oxide film 104 formed according to resistor 12 completely ent distant. This is followed by contamination as shown in FIG. 28 of the N type in the surface of the collector layer with high Resistor 11 introduced and to a depth β ( <α) in oxidizing atmosphere to form emitter regions 31, 32 and a channel stop 19 diffused. With this Step, oxide film 104 is formed on the surfaces of the col high resistance detector layer 11 and the collector low resistance layer 12 is formed. Furthermore, according to FIG. 30, the surface of the High resistance collector layer 11 formed oxide film 104 structured using photolithography. The one on this Oxide film 104 structured in this manner serves as oxide film 4 according to FIG Fig. 8. In this step, the surface of the Low resistance collector layer 12 formed oxide film 10 completely removed. Then, according to FIG. 32, steam is removed separation, sputtering, etc. a metal layer 106 over the entire surface of the collector layer with high resistance 11 formed. 34, the metal layer 106 is passed through Photolithography to form a front base electrode 62,  a base-emitter connection electrode 81, and a front derstufenemitter-electrode 72 structured. Following this, as shown in FIG. 36, is a collector Gate electrode 51 serving metal layer above the entire Surface of the low resistance collector layer 12 is formed, and thus the front-stage transistor is completed constant. In the front and rear stages produced in this way Entransistors become the front-stage emitter electrode 71 and the backside side base electrode 62 electrically a wiring 41 is connected while the front stages are tenkollektor-electrode 51 and the back stage side collector Electrode 62 electrically connected by wiring 42 be, so that the three-stage Darlington transistor according the first preferred embodiment shown in FIG. 8 example is completed. 4-4. Arrangement of a device according to a second preferred embodiment A Darlington transistor according to a second preferred Embodiment is equivalent to a case where: M = 2, m = 1. 37 shows an arrangement in a schematic view a second stage Darlington transistor according to the two th preferred embodiment. As shown in Fig. 37 is placed in a front-stage transistor chip TF a collector layer with high resistance 11 on a Kol lector layer with low resistance 12 is formed. A ba Sis area 21 of a transistor Q1 is in an area A1 an upper portion of the collector layer with high Wi derstand 11 formed while an emitter region 31 selectively  is formed on a surface of a base region 21. There is also a front stage side collector electrode 51 on a surface of the low collector layer Resistor 12 formed, a front step side base elec Trode 61 is on the base region 21 of transistor Q1 and is a front step side emitter electrode 71 formed on the emitter region 31 of the transistor Q1. The Numeral 4 denotes an oxide film, the numeral 18 denotes a protective ring, and the reference number 19 be draws a channel stop. On the other hand, in a step-down transistor Chip TR has a collector layer with high resistance 13 a low-resistance collector layer 14 is formed. A base region 22 of a transistor Q2 is in a loading rich A2 with an upper section of the collector layer high resistance 13 is formed, and an emitter region 32 is selectively formed in a surface of the base region 22. Furthermore, a reverse side collector electrode 52 on the surface of the low resistance collector layer stood 14 formed, a back step side base electrode 62 is formed on the base region 22 of the transistor Q2, and a back side emitter electrode 72 is on the emit terbereich 32 of transistor Q2 formed. The reference number 4 denotes an oxide film, reference numeral 18 denotes a guard ring, and reference numeral 19 denotes one Channel stop. The front step side emitter electrode 71 and the back step Side base electrode 62 are electrically connected via a ver wire 41 connected while the front stage side collector gate electrode 51 and the reverse side collector electrode 52 are electrically connected by wiring 42. Like this 10, the front step side base electrode 61 acts as one Base electrode of the second stage Darlington transistor, the backside side emitter electrode 72 acts as this  Emitter electrode, and the front stage side collector elec trode 51 and the reverse side collector electrode 52 serves as its collector electrode. In the front stage side transistor chip TF is the collector gate resistance ρN⁻ of the collector layer with high resistance 11 set to 110 Ωcm and its collector film thickness tN⁻ is set to 100 µm, and in the downgrade train sistor chip TR is the collector resistance ρN⁻ the collector Gate layer with high resistance 13 set to 45 Ωcm and its collector film thickness tN⁻ is set to 160 µm poses. Thus, transistor Q1 meets the first stage and second stage transistor Q2 <Theory 2 <. A transistor that the <Theory 1 <fulfilled is the second Step transistor Q2 (r = 45/160 = about 0.28). 4-5. Method of manufacturing a device according to the second preferred embodiment Similar to the first preferred embodiment the front stage side transistor chip TF and the Reverse side transistor chip TR separately posed. 4-6. Arrangement of a device according to a third preferred embodiment A Darlington transistor according to a third preferred Embodiment is equivalent to a case where M = 3, m = 1. 38 shows a sectional view of an arrangement of a Three-stage Darlington transistor according to the third before preferred embodiment. As shown in Fig. 38  is in a front stage transistor chip TF a Kol Lector layer with high resistance 11 on a collector low resistance layer 12 is formed. A base region 21 of a transistor Q1 is in a loading rich A1 with an upper section of the collector layer high resistance 11 is formed, while an emitter region 31 selectively formed in a surface of the base region 21 is. This is followed by a front stage side panel gate electrode 51 on a surface of the collector layer formed with low resistance 12, and it becomes a pre the step side base electrode 61 on the base region 21 of transistor Q1 is formed, and it becomes a front stage side emitter electrode 71 on the emitter region 31 of the Transistor Q1 formed. The reference number 4 designates one Oxide film, reference numeral 18 denotes a protective ring, and reference numeral 19 denotes a channel stop. On the other hand, in a backstage side transi stor chip TR a collector layer with high resistance 13 on a surface of a low collector layer Resistor 14 formed. The base areas 22 and 23 of the Transistors Q2 and Q3 are one in regions A2 and A3 upper section of the collector layer with high resistance 13 are respectively formed, and emitter regions 32 and 33 are se formed selectively on surfaces of the base regions 22 and 23. This is followed by a backstage side collector elec trode 52 on the surface of the collector layer with low formed according to resistor 14, a back side side base elec trode 62 is ge on the base region 22 of the transistor Q2 forms, a back stage side emitter electrode 72 is on the emitter region 33 of the transistor Q3, and a Base-emitter connection electrode 82 is over the emitter region 32 of the transistor Q2 to the base region 23 of the Transistor Q3 formed. The reference number 4 designates one  Oxide film, the reference numeral 18 a protective ring, the reference number 19 denotes a channel stop. The front stage side emitter electrode 71 and back stages side base electrode 62 are electrical by means of a Wiring 41 connected while the front step side col detector electrode 51 and backside side collector electrode 52 are electrically connected by means of a wiring 42. Thus, the front step side base electrode 61 acts as a base electrode of a three-stage Darlington transistor, the backside side emitter electrode 72 acts as one Emitter electrode, and the front stage side collector elec trode 51 and the reverse side collector electrode 52 we ken as collector electrodes. In the front stage side transistor chip TF is the collector gate resistance ρN⁻ of the collector layer with high resistance 11 set to 80 Ωcm, and its collector film thickness tN⁻ is set to 120 µm, and in the downgrade train sistor chip TR is the collector resistance ρN⁻ Collector layer with high resistance 13 turned to 45 Ωcm represents, and its collector film thickness tN⁻ is to 140 microns set. Thus, transistor Q1 meets the first Stage and the transistor Q2 of the second stage <Theory 2nd <. A transistor that the <Theory 1 <fulfilled is a two stage transistor Q2 or a three-stage transistor Q3 (r = 45/140 = about 0.32). 4-7. Method of manufacturing a device according to the third preferred embodiment Similar to the first preferred embodiment the front stage side transistor chip TF and the  Reverse side transistor chip TR separately posed. 4-8. Arrangement of a device according to the fourth be preferred embodiment A Darlington transistor according to a fourth preferred Embodiment is equivalent to a case where M = 4, m = 3. Fig. 39 shows a schematic in a sectional view order of a four-stage Darlington transistor according to the fourth preferred embodiment. As in Fig. 39 is shown, is in a front-stage transistor chip TF a collector layer with high resistance 11 on a Kol lector layer with low resistance 12 is formed. There are base regions 21 to 23 of transistors Q1 to Q3 in areas A1 to A3 of an upper section of the collector High resistance gate layer 11 formed, while Emit ter areas 31 to 33 selectively in surfaces of the Basisbe rich 21 to 23 are formed. Furthermore, is a front step side collector electrode 51 on a surface of the Low resistance collector layer 12 formed, a Front step side base electrode 61 is on the base Rich 21 of transistor Q1 is formed, a front stage tenemitter electrode 71 is on the emitter region 33 of the Transistor Q3 formed a base-emitter connection elec Trode 81 is over the emitter region 31 of transistor Q1 to the base region 22 of the transistor Q2, and a Base-emitter connection electrode 83 is over the emitter region 32 of transistor Q2 to base region 23 of the Tran transistor Q3 connected. The reference number 4 designates a Oxide, reference numeral 18 denotes a guard ring, and reference numeral 19 denotes a channel stop.  On the other hand, is in the reverse side transistor chip TR a collector layer with high resistance 13 a surface of a low resistance collector layer stood 14 formed. A base region 24 of a transistor Q4 is the area in an area A4 of an upper section High resistance gate layer 13 is formed, and an emit ter area 34 is selective on a surface of the base portion rich 24 formed. Then there will be a backstop side collector electrode 52 on the surface of the col low resistance layer 14 formed, a Reverse side base electrode 62 is on the base area 24 of the transistor Q4 is formed, a back stage side center Relectrode 72 is on the emitter region 34 of the transistor Q4 formed. The reference numeral denotes an oxide film, the Reference number 18 denotes a protective ring, the reference number fer 19 denotes a channel stop. The front stage side emitter electrode 71 and back stages side base electrode 62 are electrical by means of a Wiring 41 connected while the front step side col detector electrode 51 and backside side collector electrode 52 are electrically connected by means of a wiring 42. Thus, the front step side base electrode 61 acts as a base electrode of a four-stage Darlington transistor, the backside side emitter electrode 72 acts as one Emitter electrode, and the front stage side collector elec trode 51 and the reverse side collector electrode 52 we ken as collector electrodes. The collector is in the front-stage side transistor chip TF gate resistance ρN⁻ of the collector layer with high resistance 11 set to 80 Ωcm, and its collector film thickness tN⁻ is set to 120 µm, and in the downgrade train sistor chip TR is the collector resistance ρN⁻ Collector layer with high resistance 13 turned to 45 Ωcm  represents, and its collector film thickness tN⁻ is to 140 microns set. Thus, transistor Q3 satisfies the third Stage and transistor Q4 of the fourth stage <Theory 2nd <. A transistor that the <Theory 1 <fulfilled is a four stage transistor Q4 (r = 45/140 = about 0.32). 4-9. Method of manufacturing a device according to the fourth preferred embodiment Similar to the first preferred embodiment the front stage side transistor chip TF and the Reverse side transistor chip TR separately posed. 4-10. Arrangement of a device according to a fifth preferred embodiment A Darlington transistor according to a fifth preferred Embodiment is equivalent to a case where M = 4, m = 2. 40 shows a sectional view of an arrangement of a Four-stage Darlington transistor according to the fifth before preferred embodiment. As shown in Fig. 40 is in a front stage transistor chip TF a Kol Lector layer with high resistance 11 on a collector low resistance layer 12 is formed. A base region 21 of a transistor Q1 is in a loading rich A1 with an upper section of the collector layer high resistance 11 is formed while a base region 22 a transistor Q2 is formed in an area A2, and Emitter regions 31 and 32 selectively in surfaces of the base  areas 21 and 22 are formed. Furthermore is one Front stage side collector electrode 51 on a surface che of the low resistance collector layer 12 gebil det, and it is a front step side base electrode 61 formed on the base region 21 of the transistor Q1, and it is a front stage side emitter electrode 71 on the Emitter region 32 of transistor Q2 is formed, and it is a base emitter connection electrode 81 over the emitterbe rich 31 of transistor Q1 to the base region 22 of the Tran transistor Q2 formed. The reference number 4 designates one Oxide film, reference numeral 18 denotes a protective ring, and reference numeral 19 denotes a channel stop. On the other hand, in a backstage side transi stor chip TR a collector layer with high resistance 13 on a surface of a low collector layer Resistor 14 formed. The base areas 23 and 24 of the Transistors Q3 and Q4 are one in regions A3 and A4 upper section of the collector layer with high resistance 13 are respectively formed, and emitter regions 33 and 34 are se formed selectively on surfaces of the base regions 23 and 24. This is followed by a backstage side collector elec trode 52 on the surface of the collector layer with low formed according to resistor 14, a back side side base elec trode 62 is ge on the base region 23 of the transistor Q3 forms, a back stage side emitter electrode 72 is on the emitter region 34 of the transistor Q4, and a Base-emitter connection electrode 82 is over the emitter region 33 of the transistor Q3 to the base region 24 of the Transistor Q4 formed. The reference number 4 designates one Oxide film, the reference numeral 18 a protective ring, the reference number 19 denotes a channel stop. The front stage side emitter electrode 71 and back stages side base electrode 62 are electrical by means of a Wiring 41 connected while the front step side col  detector electrode 51 and backside side collector electrode 52 are electrically connected by means of a wiring 42. Thus, the front step side base electrode 61 acts as a base electrode of a four-stage Darlington transistor, the backside side emitter electrode 72 acts as one Emitter electrode, and the front stage side collector elec trode 51 and the reverse side collector electrode 52 we ken as collector electrodes. In the front stage side transistor chip TF is the collector gate resistance ρN⁻ of the collector layer with high resistance 11 set to 80 Ωcm, and its collector film thickness tN⁻ is set to 120 µm, and in the downgrade train sistor chip TR is the collector resistance ρN⁻ Collector layer with high resistance 13 turned to 45 Ωcm represents, and its collector film thickness tN⁻ is to 140 microns set. Thus, transistor Q2 satisfies the second Stage and the transistor Q3 of the third stage <Theory 2nd <. Transistors that the <Theory 1 <are a three stage transistor Q3 or a four-stage transistor Q4 (r = 45/140 = about 0.32). 4-11. Method of manufacturing a device according to the fifth preferred embodiment Similar to the first preferred embodiment the front stage side transistor chip TF and the Reverse side transistor chip TR separately posed. 4-12. Arrangement of a device according to a sixth preferred embodiment  A Darlington transistor according to a third preferred Embodiment is equivalent to a case where M = 4, m = 1. 41 shows an arrangement of a Four-stage Darlington transistor according to the sixth before preferred embodiment. As shown in Fig. 41 is in a front stage transistor chip TF a Kol Lector layer with high resistance 11 on a collector low resistance layer 12 is formed. A base region 21 of a transistor Q1 is in a loading rich A1 with an upper section of the collector layer high resistance 11 is formed, while an emitter region 31 selectively formed in a surface of the base region 21 is. Furthermore, there is a front stage side collector elec trode 51 on a surface of the collector layer with low Riges resistor 12 is formed, and it becomes a pre the step side base electrode 61 on the base region 21 of transistor Q1 is formed, and it is a front stage side emitter electrode 71 on the emitter region 32 of the Transistor Q2 formed. The reference number 4 designates one Oxide film, reference numeral 18 denotes a protective ring, and reference numeral 19 denotes a channel stop. On the other hand is in a backstage side transi stor chip TR a collector layer with high resistance 13 on a surface of a low collector layer Resistor 14 formed. The base areas 22 to 24 of the Transistors Q2 to Q4 are one in areas A2 to A4 upper section of the collector layer with high resistance 13 each formed, and emitter regions 32 to 34 are se formed selectively on surfaces of the base regions 22 and 24. This is followed by a backstage side collector elec trode 52 on the surface of the collector layer with low  formed according to resistor 14, a back side side base elec trode 62 is ge on the base region 22 of the transistor Q2 forms, a back stage side emitter electrode 72 is on the emitter region 34 of the transistor Q4, and a Base-emitter connection electrode 82 is over the emitter region 32 of the transistor Q2 to the base region 24 of the Transistor Q4 formed. The reference number 4 designates one Oxide film, the reference numeral 18 a protective ring, the reference number 19 denotes a channel stop. The front stage side emitter electrode 71 and back stages side base electrode 62 are electrical by means of a Wiring 41 connected while the front step side col detector electrode 51 and backside side collector electrode 52 are electrically connected by means of a wiring 42. Thus, the front step side base electrode 61 acts as a base electrode of a four-stage Darlington transistor, the backside side emitter electrode 72 acts as one Emitter electrode, and the front stage side collector elec trode 51 and the reverse side collector electrode 52 we ken as collector electrodes. In the front stage side transistor chip TF is the collector gate resistance ρN⁻ of the collector layer with high resistance 11 set to 80 Ωcm, and its collector film thickness tN⁻ is set to 120 µm, and in the downgrade train sistor chip TR is the collector resistance ρN⁻ Collector layer with high resistance 13 turned to 45 Ωcm and its collector film thickness ρN⁻ is 140 µm set. The transistor Q1 thus fulfills the first Stage and the transistor Q2 of the second stage <Theory 2nd <. Transistors that the <Theory 1 <are two stage transistor, a three stage transistor and a four stage transistor Q2, Q3 and Q4 (r = 45/140 = about 0.32).   4-13. Method of manufacturing a device according to the sixth preferred embodiment Similar to the first preferred embodiment the front stage side transistor chip TF and the Reverse side transistor chip TR separately posed. 4-14. Arrangement of a device according to a seventh preferred embodiment A Darlington transistor according to a seventh preferred Embodiment is equivalent to a case where M = 4, i = 1, 2, 3. 42 shows a sectional view of an arrangement of a Three-stage Darlington transistor according to the seventh ahead preferred embodiment. The three-stage Darlington train sistor has three transistor chips, namely transistor chips TN1, TN2 and TN3 of the first stage, the second stage and the third stage. As shown in Fig. 42, is a Kol in a transistor chip TN1 of the first stage Lector layer with high resistance 11 on a collector low resistance layer 12 is formed. A basic term Range 21 of a transistor Q1 is in a range A1 upper section of the collector layer with high resistance 11, while an emitter region 31 selectively in a Surface of the base region 21 is formed. Furthermore is a collector electrode of the first stage 51 on one Surface of the low resistance collector layer 12 is formed, and it is a base electrode of the first stage 61 formed on the base region 21 of the transistor Q1, and it is an emitter electrode of the first stage 71 on the Emitter region 32 of transistor Q2 is formed. The reference  numeral 4 denotes an oxide film, the reference numeral 18 be draws a guard ring, and reference numeral 19 denotes net a channel stop. On the other hand, is in the transistor chip TN2 second stage, a high resistance collector layer 13 on a surface of a low collector layer Resistor 14 formed. A base region 22 of the transistor Q2 is an area A2 of an upper portion of the collector High resistance gate layer 13 is formed, and an emit The region 32 is selective in a surface of the base region rich 22 formed. Then a collector Second stage electrode 52 on the surface of the col low resistance layer 14 formed a Ba Second stage sis electrode 62 is on the base area 22 of transistor Q2 is formed, and a back stage side Emitter electrode 72 is on the emitter region 32 of the Transistor Q2 formed. The reference number 4 designates one Oxide film, the reference numeral 18 a protective ring, the reference number 19 denotes a channel stop. In the transistor chip of the third stage TN3 is a Kol High resistance detector layer 15 on a collector layer with low resistance 16 formed. A basic term region 23 of a transistor Q3 is in a region A3 upper section of the collector layer with high resistance 15, and an emitter region 33 is selective in one Surface of a base region 23 is formed. A collector third stage electrode 53 is on a surface of the Low resistance collector layer 16 formed, a Third stage base electrode 63 is on the base region 23 of transistor Q3 is formed, and an emitter electrode the third stage 73 is on the emitter region 33 of the tran transistor Q3 formed. The reference number 4 designates one Oxide film, reference numeral 18 denotes a protective ring and reference numeral 19 denotes a channel stop.  The first stage emitter electrode 71 and the base electrode Trode of the second stage 62 are by means of wiring 41 electrically connected, the collector electrode of the second Stage 72 and the base electrode of the third stage 63 electrically connected by wiring 43, and the collector electrode of the first stage 51, the collector second stage electrode 52, and the collector electrode 53 of the third stage are together by means of a Ver wire 44 electrically connected. This is how the basic electrode works trode of the first stage 61 as a base electrode Three-stage Darlington transistor, the emitter electrode of the third stage 73 acts as its emitter electrode, and the First stage collector electrodes 51, the collector electrodes trode of the second stage 52, and the collector electrode of the second stage 52, and the collector electrode of the third Stage 53 act as its collector electrodes. In which The first stage transistor chip TN1 is the collector resistor stood ρN⁻ of the collector layer with high resistance 11 80 Ωcm is set, and its collector film thickness is TN⁻ set to 120 µm; in the transistor chip the second Level TN2 is the collector resistance ρN⁻ the collector layer with high resistance 13 set to 60 Ωcm, and whose collector film thickness TN⁻ is set to 130 µm; the transistor chip of the third stage TN3 is the collector gate resistance ρN⁻ of the collector layer with high resistance 13 set to 45 Ωcm, and its collector film thickness TN⁻ is set to 140 µm. Thus, transistor Q1 the first stage and the transistor Q2 the second stage <Theory 2 <. The transistors that the <Theory 2 <fulfill len, the second stage transistor Q2 and a Tran third stage sistor Q3. Transistors which the <Theory 1 <are the Second stage transistor Q2 (r = 60/130 = about 0.46) and  the third stage transistor Q3 (r = 45/140 = about 0.32). 4-15. Method of manufacturing a device according to the seventh preferred embodiment Similar to the first preferred embodiment the transistor chip of the first stage TN1, the Transi second stage storchip TN2 and the transistor chip third stage TN3 manufactured separately. 4-16. Arrangement of a device according to an eighth be preferred embodiment A Darlington transistor according to an eighth preferred Embodiment is equivalent to a case where M = 4, i = 1, 2, 3, 4. 43 shows a sectional view of an arrangement of a Four-stage Darlington transistor according to the eighth before preferred embodiment. The four-stage Darlington train sistor has four transistor chips, namely transistor chips TN1, TN2, TN3 and TN4 of the first stage, the second Stage, third stage and fourth stage and four Transistor chips. As shown in Fig. 43, in a transistor chip TN1 of the first stage Lector layer with high resistance 11 on a collector low resistance layer 12 is formed. A basic term Range 21 of a transistor Q1 is in a range A1 upper section of the collector layer with high resistance 11 is formed while an emitter region 31 is selective in a surface of the base portion 21 is formed. Furthermore is a collector electrode of the first stage 51 on one Surface of the low resistance collector layer 12 is formed, and it is a base electrode of the first stage  61 formed on the base region 21 of the transistor Q1, and it is an emitter electrode of the first stage 71 on the Emitter region 32 of transistor Q2 is formed. The reference numeral 4 denotes an oxide film, the reference numeral 18 be draws a guard ring, and reference numeral 19 denotes net a channel stop. On the other hand, is in the transistor chip TN2 second stage, a high resistance collector layer 13 on a surface of a low collector layer Resistor 14 formed. A base region 22 of the transistor Q2 is an area A2 of an upper portion of the collector High resistance gate layer 13 is formed, and an emit The region 32 is selective in a surface of the base region rich 22 formed. Then a collector Second stage electrode 52 on the surface of the col low resistance layer 14 formed a Ba Second stage sis electrode 62 is on the base area 22 of transistor Q2 is formed, and a back stage side Emitter electrode 72 is on the emitter region 32 of the Transistor Q2 formed. The reference number 4 designates one Oxide film, the reference numeral 18 a protective ring, the reference number 19 denotes a channel stop. In the transistor chip of the third stage TN3 is a Kol High resistance detector layer 15 on a collector layer with low resistance 16 formed. A basic term region 23 of a transistor Q3 is in a region A3 upper section of the collector layer with high resistance 15, and an emitter region 33 is selective in one Surface of a base region 23 is formed. A collector third stage electrode 53 is on a surface of the Low resistance collector layer 16 formed, a Third stage base electrode 63 is on the base region 23 of transistor Q3 is formed, and an emitter electrode the third stage 73 is on the emitter region 33 of the tran  transistor Q3 formed. The reference number 4 designates one Oxide film, reference numeral 18 denotes a protective ring and reference numeral 19 denotes a channel stop. In the transistor chip of the fourth stage TN4 is a Kol High resistance detector layer 17 on a collector Low resistance layer 28 is formed. A basic term Range 24 of a transistor Q4 is one in an area A4 upper section of the collector layer with high resistance 17, and an emitter region 34 is selective in one Surface of a base region 24 is formed. A collector fourth stage electrode 54 is on a surface of the Low resistance collector layer 28 formed, a Fourth stage base electrode 64 is on the base region 24 of transistor Q4 is formed, and an emitter electrode the fourth stage 74 is on the emitter region 34 of the tran transistor Q4 formed. The reference number 4 designates one Oxide film, reference numeral 18 denotes a protective ring and reference numeral 19 denotes a channel stop. The first stage emitter electrode 71 and the base electrode Trode of the second stage 62 are by means of wiring 41 electrically connected, the collector electrode of the second Stage 72 and the base electrode of the third stage 63 electrically connected by wiring 43 which Third stage emitter electrode 73 and the base electrode 64 of the fourth stage are by means of a wiring 45 electrically connected, and the collector electrode of the first Stage 51, the collector electrode of the second stage 52, the Third stage collector electrode 53 and the collector fourth stage electrodes 54 are common by means of egg ner wiring 46 electrically connected. So that works Base electrode of the first stage 61 as a base electrode of a four-stage Darlington transistor, the Emitterelek fourth stage trode 74 acts as its emitter electrode trode, and the collector electrodes of the first stage 51, the  Second stage collector electrode 52, and the collector third stage electrode 53, and the collector electrode the fourth stage 54 act as its collector electrodes. In the transistor chip of the first stage TN1 Collector resistance ρN⁻ of the collector layer with high Wi 11 was set to 100 Ωcm, and its collector film thickness ρN⁻ is set to 100 µm; at the transi Second stage storchip TN2 is the collector resistance the collector layer with high resistance 13 to 80 Ωcm is set, and its collector film thickness ρN⁻ is set to 120 µm set; in the third-stage transistor chip TN3 is the collector resistance ρN⁻ of the collector layer with high resistance 13 set to 60 Ωcm, and its Kol lector film thickness ρN⁻ is set to 140 µm, and at the Fourth stage transistor chip TN4 is the collector resistor stood ρN⁻ of the collector layer with high resistance 17 45 Ωcm, and its collector film thickness ρN⁻ on 160 µm set. Thus, the transistor Q1 meet the most stage and transistor Q2 of the second stage <Theory 2 <. The transistors that the <Theory 2 <fulfill len, the second stage transistor Q2 and a Tran sistor Q3 of the third stage, and transistors which the <Theory 2 <transistor Q3 are the third Stage and transistor Q4 of the fourth stage. Transistors which the <Theory 1 <are the Third stage transistor Q3 (r = 60/130 = about 0.46) and the fourth stage transistor Q4 (r = 45/160 = about 0.28). 4-17. Method of manufacturing a device according to the eighth preferred embodiment Similar to the first preferred embodiment the transistor chip of the first stage TN1, the Transi  second stage storchip TN2, the third stage transistor chip th stage TN3, and the transistor chip of the fourth stage TN4 made separately. 5. Extent to which the effects of the theory <2-1 < be achieved Before the first, second, fourth, seventh and eighth preferred embodiments is the transistor chip last stage formed as a single transistor, and it will the <Theory 2-1 <between the transistor of the last stage and a front stage transistor of the last stage. As shown by curve L15 in FIG. 11, can be a breakthrough limit in an extreme case good high voltage range can be obtained without the limit deteriorate against short circuit. On the other hand, the third, fifth and sixth most preferred embodiment of the transistor chip last stage by two or more transistors det, and it will be the <Theory 2-1 <between the transistor the last stage and the front stage transistor of the last Level not met. In this case, one becomes so extreme good high voltage property according to curve L15 in FIG. 11 not achieved. However, the <Theory 2-1 <between at least least another front stage transistor and back stages transistor fulfilled as the transistor of the last stage and the front stage transistor of the last stage, and consequently will get better high voltage property in ver equal to a Darlington transistor according to the one gangs described manner is formed. 6. Variations There is no need for <Theory 2-1 <and <Theory 2-2 Absolutely according to the present invention  must be applied simultaneously, whereby <Theory 2-1 < can also be used alone. The Darlington transistor according to the present invention can either be on an NPN transistor or a PNP tran sistor can be applied. The transistor according to an arrangement <Theory 1 <can not just applied to a Darlington transistor, but also on a single bipolar transistor or a bipolar transistor that connects in a different way that is. As has been described, a bipolar transistor according to claim 1 and one according to that in claim 4 bipolar transistor produced a ratio nis ρ / t of a resistance ρ (Ωcm) of a collector layer with high resistance to the film thickness t (µm) the collector layer with high resistance immediately below a Ba sis range of 0.6 or below, so that a High voltage property can be improved. As a result of this, a high voltage property can High voltage power bipolar transistor who improved the. Furthermore, a Darlington transistor according to claim 2 and a Darlington transistor according to the manufacturing ver drive according to claim 5 a resistance of a first collector High resistance gate layer of a front stage bipolar transistor that is larger than a resistance of one second collector layer with high resistance of a backstop fenbipolar transistor, and thus can be a permanent limit against breakdown in a good high voltage range without the safety limit with regard to a Short circuit to deteriorate.

Claims (18)

1. Bipolar transistor with
a low resistance collector layer;
a high resistance collector layer formed on the low resistance collector layer, the resistance of which is set higher than the resistance of the low resistance collector layer;
a base region formed in a surface of the high resistance collector layer; and
an emitter region formed in a surface of the base region; and
wherein a ratio ρ / t of a resistance ρ (Ωcm) of the high resistance collector layer to a film thickness t (µm) of the high resistance collector layer was immediately below the base region 0.6 or less. 2. Bipolar transistor according to claim 1, characterized in that it further has a ge formed on the base region base electrode; and
has an emitter electrode formed on the emitter region. 3. Darlington transistor with
a first bipolar transistor formed on a first semiconductor substrate; and
a second bipolar transistor formed on a second semiconductor substrate;
wherein the first and second bipolar transistors are connected in Dar lington circuit having a front stage of the first bipolar transistor and a back stage of the second bipolar transistor;
wherein the first bipolar transistor comprises a first low resistance collector layer, a first high resistance collector layer formed on the first low resistance collector layer and the resistance of which is set higher than the resistance of the first low resistance collector layer, a first Base region formed in a surface of the first high resistance collector layer and having a first emitter region formed in a surface of the first base region;
wherein the second bipolar transistor has a second low resistance collector layer, a second high resistance collector layer formed on the second low resistance collector layer and the resistance of which is set higher than the resistance of the second low resistance collector layer, a second base region which is formed in a surface of the second high resistance collector layer and has a second emitter region formed in one side of the second base region; and
wherein the resistance of the first high resistance collector layer is set larger than a resistance of the second high resistance collector layer. 4. Darlington transistor according to claim 3, characterized records that the film thickness of the first collector layer with high resistance just below the first Base area is set smaller than the film thickness the second collector layer with high resistance un indirectly below the second base area. 5. Darlington transistor according to claim 4, characterized in that first to M-th (M integer equal to 2 or higher) transistors are connected in a Darlington circuit,
a transistor of the m-th stage (1 m <X) is provided as a front-stage transistor; and
a transistor of the (m + 1) th stage is provided as a Rückstufentran transistor. 6. Darlington transistor according to claim 5, characterized in that
M = 2 and m = 1;
the resistance of a first stage transistor of the front stage transistor is 110 Ωcm and the film thickness is 110 µm; and
the resistance of a transistor of the second stage of the down-stage transistor is 45 Ωcm and the film thickness is 160 µm. 7. Darlington transistor according to claim 5, characterized in that
M = 3 and m = 1;
the resistance of a transistor of the first stage of the front-stage transistor is 120 Ωcm and the film thickness is 80 µm; and
the resistance of a transistor of the second stage of the down-stage transistor 45 Ωcm and the film thickness is 140 microns. 8. Darlington transistor according to claim 5, characterized in that
x = 4 and m = 3;
the resistance of a third stage transistor of the front stage transistor is 120 Ωcm and the film thickness is 80 µm; and
the resistance of a fourth-stage transistor of the down-stage transistor is 45 Ωcm and the film thickness is 140 µm. 9. Darlington transistor according to claim 5, characterized in that
M = 4 and m = 2;
the resistance of a second stage transistor of the front stage transistor is 120 Ωcm and the film thickness is 80 µm; and
the resistance of a transistor of the third stage of the step-down transistor 45 Ωcm and the film thickness is 140 microns. 10. Darlington transistor according to claim 5, characterized in that
M = 4 and m = 1;
the resistance of a transistor of the first stage of the front-stage transistor is 120 Ωcm and the film thickness is 80 µm; and
the resistance of a transistor of the second stage of the down-stage transistor 45 Ωcm and the film thickness is 140 microns. 11. Method for producing a bipolar transistor with
a first step of forming a high resistance collector layer on a low resistance collector layer such that its resistance is set larger than the resistance of the low resistance collector layer;
a second step of forming a base region in a high resistance surface of the collector layer; and
a third step of forming an emitter region in a surface of the base region;
wherein a ratio ρ / t of the resistance ρ (Ωcm) of the high resistance collector layer to the film thickness t (µm) of the high resistance collector layer is directly below the base region 0.6 or less. 12. A method for producing a bipolar transistor according to claim 11, subsequent to the third step further with
a fourth step of forming a base electrode on the base region; and
a fifth step to form an emitter electrode on the emitter region. 13. A method for producing a bipolar transistor according to claim 11, characterized in that the first step comprises the steps:
Manufacture of a single crystal silicon rod;
Irradiating the single crystal silicon rod with neutrons to form a high resistance region in the single crystal silicon rod;
Cutting the monocrystalline silicon rod into a semiconductor substrate formed from the high-resistance region;
Introducing contamination in the front and back of the semiconductor substrate to form a low resistance region in the front and back of the semiconductor substrate; and
Cutting the low resistance region formed in the surface of the semiconductor substrate to define the high resistance region remaining in the semiconductor substrate as the high resistance collector layer and the low resistance region formed in the back of the semiconductor as the low resistance collector layer Define resistance. 14. A method for producing a bipolar transistor according to claim 11, characterized in that the first step comprises the steps:
Producing a semiconductor substrate formed from a low-resistance region; and
Forming a layer formed from a high resistance area on the semiconductor substrate by epitaxial growth to define the semiconductor substrate except for the layer as the low resistance collector layer and to define the layer as the high resistance collector layer. 15. A method for producing a bipolar transistor according to claim 13, characterized in that the second step comprises the steps:
Forming an oxide film on a surface of the high resistance collector layer;
Patterning the oxide film; and
Diffusing an impurity of a given conductivity type to a certain depth in the high resistance collector layer in an oxidizing atmosphere to form the base region. 16. A method for producing a bipolar transistor according to claim 15, characterized in that the third step comprises the steps:
Forming an oxide film on a surface of the high resistance collector layer;
Patterning the oxide film; and
Diffusing an impurity of a given conductivity type different from the given type to a certain depth in the collector layer with high resistance in an oxidizing atmosphere to form the emitter region. 17. A method of manufacturing a Darlington transistor comprising the steps of:
Forming a first bipolar transistor in a first semiconductor substrate;
Forming a second bipolar transistor in a second semiconductor substrate;
Arranging the first and second bipolar transistors in a Darlington circuit, with a front stage of the first bipolar transistor and a back stage of the second bipolar transistor; wherein the step of forming the first bipolar transistor includes the steps of forming a high resistance collector layer on a first low resistance collector layer to set its resistance higher than a resistance of the first low resistance collector layer; Forming a first base region in a surface of the first collector layer with high resistance; and forming a first emitter region in a surface of the first base region;
wherein the step of forming the second bipolar transistor includes the steps of forming a high resistance collector layer on a second low resistance collector layer to set its resistance higher than a resistance of the second low resistance collector layer; and forming a second base region in a surface of the second high resistance collector layer; and forming a second emitter region in a surface of the second base region; wherein the resistance of the first collector layer having a high resistance is set higher than the resistance of the second collector layer having a high resistance. 18. Method of making a Darlington transistor according to claim 17, characterized in that the film thickness of the first collector layer with high resistance just below the first base area is un as the film thickness of the second collector layer indirectly below the second base area.