DE4233777C2 - Manufacturing process for a semiconductor device - Google Patents

Description

The invention relates to a method according to the Preamble of claim 1.  

In the field of semiconductor manufacturing, an integrated Circuit based on an increase in integration density or improved functions by stacking active elements in three-dimensional way, so-called three-dimensional called integrated circuit. When implementing a such a three-dimensional integrated circuit plays a role Process for forming a so-called SOI structure (Silicon On Insulator, silicon on insulator) play a significant role in that a monocrystalline semiconductor layer on an insulator layer is formed.

There are several methods of forming a monocrystalline Silicon layer on an insulator layer has been proposed as e.g. B. a method of forming an oxide film in a substrate by implanting oxygen ions in a monocrystalline Silicon substrate (SIMOX), a melt recrystallization process which is a non-monocrystalline semiconductor on an insulator layer is heated by a heater Melt recrystallization process using high energy Irradiation etc. Especially the melt recrystallization process by means of high-energy radiation to form a three-dimensional integrated circuit indispensable. The three-dimensional integrated circuit is a Integrated circuit built into a structure Multi-layer structure by stacking layers of the integrated Circuit with an intermediate insulating layer converted will, and on a significant improvement in features and Integration density compared to the previous two-dimensional integrated circuits.

The melt recrystallization process is a process of formation a monocrystalline layer by recrystallizing one polycrystalline or amorphous semiconductor layer on one Insulator layer by means of a heat treatment. On High power laser or an electron beam can be used as an energy beam to be used. The laser is mostly used because it is easier to use operate. The temperature distribution within one  molten semiconductor should be controlled so that the Recrystallization starts from any point to a monocrystalline semiconductor layer through the Melt recrystallization process using laser radiation form. There are several methods of controlling the Temperature distribution has been suggested. With every procedure the recrystallization begins at a point of low temperature and continues to places of higher temperature. That leads to Sub-grain boundaries or grain boundaries after the digits are higher Temperature have been recrystallized. On Melting recrystallization process using laser radiation, the an anti-reflection film is used to control the temperature in detail e.g. B. described in US 4,822,752. Now there is one Description of how such a Melting recrystallization process using laser radiation under Using an anti-reflection film a monocrystalline Semiconductor layer is formed.

Fig. 42 shows a perspective cross section of the structure of a semiconductor device in a manufacturing process according to the Schmelzrekristallisationsverfahren by laser irradiation. Figs. 43 to 45 are cross-sections of the structures to illustrate the essential steps of the Schmelzrekristallisationsverfahrens. The melt recrystallization process described below is a process that uses an anti-reflection film to control the temperature distribution in a molten semiconductor layer.

As shown in FIGS. 42 and 43, an insulating layer 2 made of a silicon oxide film is formed on the surface of a monocrystalline silicon substrate 1 . An opening 15 is formed in a predetermined area of the insulating layer 2 . The opening 15 forms a seed area. A non-monocrystalline semiconductor layer, in other words a polycrystalline silicon layer 13 , is formed on the surface of the insulating layer 2 and inside the opening 15 . Antireflection films 14 having a predetermined shape are also formed on the surface of the polycrystalline silicon layer 13 . For example, a silicon nitride film (Si ₃ N ₄ ) is used as the anti-reflection film 14 . The antireflection films 14 are each formed at a location approximately the same distance from the opening 15 created in the insulating layer 2 (see Fig. 42). Although not shown, a thin cover film may be entirely formed on the surfaces of the polycrystalline silicon layer 13 and the anti-reflective film 14 to protect the surfaces from being deformed in the recrystallization process. The opening 15 is filled with polysilicon, which is a non-monocrystalline semiconductor. The crystal orientation of the polycrystalline silicon layer 13 to be recrystallized is therefore controlled on the basis of the monocrystalline silicon substrate 1 .

The reflectivity of the silicon nitride film which forms the antireflection film 14 periodically indicates a maximum value and 0 depending on its thickness. By taking advantage of this effect, a silicon nitride film is used for the antireflection film with a thickness giving a reflectivity of 0. In accordance with this example, a silicon nitride film about 60 nm thick is used as the anti-reflection film 14 . Therefore, the anti-reflection films 14 shown in Figs. 42 and 43, which are selectively formed on the surface of the polycrystalline silicon layer 13 , have zero reflectivity for the laser light 70 , that is, in other words, absorb almost all of the incident light. In contrast, the reflectivity for the laser light 70 is about 40% in the area where the thickness of the anti-reflection film 14 is 0, in other words, in the area where the surface of the polycrystalline silicon layer 13 is exposed. This has the effect that the laser light radiated onto the entire surface of the polycrystalline silicon layer 13 absorbs more in the lower region of the antireflection film 14 and the region is heated to a higher temperature. The laser light used has a wavelength of approximately 488 nm and the beam diameter is in the range of 120-180 µm. A silicon oxide film with a thickness in the range of 1-3 μm is used for the insulating layer 2 . The polycrystalline silicon layer 13 used as the non-monocrystalline semiconductor layer has a thickness of approximately 0.6 μm. The width of the antireflection film 14 is approximately 5 μm and the distance between the films is approximately 10 μm.

The laser light 70 moves at a constant speed while striking the surface of the polycrystalline silicon layer 13 . The temperature of the polycrystalline silicon layer 13 irradiated with the laser light 70 increases and the layer melts. The temperature distribution of the polycrystalline silicon layer 13 at this time is shown in FIG. 46. Fig. 46 shows a temperature distribution showing the relationship between locations on the surface of the polycrystalline silicon layer 13 and the temperature inside. As can be seen from the temperature distribution shown, the temperature in the interior of the polycrystalline silicon layer 13 at the lower region of the anti-reflection film 14 is higher. In other words, the temperature inside the polycrystalline silicon layer 13 is higher than in the vicinity of the opening 15 .

As shown in Fig. 44, after the laser light is turned off, the molten polycrystalline silicon layer 13 cools, the temperature gradually drops, and the recrystallization (solidification) begins in the range of the lower temperatures. As shown in the temperature distribution of Fig. 46, the temperature inside the polycrystalline silicon layer 13 in the vicinity of the opening 15 is low, and in the cooling process, the recrystallization of the polycrystalline silicon layer 13 is triggered by the portion of the polycrystalline silicon layer 13 that defines the opening 15 fills and is used as the germ region 16 . The seed region 16 is connected to the monocrystalline silicon substrate 1 . Therefore, a monocrystalline silicon region 3 a with the same crystal orientation as the monocrystalline silicon substrate 1 extends into its surroundings, starting from the seed region 16 .

As shown in FIG. 45, the completely recrystallized layer changes into a homogeneous monocrystalline silicon layer 3 . The anti-reflection films 14 are then removed.

When a monocrystalline semiconductor layer is formed in this way, the lower portion of the antireflection film has a higher temperature and therefore the recrystallization of the polycrystalline silicon layer starts from the seed regions between the antireflection films and proceeds in the direction of the lower sections of the antireflection films. This leads to the collision of crystals that develop from opposite sides of the anti-reflection film. Sub-grain boundaries 31 occur at the places where the developing crystals collide (see Fig. 45).

Although each section of semiconductor layer between the anti-reflection films is monocrystalline, their crystal orientations are actually somewhat shifted from each other because neighboring semiconductor layers with anti-reflection films in between grow separately as crystals. Sub-grain boundaries 31 are formed as the boundary section. Such sub-grain boundaries 31 appear under the anti-reflection films and therefore their positions can be controlled. Even if the recrystallization is carried out without forming the seed regions (openings), the semiconductor layer portions between the antireflection films are converted into single crystals. However, since nothing defines the orientation of the single crystal in this case, the adjacent semiconductor layers with the antireflection films therebetween have different crystal orientations. More specifically, the boundaries under the anti-reflection films are formed as grain boundaries.

Effects that such grain boundaries or subgrain boundaries have on the properties of active devices formed in that monocrystalline silicon layer are described in "Japanese Journal of Applied Physics", vol. 22, 1983, supplement 22-1, pp. 217-221 or in "Extended Abstracts of the 17th Conference on Solid State Devices and Materials", Tokyo, 1985, pp. 147-150. According to the documents, an increase in the leakage current etc. is induced in the presence of grain boundaries in the channel region of a MOS field-effect transistor. The active region of a transistor is therefore defined in such a way that it defines the existence of the grain boundaries or sub-grain boundaries in the channel region of a MOS field effect transistor according to "IEEE Electron Device Letter", vol. EDL-7, no. 3, March 1986, pp. 193-195. Specifically, as will be described later, a silicon nitride film 181 is patterned to exclude a range of sub-grain boundaries 31 in a monocrystalline silicon layer 3 , as shown in FIG. 50. An active region is formed in a portion of the monocrystalline silicon layer 3 that is free of sub-grain boundaries under the silicon nitride film 181 .

It has been found that the presence of sub-grain boundaries or grain boundaries have no adverse effect on properties active components, even if there are sub-grain boundaries or grain boundaries exist at locations other than in a channel area, e.g. B. in a source / drain area because the resistance of the source / drain Area with impurities of high concentration is reduced, provided that sub-grain boundaries or grain boundaries are not at the pn- Transition exist.

The surface of the monocrystalline silicon layer 3 , which is produced by a melt recrystallization method using such an anti-reflection film as described above, is wavy and roughly graded, as shown in Fig. 45. FIG. 47 shows a graphical representation of the measurement result for the surface roughness of the monocrystalline silicon layer 3 shown in FIG. 45. The measurement represents a case in which the thickness of the recrystallized semiconductor layer is 550 nm. In this case, the steps and indentations of the surface are up to ± 60 nm (± 0.06 µm) or more. The surface of the recrystallized monocrystalline silicon layer 3 is wavy and graded because the surface of the melted polycrystalline silicon layer 13 is partially covered with the anti-reflection films 14 . More specifically, when the polycrystalline silicon layer 13 is recrystallized, the layer under the antireflection film 14 has a higher temperature than the area between the antireflection films 14 . Therefore, the area between the antireflection films 14 solidifies first and the lower area of the antireflection films 14 later. The higher the temperature of the melt, the lower its surface tension, and therefore when the monocrystalline silicon layer 3 solidifies, the first solidifying section 3 a assumes a stepped shape, while the later solidifying section 3 b acquires an indented shape, such as 45 is shown in FIG . In the surface of the monocrystalline silicon layer 3 , steps and indentations are generated corresponding to the positions of the anti-reflection films 14 , as shown in FIG. 45. The width of the antireflection film 14 is approximately 5 μm with a distance between the films of approximately 10 μm, so that the indentation or step occurs approximately every 15 μm. The formation of such indentations and steps in the surface leads to various difficulties in the process of forming active components on the surface of the monocrystalline silicon layer 3 . This results in uneven performances that are achieved by the components.

It is known that in the formation of components on a such a monocrystalline silicon layer on an insulator layer the reduction in the thickness of the semiconductor layer to 0.1 µm or less the performance of the components increases. The film thickness can however not be reduced if the steps and indentations like described above on the surface of the monocrystalline Silicon layer are present.

Polishing the surface of the monocrystalline silicon layer can be carried out as a way of reducing the steps and indentations of the surfaces described above. In particular, a vigorous polishing process that uses a hard abrasive such. B. SiO ₂ , used as a polishing pad, prevailing among the various methods for reducing the surface levels and indentations. When a monocrystalline silicon layer has been polished by this vigorous polishing process, observations with an optical microscope and scanning electron microscope confirm that the steps and indentations of the monocrystalline silicon layer have each been reduced to a size that is only several nm and less, and therefore take the form of a mirror surface.

Even if active components in a monocrystalline Silicon layer are formed so that no grain boundaries or Sub-grain boundaries exist in the active area as described above However, the properties of the active components are wider significantly uneven. Therefore, studies of the Crystal properties of a monocrystalline silicon layer a usual process for forming active components, and the inventors found new defects in the crystal that immediately not discovered after the formation of the monocrystalline silicon layer had been.

Figs. 48-58 show partial cross sections of the steps in their order in a manufacturing process for a CMOS transistor using an SOI structure. With reference to these figures, a description will now be given of a method of forming a MOS transistor using an SOI structure and the related problems.

In Fig. 48, the state is a monocrystalline silicon layer of SOI structure shown immediately after its formation. An insulating layer 2 made of SiO _{2 is} formed on a monocrystalline silicon substrate 1 . A monocrystalline silicon layer 3 is created on the insulating layer 2 . Sub-grain boundaries 31 exist on the monocrystalline silicon layer 3 at constant intervals, as has been described above.

As shown in FIG. 49, an oxide film 17 is created on the monocrystalline silicon layer 3 by means of thermal oxidation. The oxide film 17 is formed to remove the surface defects of the monocrystalline silicon layer 3 . The oxide film 17 is also used as an underlying oxide film in creating element isolation regions in a subsequent step. A silicon nitride film 18 is then formed on the entire surface of the oxide film 17 by means of a CVD process (deposition from the vapor phase). The thickness of the oxide film 17 and the silicon nitride film 18 is 50 nm and 100 nm, respectively.

As shown in Fig. 50, photoresist 45 is formed only on the element region by a photolithography method. The silicon nitride film 18 is then removed using the patterned photoresist film 45 as a mask, leaving a silicon nitride film 181 .

As shown in Fig. 51, photoresist is created in a PMOS transistor area. Using the photoresist films 42 and 45 as masks, boron ions (B) are implanted in the monocrystalline silicon layer 3 through the oxide film 17 . The amount of boron ions implanted at this time is about 3 _* 10 ¹³ cm ^-2 .

As shown in Fig. 52, after removing the resist films 42 and 45 by thermal oxidation using the silicon nitride film 181 as a mask, a thick oxide film 171 is created. At the same time, a p⁺ impurity region 33 is formed as a channel cutting layer in the area where the boron ions have been implanted.

As shown in FIG. 53, after the silicon nitride film 181 is removed, photoresist 4 is formed only in the area for creating a PMOS transistor. Using the photoresist film 4 as a mask, boron ions are implanted in the monocrystalline silicon layer 39 in the area to create an NMOS transistor.

A p ^- region 34 is thus formed, as shown in FIG. 54. Using the photoresist film as mask 4 , which is formed only in the NMOS transistor region, phosphorus ions (P) are implanted in the monocrystalline silicon layer 39 in the PMOS transistor region. The amount of boron and phosphorus ions to be implanted at this time is determined as a function of the threshold voltages that are to be set for the NMOS and PMOS transistors.

As shown in FIG. 55, an n ^- region 35 is created. After the removal of the photoresist film 4 , the oxide film 17 is removed. Then, a gate oxide film 51 is created. The thickness of the gate oxide film is several 10 nm. A polycrystalline silicon layer for a gate electrode with a thickness of approximately 300 nm is formed by a CVD method. The polycrystalline silicon layer is doped with impurities in order to lower its resistance. Then the polycrystalline silicon layer is selectively removed using a patterned photoresist film 44 as a mask. This creates a gate electrode 61 .

As shown in Fig. 56, photoresist 42 is formed only in the PMOS transistor region. Using photoresist films 42 and 44 as masks, arsenic ions (As) are implanted in the source and drain formation regions of an NMOS transistor.

As shown in Fig. 57, a photoresist film 4 is formed only in the area of the NMOS transistor, in which an n + impurity region 36 is created as the source and drain region. Using the photoresist film 4 as a mask, boron ions (B) are implanted in the source / drain formation region of a PMOS transistor.

Finally, a p⁺ impurity region 37 is created as the source / drain region, as shown in FIG. 58. After the removal of the photoresist film 4 , an interlayer insulating film 7 is formed on the entire surface. After the interlayer insulating film 7 has been provided with contact holes, a metal wiring layer 8 is created which is electrically in contact with the respective source and drain regions. In a device with an SOI structure, a so-called multi-layer wiring structure is usually created by forming additional insulation and wiring layers.

A manufacturing method for a semiconductor device having an SOI structure has been described. In Figs. 59 and 60, the result of the investigation of the SOI crystal properties is shown in this fabrication process. FIG. 59 shows the investigation result of the inventor on the surface of the monocrystalline silicon layer 3 in the process shown in FIG. 48. As described above, crystal defects are hardly observed except for sub-grain boundaries 31 , the position of which is controlled to be under the anti-reflection films. The density of the crystal defects is equal to or less than 10 ⁴ cm ^-2 and is therefore approximately the same as that of a conventional size monocrystalline silicon substrate. In contrast, FIG. 60 shows the observation result on the surface of the monocrystalline silicon layer 3 immediately after the oxide film 17 has been formed on the monocrystalline silicon layer 3 by the process shown in FIG. 49. As can be seen from FIG. 60, a plurality of crystal defects 19 , which extend in a certain direction starting from the sub-grain boundaries 31 , are newly generated.

The inventors have determined that such new crystal defects are generated both in the heat treatment (annealing in a non-oxidizing atmosphere) immediately after the formation of a monocrystalline silicon layer and in the oxidation of the monocrystalline silicon layer starting from the sub-grain boundaries or the grain boundaries. The defects as shown in Fig. 60 are generated along the orientation <110 <(or <111 <). It has been shown that more defects are generated in the oxidation of the monocrystalline silicon layer than in the heat treatment. The defects are formed in a line shape as shown in FIG. 60. The defect density is about 3 _* 10 ⁵ cm ^-2 when the layer is subjected to oxidation and about 10 ^-4 cm ^-2 when the layer is heat treated. This shows that the new crystal defects result from the movement of point defects, e.g. B. excess silicon or lattice defects that exist in the grain boundaries or sub-grain boundaries, immediately after the formation of the monocrystalline silicon layer in conjunction with stresses that are exerted during the oxidation or annealing process (defects that exist as point defects or form layers of layered dislocation defects). The occurrence of such crystal defects leads to significantly non-uniform properties of the active components. For example, the threshold voltage (Vth) or current driving ability, etc. of a MOS transistor is increased by the existence of crystal defects. Due to the formation of such defects across the channel area, the impurities diffuse along the defect, which leads to a critical defect in the source / drain line. This causes the MOS transistor to malfunction. It is therefore necessary to prevent the formation of such defects in order to achieve a higher performance of the active components with an SOI structure.

(A), (B) and (C) in Fig. 61 are plan views corresponding to Figs. 49, 52 and 58, respectively. Figs. 49, 52 and 58 show cross sections along lines XX in (A), (B) and (C) of Fig. 61. As shown in (A) of Fig. 61, it is observed that a large number of crystal defects 19 are newly formed which extend in a fixed direction from the sub-grain boundaries 31 . Subsequently, when a thick insulating film 171 is formed in an area surrounding a monocrystalline silicon layer 39 in a MOS transistor area, as shown in (B) of Fig. 61, the sub-grain boundaries are introduced into the insulating oxide film. However, the crystal defects 19 grow through a heat treatment and remain in the monocrystalline silicon layer 39 in the MOS transistor region. After a gate electrode 61 and an n + impurity region 36 and a p + impurity region 37 have finally been formed as source / drain regions, the crystal defects 19 remain and extend in the source / drain regions and the channel region .

Moreover, the inventors have found that new crystal defects 19 similar to those shown in Fig. 60 are generated with the sub-grain boundaries 31 as the starting point, when the monocrystalline silicon layer 3 immediately polished to reduce the steps and indentations in the surface after the formation of the monocrystalline silicon layer 3 as shown in Fig. 48. These defects are not observed before the surface of the monocrystalline silicon layer is polished. Therefore, they are created during polishing. The defects not only increase the non-uniformity of the component properties, such as. B. current driving ability, threshold voltage, etc., but also cause critical defects such as the increase in leakage current.

As has been described above, the generated ones Crystal defects extending from the sub-grain boundaries and remain in the semiconductor device with SOI structure, too following effects. If e.g. B. integrated memory cells in the Semiconductor devices with an SOI structure cannot be formed all memory cells meet the same characteristic. The Operating speed of the memory cells is not uniform, and there are lower memory cells Operating speed as the specification indicates. The worsens the production yield for the Semiconductor devices.

If e.g. B. the device is a memory in a computer should be used, it will be because of the differences in the Characteristic curves of the various transistors impossible read the stored data from the memory exactly. Although the Memory cells are functional to a certain extent Efficiency low and the operating speed of Products with such facilities are low.  

EP 0 179 719 A1 describes a production method for a Semiconductor device known in which a silicon dioxide layer is formed on an SOS substrate. On the oxidation layer becomes a recrystallized, monocrystalline semiconductor layer formed, areas of the monocrystalline semi-lead The layer can be removed selectively, in which mechanical chip due to a mismatch in the atomic structure are. This creates island-shaped areas. On the in Self-shaped monocrystalline semiconductor layers can be active Components are formed.

It is therefore an object of the present invention to provide a method to provide for the production of a semiconductor device with which a semiconductor device can be manufactured in which in there are no sub-grain boundaries in an active area, ins crystal defects in an SOI structure are said to be special be changed.

This problem is solved by a method with the features of claim 1.

Preferred embodiments of the invention result from the Subclaims.  

In the manufacturing method according to the invention for the Semiconductor device becomes the active component in the island-shaped monocrystalline silicon layer is formed, and therefore the part the monocrystalline silicon layer corresponding to the area higher temperature in the temperature distribution during melting selectively removed before the island-shaped monocrystalline Silicon layer is subjected to a predetermined treatment. Before e.g. B. the monocrystalline silicon layer Subjected to heat treatment or the surface of the monocrystalline Silicon layer is polished, the area of monocrystalline silicon layer corresponding to the area higher Removed temperature in the temperature distribution during melting. This area corresponds to the monocrystalline silicon layer the area of higher temperature in the temperature distribution at Melting corresponds to the area where sub-grain boundaries or grain boundaries exist. After the area in which sub-grain boundaries or Grain boundaries exist, has been removed, becomes an active one Component in the island-shaped monocrystalline silicon layer educated. Therefore, in the course of heat treatment or during Polishing does not produce new crystal defects caused by existence caused by sub-grain boundaries or grain boundaries. Consequently vary the properties of the active components used in the island-shaped monocrystalline silicon layer are formed, Not.

As described above, the area of monocrystalline Silicon layer with sub-grain boundaries or grain boundaries removed, and therefore, there is no way that new crystal defects can be created if there is an oxidation  or heat treatment is carried out. Therefore a Non-uniformity of the properties of different components or their malfunction in a semiconductor device with SOI structure be significantly suppressed. By removing the Area of a monocrystalline silicon layer with sub-grain boundaries or grain boundaries, no new defects are created if the monocrystalline semiconductor layer is polished to the steps and To reduce indentations in their surface. Therefore a monocrystalline silicon layer with a flat and flat Surface to be formed on an insulator layer and it is therefore possible to use a higher power semiconductor device Achieve SOI structure.

The following is a description of exemplary embodiments with reference to the figures. From show the figures

Fig. 1-9 cross sections of successive steps of a manufacturing method for a semiconductor device according to a first embodiment;

Fig. 10 plan views (A), (B) and (C) corresponding to Figures 1, 2 and 9.

FIG. 11 shows a partial cross section of the cross-sectional structure of the semiconductor device shown in FIG. 9;

Fig. 12-17 cross sections of successive steps of a manufacturing method for a semiconductor device according to a second embodiment;

Fig. 18-22 cross sections of successive steps of a manufacturing method for a semiconductor device according to a third embodiment;

Fig. 23-25 cross sections of successive steps of a polishing method according to a first embodiment in a manufacturing method of a semiconductor device;

Fig. 26-27 cross sections of successive steps of a polishing method according to a second embodiment in a manufacturing method of a semiconductor device;

Fig. 28-33 cross sections of successive steps of a polishing method according to a third embodiment in a manufacturing method of a semiconductor device;

Fig. 34-39 cross sections of successive steps of a polishing method according to a fourth embodiment in a manufacturing method of a semiconductor device;

FIG. 40 is a cross-section of the concept for a vigorous polishing method which is used in a polishing process in the manufacturing method for a semiconductor device;

FIG. 41 is a schematic diagram of a manufacturing method for a semiconductor device;

Figure 42 is a perspective cross-section of a typical manufacturing process in a method Schmelzrekristallisations with an antireflection film.

Fig. 43-45 cross sections of successive steps in a Schmelzrekristallisationsverfahren;

Figure 46 is a graph showing the temperature distribution in an unmelted polycrystalline silicon layer at a Schmelzrekristallisationsverfahren.

FIG. 47 is a graph showing the measurement result for the surface roughness of a monocrystalline silicon layer, which is formed by a Schmelzrekristallisationsverfahren;

Fig. 48-58 cross sections of successive steps of a manufacturing method for a semiconductor device;

FIG. 59, immediately after it has been produced by a Schmelzrekristallisationsverfahren with an anti-reflection film is a plan view schematically showing the state of the surface of a monocrystalline silicon layer;

Figure 60 is a plan view schematically showing the state of the surface of a monocrystalline silicon layer after a thermal oxide film was on the surface of the monocrystalline silicon layer which has been formed by a Schmelzrekristallisationsverfahren with an antireflection film formed. and

Fig. 61 are plan views (A), (B) and (C) corresponding to FIGS. 49, 52 and 58, respectively.

Embodiment 1

In Fig. 1 the state of a monocrystalline silicon layer of SOI structure is shown immediately after it has been formed by a Schmelzrekristallisationsverfahren using an anti-reflection film. An insulator layer 2 made of SiO ₂ is formed on a monocrystalline silicon substrate 1 . A monocrystalline silicon layer 3 is created on the insulator layer 2 . The monocrystalline silicon layer 3 has sub-grain boundaries 31 .

As shown in Fig. 2, a photoresist film 41 is applied on the monocrystalline silicon layer, which is patterned by a photolithography process. The monocrystalline silicon layer is selectively removed using the photoresist film 41 as a mask, and island-shaped monocrystalline silicon layers 32 are formed. The selective removal of the monocrystalline silicon layer is carried out by removing only the regions which contain sub-grain boundaries 31 . In other words, the high temperature portion is removed in the recrystallization process, that is, only the area under the anti-reflection films 14 , as shown in FIG. 38. The removal of the monocrystalline silicon layer with the sub-grain boundaries 31 in this way prevents further crystal defects with the sub-grain boundaries from being generated as starting points if a heat treatment or oxidation is carried out in subsequent steps for producing active components.

Then, a photoresist film 42 is formed only in the area for creating a PMOS transistor, as shown in FIG. 3. Boron ions (B) are implanted in the side walls of the island-shaped monocrystalline silicon layers 32 in the formation area for an NMOS transistor, using the photoresist films 41 and 42 as masks. The ion implantation is accomplished by inclined injecting boron ions with the substrate rotated as shown in FIG. 3. The distance between the NMOS transistor formation region and the PMOS transistor formation region is shown schematically in FIG. 3. However, it is necessary to consider shading when determining the placement of areas for forming active devices when oblique implantation of ions as described above is used with the substrate rotating. If e.g. B. with a monocrystalline silicon layer with a thickness of 0.5 µm using a photoresist film with a thickness of 1 µm as a mask oblique implantation of ions at an angle of 45 °, the distance between the NMOS transistor formation region and the PMOS should - The transistor formation area is 2.5 µm or more.

As shown in FIG. 4, the photoresist film 41 on the monocrystalline silicon layer 32 in the NMOS transistor formation region is removed. A p⁺ impurity region 33 is formed as a channel cut-off layer in the region in which boron ions are implanted. Boron ions (B) are implanted only in the island-shaped monocrystalline silicon layers 32 of the NMOS transistor formation region.

As shown in FIG. 5, only the surfaces of the island-shaped monocrystalline silicon layers 32 of the PMOS transistor formation region are exposed and phosphorus ions (P) are implanted. The amount of boron and phosphorus ions to be implanted at this time is determined as a function of the threshold voltages that are to be set for the NMOS or PMOS transistor. A p ^- region 34 and an n ^- region 35 are thus formed.

As shown in FIG. 6, an oxide film 5 is formed on the monocrystalline silicon layer by thermal oxidation. The surface of the monocrystalline silicon layer is subjected to a thermal oxidation treatment at this time, but no new crystal defects are formed because the area with the sub-grain boundaries has been removed. Then, a polycrystalline silicon layer 6 for a gate electrode is formed on the entire surface. The resistance of the polycrystalline silicon layer 6 is reduced by doping with impurities.

As shown in FIG. 7, the polycrystalline silicon layer 6 and the oxide film 5 are patterned using the photoresist film 44 as a mask to provide a gate electrode 61 and a gate oxide film 51 . Using the photoresist film 42 covering the PMOS transistor formation region as a mask, phosphorus ions (P) are implanted in the source and drain region of an NMOS transistor.

As shown in FIG. 8, using a photoresist film 4 covering the NMOS transistor formation area as a mask, boron ions (B) are implanted in the source and drain formation area of a PMOS transistor. Then, heat treatment is carried out at a temperature of about 900 ° C for about an hour to fix crystal defects generated by the ion implantation and to activate the impurities. A p⁺ impurity region 37 is thus formed as the source and drain region of the PMOS transistor and an n⁺ impurity region 36 as the source and drain region of the NMOS transistor. As indicated above, oxidation treatment or heat treatment is carried out in the active device formation process while avoiding the formation of further crystal defects, so that the properties of the active devices are improved. At this time, the density of the crystal defects existing in the monocrystalline silicon layer is 10 ⁴ cm ^-2 or less, and the generation of new crystal defects due to the heat or oxidation treatment is significantly suppressed.

As shown in FIG. 9, an interlayer insulating film 7 and a metal wiring layer 8 are formed.

The photoresist film 4 is formed directly on the monocrystalline silicon layer in the process shown in Figs. 4 and 5, but the photoresist film 4 can also be formed after the surface of the monocrystalline silicon layer has been covered with a film made of SiO ₂ exists to protect the surface of the monocrystalline silicon layer. The SiO ₂ film can be a thermal oxidation film or a CVD film.

(A), (B) and (C) in Fig. 10 are plan views corresponding to Figs. 1, 2 and 9, respectively. Figs. 1, 2 and 9 show cross sections along lines XX in (A), (B) and . (C) of FIG. 10. As shown in Fig. is shown at (a) 10, 3 sub-grain boundaries 31 are contained in a monocrystalline silicon layer. As shown in Fig. 10 at (B), an island-shaped monocrystalline silicon layer 32 is formed. The patterning of the island-shaped monocrystalline silicon layer 32 has a photolithography process. A heat treatment at a temperature of 200 ° C or less, such as. B. the photolithography process, does not produce crystal defects due to sub-grain boundaries. The inventors have determined that crystal defects are generated due to sub-grain boundaries when e.g. B. a heat treatment is carried out at 600-700 ° C or more, that is, when the formation of a layer is carried out by a CVD method or a thermal oxidation. Then, a gate electrode 61 is formed, as shown in Fig. 10 at (C), an n⁺ impurity region 36 and a p⁺ impurity region 37 are created as source / drain regions, and the generation of further crystal defects becomes suppressed.

Fig. 11 shows a cross-sectional view showing the structure under an n-channel MOS transistor on the right side of Fig. 9 in detail. As shown in FIG. 11, 1 n⁺ impurity regions 136 are formed in a monocrystalline silicon substrate as source / drain regions. Between these two n⁺ impurity regions 136 , a gate electrode 161 is formed on the monocrystalline silicon substrate 1 with a gate oxide film 151 in between. A metal wiring layer 108 is formed in an insulator layer 2 so that it is connected to the n⁺ impurity region 136 . An n-channel MOS transistor with a p ^- region 34 , an n + impurity region 36 , a gate oxide film 51 and a gate electrode 61 is formed on the insulator layer 2 .

Embodiment 2

In Fig. 12 illustrates the state immediately after a monocrystalline silicon layer 3 has been formed.

As shown in Fig. 13, using a photoresist film 43 patterned by a photolithography method as a mask, at least the part of the monocrystalline silicon layer in which sub-grain boundaries exist is removed. Island-shaped monocrystalline silicon layers 32 are thus formed. The selective removal of the monocrystalline silicon layer is similar to the process shown in FIG. 2.

As shown in FIG. 14, after the removal of the resist film 43 , an oxide film (silicon oxide film) 9 and a silicon nitride film 10 are sequentially formed. The thickness of the oxide film 9 is approximately 50 nm, the thickness of the silicon nitride film 10 approximately 100 nm. The patterned photoresist film 41 is only created in the area of formation of active components.

As shown in Fig. 15, the silicon nitride film, silicon oxide film and the monocrystalline silicon layer using the photoresist film 41 used as mask is selectively removed, and there are provided a silicon nitride film 101, a silicon oxide film 91 and an island-shaped monocrystalline silicon layer 38. A photoresist film 42 is formed to cover the island-shaped monocrystalline silicon layer 38 in the PMOS transistor formation region. Using the photoresist films 41 and 42 as masks, boron ions (B) are implanted obliquely in the side walls of the island-shaped monocrystalline silicon layer 38 in the PMOS transistor formation region. This process corresponds to the process of the first embodiment shown in FIG. 3.

As shown in Fig. 16, heat treatment is carried out in an oxidizing atmosphere after the photoresist films 41 and 42 are removed. A thick oxide film 92 is formed on the side walls of the island-shaped monocrystalline silicon layers 38 . In the NMOS transistor formation region, a p⁺ impurity region 33 is formed as a channel clipping layer within the silicon oxide film 92 . When the island-shaped monocrystalline silicon layer is subjected to a heat treatment or oxidation treatment with at least a part of the monocrystalline silicon layer having the sub-grain boundaries removed as shown in Fig. 11, no new crystal defects are formed with the sub-grain boundaries as starting points. The thickness of the silicon oxide film 92 formed on the side walls of the island-shaped monocrystalline silicon layer 38 should be sufficiently thick that parasitic transistors formed on the side walls do not work in the operating voltage range of the MOS transistors. The thickness of the silicon oxide film 92 should e.g. B. are in the range between 200 and 300 nm.

The manufacturing process shown in FIG. 16 corresponds to the process shown in FIG. 52 in connection with the associated example, and LOCOS insulation (local oxidation of silicon) is used to isolate regions of active components. In the case of the LOCOS insulator structure shown in Fig. 52, the parts of the monocrystalline silicon layer with sub-grain boundaries have not been removed, and a thick insulating oxide film has been created by a heat treatment. In contrast, in the case of the LOCOS insulating structure shown in Fig. 16 as an embodiment of the present invention, a thick oxide film is formed by thermal oxidation after the part of the monocrystalline silicon layer with sub-grain boundaries has been removed. In other words, the side walls of the island-shaped monocrystalline silicon layer are thermally oxidized.

Finally, as shown in Fig. 17, the active devices and metal wirings are formed by the same steps as in an ordinary CMOS transistor.

As described above, a manufacturing method for a semiconductor device according to the present invention is a manufacturing method for a semiconductor device having a mesa insulation as a structure for isolating device formation regions ( Figs. 1-9) and a manufacturing method for a semiconductor device with a SOI structure using LOCOS insulation ( Fig. 12-17) can be used.

Embodiment 3

Figs. 18-22 show cross sections of successive steps of a manufacturing method for a semiconductor device according to another embodiment of the invention, which is applied to the production of a semiconductor device of SOI structure, using the LOCOS isolation.

Fig. 18 shows the state immediately after a monocrystalline silicon layer 3 is formed by a melt recrystallization method using an anti-reflection film.

As shown in FIG. 19, using a photoresist film 43 patterned by a photolithography method as a mask, the monocrystalline silicon layer having sub-grain boundaries 31 is selectively removed. Island-shaped monocrystalline silicon layers 32 are thus formed.

As shown in FIG. 20, after the removal of the photoresist film 43 , an oxide film 9 with a thickness of about 50 nm and a silicon nitride film 10 with a thickness of about 100 nm are successively formed on the island-shaped monocrystalline silicon layer 32 . The thickness of the oxide film 9 is approximately 50 nm, the thickness of the silicon nitride film 10 is approximately 100 nm. A photoresist film 41 is only created in the region for forming active components.

As shown in FIG. 21, the silicon nitride film 10 is selectively removed using the photoresist film 41 as a mask, and a silicon nitride film 102 is created. A photoresist film 42 is then formed in order to cover the island-shaped monocrystalline silicon layer 32 only in a PMOS transistor formation region. Boron ions (B) are implanted using the photoresist films 41 and 42 as masks. Boron ions are thus implanted in the side walls of the island-shaped monocrystalline silicon layer 32 in an NMOS transistor formation region.

As shown in Fig. 22, heat treatment is carried out in an oxidizing atmosphere after the photoresist films 41 and 42 are removed. In the NMOS transistor formation region, a p⁺ impurity region 33 is formed as a channel cut-off layer on the side walls of the island-shaped monocrystalline silicon layer 32 , while thick oxide films 93 are created on the side walls of the island-shaped monocrystalline silicon layers 32 in the PMOS and NMOS transistor formation regions. The island-shaped monocrystalline silicon layer with LOCOS insulating structure with substantially the same structure as shown in Fig. 16 is formed with a substantial shape difference of the insulating oxide films. Active devices are formed by the same steps as in the usual manufacturing process for a CMOS transistor.

In the above-described embodiments, after a monocrystalline silicon layer has been formed, the area with Subgrain borders almost completely removed before one Heat treatment or oxidation treatment is carried out, and the The formation of further crystal defects is prevented. The removal of at least part of the monocrystalline silicon layer in the The area with the sub-grain boundaries, however, allows education to suppress further crystal defects even if subsequently heat treatment or oxidation treatment is carried out.

Cases are described in the above-described embodiments in which a manufacturing method according to the invention a method for creating a monocrystalline silicon layer is applied using an anti-reflection film. As long as a method of forming a temperature distribution in molten silicon used and a monocrystalline Silicon layer executed by recrystallization exist Subgrain boundaries or grain boundaries in the range corresponding to High temperature section in the temperature distribution at  Melting process. Therefore, the application of an inventive Manufacturing process to other manufacturing processes for a Semiconductor device with an SOI structure using a Melt recrystallization process lead to similar effects.

Although in the above-described embodiments Manufacturing process has been described in the active Devices on a single monocrystalline silicon layer formed, the present invention can also be applied to a Method for producing a three-dimensional circuit structure are used in the active components in a multilayer monocrystalline silicon layer are formed.

In accordance with a manufacturing method for a semiconductor device according to a further aspect of the present invention, the surfaces of the island-shaped monocrystalline silicon layers are leveled by polishing after that part of the monocrystalline silicon layer with the sub-grain boundaries has been selectively removed. The polishing process is e.g. B. between the processes shown in FIGS. 5 and 6, in FIGS. 13 and 14 and in FIGS. 19 and 20. The surfaces of the island-shaped monocrystalline silicon layers are polished after that part of the monocrystalline silicon layer with the sub-grain boundaries has been selectively removed in each of the cases. Therefore, no further crystal defects are generated by the polishing, which start from the sub-grain boundaries. A polishing method applicable to a semiconductor device manufacturing method according to the present invention will now be described.

Embodiment A

As shown in Fig. 23, a silicon oxide film 11 is formed which covers the island-shaped monocrystalline silicon layer 32 , the regions of which have been removed with sub-grain boundaries. The thickness of the silicon oxide film 11 is approximately 300 nm.

Then, as shown in Fig. 24, the silicon oxide film 11 is subjected to isotropic etching, and sidewall silicon oxide films 111 are formed on the sidewalls of the island-shaped monocrystalline silicon layer. The height of the sidewall silicon oxide film 111 can be controlled by changing the etching time. In the state shown in Fig. 24, vigorous polishing is carried out with the sidewall silicon oxide films 111 formed on the side walls of the island-shaped monocrystalline silicon layers 32 serving as stoppers for the polishing process. As a result, an island-shaped monocrystalline silicon layer 32 with a uniform thickness can be created. The state after this polishing is shown in Fig. 25.

A film is formed on the side walls of the island-shaped monocrystalline silicon layer 32 , which acts as a stopper to increase the accuracy of the polishing process, as described above. The substance that forms the film is preferably composed of a substance having a lower polishing rate than that of the substance that forms the island-shaped monocrystalline silicon layer. The most suitable material for the film is silicon oxide. The reason for this is that the silicon oxide film is made of the same material as the plate with which the vigorous polishing is carried out, its polishing rate is very low and the material is consistent with the process of forming active devices in subsequent steps.

Embodiment B

Another approach is a polishing process that is shown in FIGS. 26 and 27 as another embodiment to improve polishing accuracy. In the previous embodiment, a method for polishing the island-shaped monocrystalline silicon layer itself is used. In such a process, the polishing must be carried out very carefully so that the island-shaped monocrystalline silicon layer does not go off completely or partially and leaves scratches on the surface. With the island-shaped monocrystalline silicon layer originally having a thickness of approximately 0.55 μm, it is difficult to polish the entire surface of the wafer with high accuracy. Therefore, a polycrystalline silicon layer 12 is formed on the entire surface before the polishing process, as shown in FIG. 26. The thickness of the polycrystalline silicon layer 12 is greater than the thickness of the island-shaped monocrystalline silicon layer 32 . As shown in Fig. 27, the polycrystalline silicon layer 12 is then polished by a vigorous polishing process. The island-shaped monocrystalline silicon layer 32 is polished using the sidewall silicon oxide film 111 as a stopper, thereby creating a uniform island-shaped monocrystalline silicon layer 32 with a smooth surface. This method can prevent the island-shaped monocrystalline silicon layer from coming off during the polishing process. The polycrystalline silicon layer formed on the island-shaped monocrystalline silicon layer also acts as a necessary aid for increasing the polishing accuracy. Therefore, an island-shaped monocrystalline silicon layer, which is uniform over the entire surface of the wafer and has a smooth surface, can advantageously be formed. After the polishing process, the polycrystalline silicon layer fills the space between the island-shaped device formation regions, and therefore the leveling effect is effective for the entire surface on the wafer. The polycrystalline silicon layer has only been described for the purpose of illustration. However, similar effects can be achieved by any layer that has a similar polishing rate as the island-shaped monocrystalline silicon layer.

Embodiment C

Figs. 28-33 show partial cross sections of a manufacturing method of a semiconductor device of SOI structure, when a stop material is used during the polishing process, which fills up the space between the island-shaped monocrystalline silicon layers.

As shown in FIG. 28, the island-shaped monocrystalline silicon layers each have an n ^- region 35 and a p ^- region 34 . p⁺ impurity regions 33 are formed as channel cut-off layers on opposite sides of the p ^- region 34 .

As shown in Fig. 29, a silicon oxide film 11 is formed which covers the island-shaped monocrystalline silicon layers. A photoresist film 4 is created on the silicon oxide film 11 .

As shown in FIG. 30, the resist film 4 and the silicon oxide film 11 are removed by an etching back process. A silicon oxide film 112 , which acts as a stop material during polishing, thus fills the space between the island-shaped monocrystalline silicon layers.

As shown in FIG. 31, the surface of the island-shaped monocrystalline silicon layer is uniformly polished and flattened using the silicon oxide film 112 as a stopping material in the polishing.

As shown in Fig. 32, an oxide film 5 and a polysilicon layer 6 for a gate electrode are formed on the entire surface. The polycrystalline silicon layer 6 is doped with impurities in order to lower its resistance.

As shown in Fig. 33, selective etching by a photolithography method enables a gate electrode 61 and a gate oxide film 51 to be formed on the island-shaped monocrystalline silicon layers. At this point, the area between the island-shaped monocrystalline silicon layers has already been filled with the silicon oxide film 112 , which is used as a stop material in the polishing. The rest of the polysilicon layer is not left behind in an isotropic etching process to form the gate electrode 61 on the side walls of the island-shaped monocrystalline silicon layer.

Embodiment D

Figs. 34-37 show partial cross sections of successive steps of another embodiment of a manufacturing method for a semiconductor device with a SOI structure, if the space is filled up between the island-shaped monocrystalline silicon layers with a stopping material, which is used in a polishing process.

As shown in FIG. 34, a monocrystalline silicon layer 3 with sub-grain boundaries 31 is formed on an insulating layer 2 .

As shown in Fig. 35, the part of the monocrystalline silicon layer having the sub-grain boundaries is removed, and as a result, an island-shaped monocrystalline silicon layer 32 is created. At this time, a part that is to form an active component can be created as an island so that no sub-grain boundaries are contained therein.

As shown in FIG. 36, a polycrystalline silicon layer 12 is formed to cover the island-shaped monocrystalline silicon layers 32 and to fill the space between them. A thickness of 500 nm or more is sufficient for the polycrystalline silicon layer 12 . As defined by the broken line in FIG. 36, the surface of the island-shaped monocrystalline silicon layer 32 is polished to a desired depth from the side of the polycrystalline silicon layer 12 .

An island-shaped monocrystalline silicon layer 321 with a smooth and uniform surface is thus formed, as shown in FIG. 37. A polycrystalline silicon layer 121 fills the space between the island-shaped monocrystalline silicon layers 321 . The polycrystalline silicon layer 121 is thus used as a stopping material during polishing. Crystal defects due to sub-grain boundaries are not generated in this process, and the monocrystalline silicon layer is not lifted off by the polishing process.

Active components are then formed by a conventional process, as shown in FIG. 38. Although Figure 38 shows LOCOS isolation. The example of a transistor formation means, instead of LOCOS isolation can also be a mesa isolation can be used. FIG. 39 shows a top view of the structure shown in FIG. 38. As shown in FIGS. 38 and 39, the polycrystalline silicon layer 121 exists in the source or drain region of a transistor. However, if the polycrystalline silicon layer 121 is arranged such that it is not formed in the channel region of the transistor, no influence is exerted on the properties of the component. If all of the device formation regions are formed from single crystal sections, there is no problem at all. But even if a polycrystalline silicon layer 121 exists in the portion of the source / drain region, as shown in Figs. 38 and 39, it is possible to form transistors with excellent properties by taking the diffusion of the impurities into account.

Fig. 40 is a cross section schematically showing a vigorous polishing process used in the above embodiment. This vigorous polishing process uses a plate 300 made of a material that is harder than the silicon to be polished. A wafer 100 as a monocrystalline silicon substrate with an SOI structure is supported by a rotatably mounted plate 400 . The surface of the monocrystalline silicon layer formed on the wafer is polished by pressing the wafer plane to be polished against the plate 300 while the wafer 100 is being rotated. In this case, e.g. B. colloidal silicate material used as an abrasive. Silicon oxide, for example, is used for the plate 300 . A metal can also be used for the plate, provided that contamination of the monocrystalline semiconductor layer can be avoided during polishing. In accordance with the vigorous polishing process shown in Fig. 40, a monocrystalline silicon layer having an excellent leveled surface can be formed by using a film as a polishing aid which is different in polishing rate from the monocrystalline silicon layer. However, it is desirable to use a material whose polishing speed is equal to or almost the same as the polishing rate of the monocrystalline silicon layer in order to level the surface even better.

The essence of the manufacturing method for a semiconductor device according to the present invention, which has been described in detail by the above-mentioned embodiment, is summarized in the manufacturing steps which are shown schematically in FIG. 41. As shown in Fig. 41, a non-monocrystalline silicon layer formed on an insulator layer is heated, melted to achieve a predetermined temperature distribution, and recrystallized into a single crystal (step 501). The monocrystalline semiconductor layer corresponding to the high temperature region in the temperature distribution during melting is selectively removed before the obtained monocrystalline semiconductor layer is subjected to a heat treatment (step 502). Then active components are formed in the resulting island-shaped monocrystalline semiconductor layers (step 504). At this point, the surface layers of the island-shaped monocrystalline semiconductor layers can be polished before these active devices are formed to remove them, and the surfaces can be flattened to reduce the steps and indentations of the surfaces of the island-shaped monocrystalline semiconductor layers, which are responsible for non-uniform device properties may be responsible, or to improve device properties by reducing the thickness of the island-shaped monocrystalline semiconductor layers (step 503).

As has been described above, according to the invention Manufacturing process that area of monocrystalline Silicon layer removed, the sub-grain boundaries or grain boundaries  having. Therefore, no new crystal defects are possible if the Process for the formation of active components an oxidation or Heat treatment is carried out. It can be used in one Semiconductor device with SOI structure the unevenness of the active components or their malfunction significantly suppressed will. By previously removing the area of the monocrystalline silicon layer, the grain boundaries or Sub-grain boundaries will never form new defects, though the monocrystalline silicon layer is polished around the steps and reduce indentations in their surface. Therefore a monocrystalline silicon layer with a uniform and flat Surface to be formed on an insulator layer and it is therefore possible with a semiconductor device with an SOI structure to achieve higher performances.

Claims (24)

1. Manufacturing method for a semiconductor device with an active region in a silicon layer, which is formed on an SiO₂ layer, characterized by the steps:
Forming a monocrystalline semiconductor layer ( 3 ) by heating and melting a non-monocrystalline silicon layer ( 13 ) which is formed on the SiO₂ layer ( 2 ),
Melting the non-monocrystalline silicon layer with a temperature distribution having regions of higher and lower temperature,
Forming an island-shaped monocrystalline silicon layer ( 32 ) by selectively removing the portion of the monocrystalline silicon layer that was exposed to the higher temperature region during melting, and
Forming an active component ( 61 ) on the island-shaped monocrystalline silicon layer. 2. Manufacturing method according to claim 1, characterized in that the step of forming the monocrystalline silicon layer ( 3 ) comprises melting a non-monocrystalline silicon layer ( 13 ) by irradiation with a laser ( 70 ). 3. Manufacturing method according to claim 1 or 2, characterized in that the temperature distribution is achieved by the non-monocrystalline silicon layer ( 13 ), on which an anti-reflection film ( 14 ) is selectively formed, is irradiated with a laser ( 70 ). 4. The manufacturing method according to claim 3, characterized in that the step of forming the island-shaped monocrystalline silicon layer ( 32 ) comprises forming the island-shaped monocrystalline silicon layer ( 32 ) by selectively removing the monocrystalline silicon layer ( 3 ) according to the position under the anti-reflection film ( 14 ) . 5. Manufacturing method according to one of claims 1 to 4, characterized in that the step of forming the island-shaped monocrystalline silicon layer ( 32 ) comprises the selective etching of a monocrystalline silicon layer with a sub-grain boundary ( 31 ). 6. Manufacturing method according to one of claims 1 to 5, characterized in that the step of forming an active component in the island-shaped monocrystalline silicon layer comprises the formation of a field effect transistor ( 61 ) in the island-shaped monocrystalline silicon layer ( 32 ). 7. Manufacturing method according to one of claims 1 to 5, characterized in that the step of forming an active component in the island-shaped monocrystalline silicon layer
the formation of a component insulation layer ( 33 , 92 ; 93 ) on a side wall of the island-shaped monocrystalline silicon layer ( 32 ), and
the formation of an active component ( 61 ) in the region of the island-shaped monocrystalline silicon layer, which is surrounded by the component insulation layer. 8. The manufacturing method according to claim 7, characterized in that the step of forming a device insulating layer comprises forming a channel cut-off layer ( 33 ) on a side wall of the island-shaped monocrystalline silicon layer ( 32 ). 9. The manufacturing method according to claim 7 or 8, characterized in that the step of forming a component insulating layer comprises forming an insulating oxide film ( 92 ; 93 ) on a side wall of the island-shaped monocrystalline silicon layer ( 32 ). 10. Manufacturing method according to claim 9, characterized in that the step of forming the insulating oxide film ( 92 )
the sequential formation of an oxide film ( 91 ) and a nitride film ( 101 ) on the top surface of the island-shaped monocrystalline silicon layer ( 38 ), and
selectively oxidizing a sidewall of the island-shaped monocrystalline silicon layer using the nitride film as a mask. 11. A manufacturing method according to claim 9, characterized in that the step of forming the insulating oxide film ( 93 )
the formation of an oxide film ( 9 ) on the top surface and side wall of the island-shaped monocrystalline silicon layer ( 38 ),
the formation of a nitride film ( 102 ) on the oxide film and the top surface of the island-shaped monocrystalline silicon layer, and
comprises increasing the thickness of the oxide film on the side wall of the island-shaped monocrystalline silicon layer by using the nitride film as a mask by oxidation. 12. Manufacturing method according to one of claims 1 to 11, characterized in that
the step of forming an active device in the region of the island-shaped monocrystalline silicon layer, forming a gate oxide film ( 51 ) selectively on the top surface of the island-shaped monocrystalline silicon layer ( 32 ) and a gate electrode ( 61 ) on the gate oxide film, and
the formation of a source / drain region ( 36 ; 37 ) by embedding impurities in the island-shaped monocrystalline silicon layer using the gate electrode as a mask. 13. The manufacturing method according to claim 1, characterized in that the step of forming the island-shaped monocrystalline silicon layer comprises the formation of first and second island-shaped monocrystalline silicon layers ( 32 ) by selective removal of the monocrystalline silicon layer ( 3 ). 14. Manufacturing method according to claim 13, characterized in that the step of forming the island-shaped monocrystalline silicon layer
the formation of a silicon layer ( 34 ) of a first conductivity type by embedding impurities of a first conductivity type in the first island-shaped monocrystalline silicon layer, and
comprises the formation of a silicon layer ( 35 ) of a second conductivity type by embedding impurities of a second conductivity type in the second island-shaped monocrystalline silicon layer. 15. The production method according to claim 14, characterized in that the step of forming an active component in the island-shaped monocrystalline silicon layer, the formation of a field effect transistor of the second conductivity type in the silicon layer ( 34 ) of the first conductivity type, and
comprises the formation of a field effect transistor of the first conductivity type in the silicon layer ( 35 ) of the second conductivity type. 16. Manufacturing method according to one of claims 1 to 15, characterized by the step:
Flattening the surface of the island-shaped monocrystalline silicon layer by removing the surface layer of the island-shaped monocrystalline silicon layer by polishing. 17. The production method according to claim 16, characterized in that the step of leveling the surface of the island-shaped monocrystalline silicon layer
the formation of a polishing stop film ( 111 ) on a side wall of the island-shaped monocrystalline silicon layer ( 32 ), and
removing the surface layer of the island-shaped monocrystalline silicon layer to a predetermined thickness using the thickness of the polishing stopper film as a reference. 18. Manufacturing method according to claim 17, characterized in that the polishing rate of the polishing stop film ( 111 ) is lower than the polishing rate of the island-shaped monocrystalline silicon layer ( 32 ). 19. Manufacturing method according to claim 16, characterized in that the step of leveling the surface of the island-shaped monocrystalline silicon layer
the formation of a polishing stop film ( 111 ) on a side wall of the island-shaped monocrystalline silicon layer ( 32 ),
forming a polishing support layer ( 12 ) on the insulator layer to cover the island-shaped monocrystalline silicon layer and the polishing stopper film, and
comprises removing the surface layers of the polishing support layer and the island-shaped monocrystalline silicon layer to a predetermined thickness using the thickness of the polishing stopper film as a reference. 20. Manufacturing method according to claim 19, characterized in that
the polishing rate of the polishing stop film ( 111 ) is lower than the polishing rate of the island-shaped monocrystalline silicon layer ( 32 ), and
the polishing rate of the polishing support layer ( 12 ) is substantially equal to the polishing rate of the island-shaped monocrystalline silicon layer ( 32 ). 21. Manufacturing method according to one of claims 17 to 20, characterized in that the formation of the polishing stop film comprises the formation of stop films ( 112 ) in such a way that they fill the space between a plurality of island-shaped monocrystalline silicon layers. 22. The manufacturing method according to any one of claims 16 to 21, characterized in that the step of flattening the surface of the island-shaped monocrystalline silicon layers comprises rotating the surface of the island-shaped monocrystalline silicon layers while the surface is pressed onto a rigid body ( 300 ). 23. The production method according to claim 1 to 22, characterized in that the step of subsequent treatment of the island-shaped monocrystalline silicon layer ( 32 ) comprises heating the island-shaped monocrystalline silicon layer to a temperature above 600 ° C. 24. Manufacturing method according to one of claims 1 to 23, characterized in that a plurality of semiconductor devices, each having an active region in a silicon layer which is formed on a SiO₂ layer, are formed with:
Depositing the non-monocrystalline silicon layer ( 13 ) on the SiO₂ layer ( 2 ),
Treating the respective monocrystalline silicon layer in order to form an active component ( 61 ) on at least two island-shaped monocrystalline silicon layers.