DE4223999C1 - Digital multiplication circuit using canonically signed digit code - has multiplexer converted and added to two's-complement value to generate reduced partial products that are added - Google Patents

Abstract

The digital circuit has the multiplier represented in canonically signed digit (CSD) form and the multiplicand in 2's complement form. A particular feature of the CSD code is that each second line of the multiplication structure is zero. This halves the number of additions of partial products necessary to obtain a result. The circuit has a converter (3) for CSD code. The converter output is received by a stage (4) which adds a corrective digit and a partial product stage (2). The sign or most significant bit is handled by a switching stage (6). USE/ADVANTAGE - for multiplication of two binary numbers used with filter, signal processor, microprocessor or correlator. Reduces amount of hardware and delay time.

Description

State of the art

Existing concepts for multiplying binary numbers are based on the Summation of partial products of different values. In particular are here so-called "booth multipliers" or "modified booth multipliers", Call "Pezaris" and "Baugh and Wooley" multipliers. The treatment of signed dual numbers happens either through the use of different basic add or subtract cells or by adding correction factors (see e.g. Hwang, Kai: Computer Arithmetic, New York; Chichester; Brisbane; Singapore: John Wiley & Sons, 1979). Newer Publications build on these concepts and achieve z. B. by fast precarry generators (see Sinha, B.P .; Srimani, P.K .: Almost in parallel algoriths for binary multiplication and their implementation on systolic ar chitectures, IEEE, Transactions on Computers, Vol. C-38, 1989, pp. 424-431) high processing speeds. An extension of the booth structure consists of combining several bits into a block the code conversion (see Sam, H .; Gupta, A .: A generalized recoding of two's complement binary numbers and its proof with application in multiplier im Implementations, IEEE, Transactions on Computers, Vol. C-39, No. 8, 1990, pp. 1006-1015).

Critique of the state of the art

The concepts mentioned have the disadvantage that they have to be carried out by the Coding or by adding correction terms for implementation a signed multiplication in 2's complement the effort, calculated in transistors, above that of the simplest amount multipliers Embodiment lies.

problem

The object of the invention is to provide known digital multipliers of two binary numbers to develop in such a way that this reduces the hardware to wall and a reduced delay time compared to an amount Multiplier of the simplest embodiment is achieved. The one in claim 1 specified invention is based on the idea of the properties of CSD codes (canonically signed digit) that take advantage of two consecutive Make at least one is zero.  

Achievable advantages

The CSD code multiplier according to the invention has the property that by combining two partial products of the same value, which due to the property of the CSD code cannot both be equal to one, the number of adder inputs required for the partial products is approximately half conventional multipliers can be reduced. Fig. 2 shows two examples, which terms can be combined, thus leading to a reduced number of partial products. Furthermore, the other operations for obtaining a correct result are also listed, namely the CSD code conversion and the treatment of leading ones. The multiplicand and the result are interpreted in Fig. 2a) as unsigned dual number and in Fig. 2b) as signed 2-complement numbers. Accordingly, signed and mixed sign-amount multiplication and pure amount multiplication are possible. The CSD code generation can be carried out very quickly using the logic in FIG. 3, so that the CSD code multiplier can be used for partial multiplications. So-called "leading ones", which are generated in the 2's complement formation, can be added by a combinatorial logic shown in FIG. 4, which saves additional adders. The processing of negative multiplicants is achieved with minimal gate effort. All adders used are standard full or half adders.

With a little additional logic each further properties of the CSD Code multiplier can be easily achieved: integrated additions / sub tractions, switchover between amount and sign multiplications tion, integrated switchable rounding by adding another addition entry for each value to which the rounding can be carried out should. The structure is in both direct parallel and pipeline structures to implement. The structure is both for fixed point and with an addition logic can be used for floating point multipliers. The trouble-free use of CLA (carry look ahead) and CSA (carry save adder) structures allow one further acceleration of multiplication. The word length to be used is selectable up to a maximum with a multiplier executed. The Lengths of the operands can be chosen freely, but only result in ent Outstanding advantages for word lengths greater than 12 bits. It is still an advantage due to the reduced number of adders, lower power consumption a version in CMOS technology.

Compared to an unsigned amount multiplier, a CSD Code multiplier in a 32 by 32 bit version approx. 10% less transi to disturb. The total delay time is reduced by approximately 40% for the same Acceleration techniques.

Detailed description of the execution

The CSD code can be mathematically derived from a 2's complement number derive dimensions (cf. Reitwiesner, Georg W .: Binary arithmetic, in: Advances in Computers, New York; London: Academic Press, 1960, pp. 232-313):

under the condition

ξ _i ξ _i-1 = 0, αi ≦ λτβ (2)

The CSD code can be determined from the following recursion:

First of all, the initialization is carried out by

γ _{b -1} = X _{β -1} = 0 (3)

The actual recursion, starting with β up to α, takes place through

where X _{α +1 is} defined by

X _{α +1} = X _α (5)

In the following, this ternary code is split into the two variables ϕ _i and η _i , which are defined as follows:

Negative values of ξ _i are defined by

Fig. 2 shows an example of the multiplication in the CSD code. The property in equation (2) shows that at least every other line in the multiplication structure is zero. This means that two partial products of the same value can be combined, since both cannot be one at the same time. This essential feature of the invention means that the required number of transistors and the delay time of a CSD code multiplier are reduced from a certain word length.

The fact that this reduction occurs only after a certain word length setting results on the one hand from the generation of the CSD code and from one somewhat more complex calculation of a partial product compared to one conventional multiplier, since two bit positions are combined. A partial product is formed by

The formation of the partial products is shown in Fig. 1 (2). The partial products E _{i are} formed there with the inputs ϕ _i , η _i and m _i .

The generation of the CSD code is derived from the mathematical recursion equation (3) to (5). In this case, a parallel circuit with combinatorial elements was generated from a recursive structure, which was optimized with regard to the delay time and only grows with one NOR gate delay per added value. This circuit enables the use of the CSD code principle in fast parallel multipliers. The optimized result is shown in Fig. 3.

Two other special features characterize the CSD code multiplier: On the one hand, this is the processing of negative multiplier bits and, on the other hand, the processing of negative multiplicands, ie that the MSB (Most Significant Bit) m _MSB is 1 in 2's complement. The processing of negative multiplier torbits takes place in that all bits of the multiplicand m _{i are} negated, ie but also all digits up to the MSB of the result word (see FIG. 1 (4)), and a 1 is added at the location of the LSB (see Fig. 1 (5)). The inversion provides so-called "leading ones", which must be added correctly (see. Fig. 4 and Fig. 1 (4)). The regularity of these leading ones, namely that a maximum of every second line can be occupied and that the complete line above the MSB of the partial products is 1 (triangular structure in FIG. 2) can be used to design combinatorial logic, all of which leading ones accumulated and the amount bits leading to the adder field in Fig. 1. This problem can be solved independently of the multiplicand m _i . One level of this logic can be described equatively by

µ _{α -1} = f _{a -1} ^⊕ (f _{α -2} + f _{α -3} + _... + f _β ) (9)

The second peculiarity, namely the processing of negative multiplicands (MSB m _MSB = 1), is closely related to the problem just described. The problem can be solved simply by inverting the multiplier in the case of a negative multiplicand (swapping the ϕ _i and η _i ) and forming the 2's complement from the multiplicand. However, this operation includes the redundancy that the partial products are not changed by the double inversion, so that this operation does not have to be carried out. The only operation to process negative multiplicands is to form the leading ones with the ϕ _i instead of the η _i . The switching can be done by a simple logic of the form

take place ( Fig. 4). The operation of the 1 addition at the location of the LSB can also be carried out with the η _i (see FIG. 1 (5)). A distinction between sign multiplication and amount multiplication can be achieved by using the control variable s to switch through the MSB of the multiplicand m to the m _MSB (sign multiplication), or to keep m _MSB = 0 constant (amount multiplication).

Further refinements of the invention

The elements presented, shown in FIGS. 1, 3, 4 and 5, form a unit and, in conjunction, cause parallel multiplications to be carried out in the CSD code. However, the principle is not subject to any further restrictions, so that many common improvement techniques can be applied to it. The following should be mentioned in detail:

• - The multiplier must be executed in parallel or as a pipeline structure ren,
• - With a small number of additional adders, additions can be made or include subtractions across the entire range of result words with little increase in total delay time,
• - If you add a control signal that switches the m _MSB switching in equation (10) on or off, you can choose between sign multiplication and mixed sign amount multiplication. If X _{α +1} = 0 is also set according to equation (5), pure amount multiplications are possible,
• - Is to round the result to the x position of the result word there is another addition input for this point to be provided, to which the result bit of position x-1 is to be led. These Operation can be carried out switchable,
• - Leave CLA (carry look ahead) and CSA (carry save adder) structures due to the regularity and the use of conventional Standard full adder without problems to accelerate the multiplication deploy,
• - With a fixed structure, different lengths of the operands should be used can only be authorized, the tap of the MSB is Selectable multiplicands,
• - Another characteristic of the CSD code multiplier is the low average power consumption in CMOS technology, which is reduced by the Number of partial products is reached,
• - a concrete calculation of the product of delay time and oil sistor number, normalized to the squared word length of the operands, resulted for a CSD code multiplier with integrated additions / subtracts Proportionality with 124 n and for a standard multi multiplier without additions / subtractions a proportionality of 240 n, where n is the length of the two operands,
• - The flexibility allows the use in microprocessors, signal processors, Correlators, digital filters and. to.

Examples

The mode of an amount multiplication is selected in FIG. 2a). The multiplier on the left in the CSD code corresponds to decimal 1 - 4 + 16 = 13. The multiplicand m is interpreted as an unsigned dual number and has the value 1 + 2 + 8 = 11. The multiplication result must therefore be decimal 13 · 11 = 143 In fact, when interpreting the result as an unsigned dual number one gets 1 + 2 + 4 + 8 + 128 = 143. The bracketed (1) on the left in the result word has no meaning. The leading ones must be generated in this mode (amount multiplication with m _MSB = 0 ( Fig. 1 (6)), ie they are always formed by η _i .

In Fig. 2b) the mode of a signed multiplication is selected, in which both the multiplicand m and the result are interpreted in 2's complement. The multiplicand in 2's complement has the decimal value -5. Multiplied by the multiplier 13, the result must be decimal 13 · -5 = -65. The interpretation of the result word in 2's complement provides exactly this value. Because the MSB of the multiplicand m is 1 (negative decimal number), the leading ones were generated with the ϕ _i instead of the η _i . They therefore appear in the first and last lines, which, however, no longer have to be taken into account.

In both modes, the 1 addition was carried out with the η _i (see FIG. 1 (5)). The circled partial products indicate a possibility of combining two terms, which cannot both be one at the same time. The arrows emanating from the multiplier in the CSD code indicate that in both cases the 1 addition is carried out with the η _i and the leading ones in FIG. 2a) are generated with the η _i and in FIG. 2b) are generated with the ϕ _i .

Claims (15)

1. Digital CSD code multiplier of two binary numbers, shown in 2's complement, which results in the number of standard full adders reduced is that the multiplier is shown in the CSD code and due to the zero value every second multiplier bit two partial products of neighboring value combined into one get caught. 2. CSD code multiplier according to claim 1, characterized in that the partial products ( Fig. 1 (2)) are generated by fast gates with negated outputs. 3. CSD code multiplier according to claim 1, characterized in that the required CSD code generated ( Fig. 1 (3)) can be increased by increasing the delay time per value by that of a fast NOR gate. 4. CSD code multiplier according to claim 1, characterized in that in the 2's complement formation of the multiplicand so-called "leading ones" arise ( Fig. 1 (4)), which can be added up due to their regularity with a low combinational logic ( Fig. 4). 5. CSD code multiplier according to one of the preceding claims, characterized in that in the case of negative multiplicands, ie that the MSB is 1, by switching from the negative bits to the positive bits of the CSD codes for treating the leading ones can be processed without any further circuit measure ( Fig. 4). 6. CSD code multiplier according to one of the preceding claims, since characterized in that neither of the two to be multiplied Factors before processing still from the result word after the Processing complements must be formed. 7. CSD code multiplier according to one of the preceding claims, since characterized in that known acceleration techniques apply Can be detected, such as purely parallel and pipeline technology and CLA (carry look ahead) and CSA (carry save adder) structures. 8. CSD code multiplier according to one of the preceding claims, since characterized in that the average power loss of the circuit compared to conventional multipliers due to the reduced number  Full adders is lower. 9. CSD code multiplier according to one of the preceding claims, ge characterized in that with a small increase in the number of transistors and the total delay time integrates additions and subtractions can be. 10. CSD code multiplier according to one of the preceding claims, ge characterized by the fact that between amount, mixed amount / before sign multiplication and sign multiplication can be selected. 11. CSD code multiplier according to one of the preceding claims, ge indicates that rounding by adding another Addition inputs for this value with appropriate interconnection can be carried out. 12. CSD code multiplier according to one of the preceding claims, there characterized in that, in the case of an existing structure, the word length of the Factors can be varied to a maximum. 13. CSD code multiplier according to one of the preceding claims, since characterized in that the multiplier length is not equal to the multi must be plicand length. 14. CSD code multiplier according to one of the preceding claims, since characterized in that he z. B. in digital filters, signal processors, Microprocessors, correlators can be used. 15. CSD code multiplier according to one of the preceding claims, there characterized by the fact that it is both a fixed-point and a Additional logic is to be used as a floating point multiplier.