DE4208924B4 - Method for communication between processors and parallel processing computers therefor - Google Patents

Abstract

An intra-processor communication method in a multi-cluster parallel processor system (100), each having at least one processor (1; 501, 502) and a main memory (2; 505) to be used by said at least one processor, and a network (4; 509) for connecting the plurality of clusters, wherein at least one process is performed with at least one associated virtual space within each cluster under control of an operating system associated with each cluster, and the intra-processor communication method for transferring transmission data from a transfer originating process associated with a first cluster to a second cluster associated transmission reception process is characterized by the following steps:
Ensuring a real communication area (13) residing in the main memory within each cluster for each process associated with the cluster, the real communication area being mapped into a virtual communication area (11) within the virtual space associated with each cluster;
Selecting a real communication area associated with the transmission reception process in the first cluster, and a virtual write address where the transmission data is within a range of ...

Description

The The invention relates to a method for data transmission between processors in a parallel processor with the goal of high-speed computation to achieve, in particular in a parallel processor of the MIMD type with distributed stores.

Rough speaking, there are three types of techniques for achieving high speed processing using multiple processors.

Of the first type of techniques is one in which a parallel processor is structured by at least Dozens of processors used to be an extreme improvement in the effectiveness of the processes compared to a processor with only one processor. condition In this type of technique, a large number of processors are used becomes. Therefore, it is important for everyone Processor reduced size and possibly limited function compared to the function of a general-purpose computer having. For example, in a compact processor of the first type Techniques of the address translation mechanism for Realizing a virtual memory is omitted. It passed Techniques of parallel processors with a large number of processors, according to those a plurality of processes are executed by a processor can, as z. As described in EP-A-0 255 857. However, that is none of the processors according to these Techniques with a function to realize a virtual memory fitted.

on the other hand As a second type of techniques, a parallel processing computer is a device with several processing elements known, each of which has a has local memory, according to which Technique data into a local memory from another processing element can be enrolled. If some processing element uses data using a local memory of another processing element Markings on a part or the totality of the words in the attached to local storage, and these flags indicate whether the content of the words is valid or not. This type of device is z. As described in EP-A-0 326 164.

Of the third type of techniques is a so-called processing technique for distributed Data for connecting a few general-purpose computers to one LAN system or the like. For example, the processing technique is equivalent with distributed data in the workstation with a UNIX operating system this third type of technique as described by UNIX System Laboratories Ltd. developed and currently licensed. Hey this guy of technology There is a condition that general purpose computers be used. Each processor has a structure like a general-purpose computer on, and each of these general purpose computers is an adapter for communication added. Each processor is loaded with a general-purpose operating system, and the communication adapter is handled as an aid including disk input / output units, managed by the operating system. Therefore, communication becomes between the processors over executed a system call. The is called, that it then when a process to To run a program created by a user begins to send data to one other process too is required to enter the operating system program and work it off.

30 Figure 3 illustrates the operation in data transmission according to the third type of known technique. Such is z. From SL Leffler et al. in "The Design and Implementation of the 4.3 BSD UNIX Operating System", Addison-Wesley Publishing Company, pp. 384-386. First, the data transfer process executes a system call for data transfer. When the operating system has received the system call, it copies the data to be transferred, along with parameters relevant to the process of the transmission receiving location, to the buffer in the operating system. Subsequently, the operating processor checks the parameters, sets them, as well as the data for the transmission circuit from the buffer area in the operating system and gives the instruction for data transmission to the transmission circuit.

When the transmitting circuit has sent the data and these have arrived in the receiving circuit of the data receiving processor, the receiving circuit stores the parameters and the data in the buffer within the receiving circuit and informs the operating system in the receiving processor. After the operating system in the receiving processor has received this message, it makes a copy of the parameters and data from the buffer within the receiving circuit into the buffer within the operating system. The operating system then examines the parameters and the data. If the investigation reveals that there is no problem, the operating system transmits an acknowledgment signal (ACK) to the originating processor. When it has received the signal ACK, it releases the buffer area within the operating system, which was ensured when a request for the transmission of the parameters and the data took place, resulting in the transmission of the ACK signal from the operating system te.

If the process, the data begins to receive, a system call to receive the Data executed has checked the operating system in the receiving processor, if all the required data already arrived. If so, the operating system creates it a copy of the data from the area storing this data within of the operating system in the area within the process, the executed the system call Has. If the data has not arrived yet, the operating system waits on the receipt of the data and leads the above procedure for receiving the data after receiving the data.

According to the above There is a limitation to the first type of known techniques mentioned in terms of the function of each processor, and the user is on it instructed to create a program that has the hardware properties sufficiently considered, like the storage capacity each processor within the limited function of each processor.

On the other hand In the above-mentioned second type, it consists of known techniques no overhead with respect to the above-mentioned copying of data. If, however, several processes are to be processed in a cluster and if a transfer process in one other clusters presented data to a particular receiving process within of several processes sending a local memory, there is a risk that the transmission process the data of the concurrent process can thus be changed by the reception process in the same cluster, that these Data can be changed so that she invalid become.

At the The third type of known technique described above operates one operating system in each cluster in such a way that several Processes can run simultaneously in each cluster. Therefore It is even when the number of user processes passing through the program to be executed by the parallel processing computer generated does not match the number of clusters, the execution associated with this program, it is possible to program this program perform, the existence virtual space corresponding to each of the user processes. Accordingly, data transmission means between the user processes actually transferring data into the virtual space according to the transfer origin process to the virtual space corresponding to the transmission reception process. Even if there is an error in the user program, the protection mechanism can or the like of the operating system to make a control, the to an unreasonable destruction leads from data of the process, the for the program are irrelevant.

Around Data at high speed from a specific cluster to send an external unit of the cluster, such as A network to make connections between the clusters, usually becomes a DMA transfer used. DMA transfer is realized by a so-called DMA controller, which is structured in such a way that he permanently a hardware Memory address generated and constantly reads data from the memory or enroll in these. If, however, data from the virtual Space of a transfer origin process are to be transmitted to the network using the DMA controller, There is no guarantee that the virtual memory to be transferred Data exists in the current memory of the cluster. In order to guarantee, that the to be transferred Data exists in real memory, it may be necessary to make a page write and then the data to the DMA controller transferred to. Page writing is a feature that only one operating system is allowed, causing the operating system inevitably in the data transmission according to the known Technique is to clamp.

Such a data transmission technique is in US 4,956,771 discloses that an intelligent controller transfers data between various "tasks" to a host computer. It uses an I / O segment attached to the host computer and the controller.

WHERE 90/05338 describes a system in which several operating systems run, and data transmission between virtual memories in main memories and extended ones Saving takes place.

Even if continuous data transmission was performed by the DMA controller after the above-mentioned preparation, there is no guarantee that an area for storing the transmitted data in the virtual space for the transmission reception process has been allocated to the real memory of the transmission reception cluster. Therefore, according to the prior art, the operating system in the transmission reception cluster has in its interior a buffer (a reception buffer) present in the real memory for storing the transmitted data. The operating system stores the received data in the reception buffer, then performs page writing if necessary, and then transmits the data to the data storage area in the virtual space corresponding to the transmission reception process. In this case, the above mentioned page entry using the operating system to be executed.

Even if the above-mentioned receiving buffer z. B. present in the transmission receiving cluster is, exists for the transmission receive cluster no way to the effect that in the know ahead when the transfer origin cluster Send data to the transmission receive cluster and how big the Scope of this data will be. Accordingly, it is not possible in advance ensure the required range in the buffer. If the volume of transmitted data is larger as previously estimated and exceeds the seized size of the receiving buffer, receives hence the transmit receive cluster the data sent from the data source cluster, but the Data is received from the transfer origin cluster at the transmission receiving cluster retransmitted after a new receive buffer of required size in the transmit receive cluster was ensured.

Around the above retransmission according to the known To enable technology indicates the operating system of the transfer origin cluster in its interior a transmission buffer, to transfer it in him Storing data until it is ensured that the data to be transmitted is received securely by the transmission receiving cluster were.

If the transmission buffer is stored in real memory, the data to be sent, as they are in the transmission buffer are stored continuously through the DMA controller to the Network transfer become. This leads to the prior art transmission-receiving cluster when transmitting of data in the virtual space according to the transmission origin process to the transmission reception process, the page inscription off, if necessary, as described above, transmits the data to be sent, as they are stored in virtual space, to the transmission buffer in real memory and then transmits those in the transmission buffer stored data through the DMA controller to the network.

As described above, then run according to the known technique, when data from the virtual space according to the transfer origin process to the virtual space according to the transmission reception process to send are these data through the transmission buffer in the operating system of the transfer origin cluster the operating system, to the receive buffer in the operating system of the transmit receive cluster, via the Operating system. Creating a copy of the data in the buffer has an overhead that is almost proportional to the length of the to be transferred Data is. This overhead lowers the efficiency of a parallel processing computer extreme wise.

Of the Invention is based on the object of lowering the overhead, as it arises by using the operating system, if several Processes in the same cluster work and a certain cluster data to a process that transmits is processed in another cluster.

In a parallel processor according to the invention with multiple clusters, each of which has at least one independently operable one Processor and a memory, in which the processor arrangement shares with the at least one processor, and with a network for connecting the plurality of clusters, wherein at least one virtual space each of the multiple clusters is assigned and at least one process in the virtual Space is executed under control of the operating system, the above said object solved by such an arrangement, according to which a process a has virtual communication area in memory within of the cluster is resident and is located in virtual space and the data obtained from a process (a transfer origin process), the just in a certain cluster (a transfer origin cluster) accomplished is to transfer to another process (a transmission receiving process) that is another cluster (a broadcast receive cluster) is assigned, read from a real communication area assigned to the transfer origin process is which area within the memory of the transmission origin cluster resident, with the read data from the originating transmission cluster transferred to the transmission receiving cluster and the data are written into a real communication area assigned to the transmission reception process that is within the memory of the transmission reception process resident.

The Invention will now be illustrated by figures embodiments described in more detail.

1 Fig. 10 is a constructional diagram of a parallel processing computer according to a first embodiment of the invention;

2 Fig. 10 is a configuration diagram of a request selection circuit;

3 Fig. 10 is a configuration diagram of a communication range table address generation circuit;

4 Fig. 10 is a structural diagram of a decision circuit;

5 Fig. 10 is a structural diagram of an address generation circuit;

6 is a structural diagram of a communication area;

7 is a structural diagram of a requirement area;

8th is a structure diagram of a page table;

9 Fig. 10 is a structural diagram of a communication area table;

10 is a structural diagram of a request table;

11 Fig. 15 is a diagram showing the data transfer flow between the processes in the parallel processing computer according to the first embodiment of the invention;

12 Fig. 10 is a configuration diagram of a parallel processing computer according to a second embodiment of the invention;

13 Fig. 15 is a diagram showing the data transfer flow between processes in the parallel processing computer according to the second embodiment of the invention;

14 Fig. 10 is a configuration diagram of a parallel processing computer according to a third embodiment of the invention;

15 Fig. 16 is a diagram showing the data transfer flow between the processes of the parallel processing computer according to the third embodiment of the invention;

16 Fig. 15 is a diagram showing the data transfer process between the processes of a parallel processing computer according to a fourth embodiment of the invention;

17 Fig. 10 is a configuration diagram of a parallel processor according to a fifth embodiment of the invention;

18 is a diagram that illustrates the entry in a path table as used in the parallel processor of 17 is used to translate a virtual Kommuni cation path in a physical communication path;

19 is a diagram that illustrates contextual information for a process as used by the parallel processor of 17 is to execute;

20 is a diagram showing the format of a BASE set command as used in the parallel processor of 17 is to be used;

21 is a diagram showing the format of a LEN setting command as used in the parallel processor of FIG 17 is to be used;

22 is a diagram showing the format of a remote store command as used in the parallel processor of FIG 17 is to be used;

23 FIG. 12 is a diagram showing the function of a unit when a data transfer command as in the parallel processor of FIG 17 to use was executed;

24 Fig. 12 is a configuration diagram of a parallel processor according to a sixth embodiment of the invention;

25 FIG. 13 is a diagram showing the format of a remote storage preparation command as used in the parallel processor of FIG 24 is to be used;

26 FIG. 13 is a diagram showing the format of a remote storage execution command as used in the parallel processor of FIG 24 is to be used;

27 is a diagram showing the flow of a data transfer command as it is in the parallel processor of 24 is to be used;

28 Fig. 12 is a configuration diagram of a parallel processor according to a seventh embodiment of the invention;

29 Fig. 10 is a configuration diagram of a parallel processor according to an eighth embodiment of the invention; and

30 Fig. 10 is a diagram for explaining the communication operation between processors according to the prior art.

Embodiment 1

A first embodiment of the invention will now be described with reference to FIG 1 described. 1 shows an inventive Parallel processing computer. Hei this embodiment, several clusters 100 through a network 4 connected with each other. In 1 is the construction of one of the clusters 100 shown, while the structures for other clusters are not shown. In 1 1 denotes a CPU which may have the same structure as a known microprocessor. In 1 For the sake of simplicity, only a single CPU is shown, but each cluster forms 100 a tightly coupled microprocessor of at least two CPUs. However, the invention also works when each cluster 100 has only a single processor. 2 refers to a memory that is the main memory of the cluster 100 is used. Access to the main memory 2 is done via the CPU 1 or an external device (not shown) via a bus 3 What happens with the help of the known technique. 4 denotes a network for connecting clusters 100 , If a cluster has specified the address of a broadcast receive cluster, the network transfers 4 the data to the transmit receive cluster (not shown) with this address.

110 denotes a transmit data read circuit for reading data from the memory 2 are to be transferred from. 28 denotes a transmission circuit for transmitting the read transmission data in packet form via the network 4 , 42 denotes a circuit for receiving a packet from the network 4 , 120 denotes a reception data write circuit for writing the data received with the received packet into the memory 2 , 7 denotes a memory access circuit for executing access to the memory 2 for reading data to be sent or for writing in received data.

In the CPU 1 For example, a user process is performed in the same manner as that performed in the UNIX operating system developed and licensed by UNIX System Laboratories Ltd., USA. There is a virtual space that corresponds to a user process. In 1 is just a virtual space 10 in the CPU 1 to simplify the description. A virtual communication area 11 for sending data and for receiving data and a virtual request area 12 for information to add to data to be sent are in virtual space 10 available.

The memory 2 has a real communication area 13 in which the virtual communication area 11 as it corresponds to each user process is mapped. He still has a real requirement area 14 in which the virtual request area existing for each user process 12 is mapped. Furthermore, a page table 15 for address translation for each user process and a communications area table 16 present to several communication areas 13 in this cluster.

According to the present embodiment, such a structure that a user process to be executed in a certain cluster is data to be transmitted in the real communication area 13 within that cluster, without the operating system operating that controls that cluster, enrolling the transmit data read control 110 the data to be sent reads, without requiring the operating system to operate, that the receive data write circuit 120 the data received from another cluster into the real communication area 13 writes in without the operating system having to do this, and that the user process reads the data without the operating system acting on it.

6 shows a structure for the virtual communication area 11 , It is arranged with data to be sent by one user process (eg, an array A, variable) or data received from another, and a data reception spot. This area is one that is primarily used to exchange data with a process running in another cluster.

7 shows a structure for the virtual request area 12 , This is an area where a library function used by the user process makes an access. The requirement area 12 has at least one requirement structure unit 12-1 and a place table 12-2 on. The requirement structure unit 12-1 stores a data transmission request that is assigned to a process in another cluster by a process that is the virtual space 10 corresponds to the requirement area 12 and parameters added to this data send request. The place table 12-2 stores information related to the process controlled by another cluster.

9 shows a structure for the communication area table 16 , This stores several entries, each of which corresponds to a communication area. Each entry has a base address BASE for the assigned communication area and a size LN for this area.

10 shows a structure for the requirement table 17 , This has several entries for storing real addresses. If the virtual requirement structure unit 12-1 ( 7 ) in the virtual request area 12 in any virtual space.

8th shows a structure for the page table 15 , Each entry of the page table 15 has a real page address field, a fixed page flag field, and other control information. If a flag F indicating that a page is pinned is stored in the fixed page flag field, the operating system controls so that the real page corresponding to that entry is not paged out. A column "Other Control Information" stores information similar to a dynamic address translation according to the prior art.

The operation of a parallel processing computer according to this embodiment will now be described. First, the initialization of the parallel processing computer will be explained. Each cluster has equipment necessary to initialize the operation, such as a magnetic disk unit which is not shown to simplify the drawing. When the power is on for the system, each cluster loads an initializer in the same way as a tightly coupled microprocessor does in the prior art, thereby starting the operating system independently in each cluster. After the operating system in each cluster has been initialized, the operating system can begin to exchange data with the operating system of each desired cluster, using a known technique such as the TCP / IP protocol. The exchange takes place via the network 4 or a known network, not shown.

In the present embodiment, after initializing the operating system, the following operations are additionally performed. The operating system in each cluster creates the communications area table 16 In the storage room 2 and sits over the bus 3 the head address for this table in a communications area table origin register 6 , Then the operating system generates the request table 17 in main memory 2 and sets the head address of this request table 17 in a request table origin register 5 , The content of the table 17 is not written yet.

The Initialization of a user process is described below.

First, the user instructs the operating system of each cluster to perform a process initialization. The operating system that received the command to initialize generates in memory 2 the page table 15 to a virtual space 10 which corresponds to the process for which the initialization was instructed. This is done in the same way as in the prior art. Subsequently, the virtual communication area 11 initialized as follows. A contiguous real address space with a programmer or compiler specified size is stored in memory 2 ensured, and this area is considered a real communication area 13 set. Then the addresses of this real communication area become 13 described in succession, wherein from the head address in the address field for the real page in the entry of the page table 15 is started, what the virtual address of the communication area 11 in virtual space 10 (please refer 8th ) corresponds. In addition, the page fix flag F in the associated page fix flag is set within the table 15 set, hence the communication area 13 not paged out (paged-out). In this case, it is assumed that the head address of the virtual communication area 11 is set to a predetermined value and that this value is common to the user programs in all clusters. It is also assumed that the size of the virtual communication area 11 with the size of the real communication area 13 matches.

The operating system assigns the real communication area 13 a unique communication area identifier within the cluster 78 and sets the base address (head address) and the size of the real communication area 13 in the entry (see 9 ) of the communication area table 16 with the communication area identifier as the entry number. The virtual communication area 11 becomes the real communication area 13 fixed by the page fix flag of the page table. Therefore, the virtual communication area 11 be unambiguously identified within the cluster by the unique communication identification within the cluster that is in the real communication area 13 was set.

Then the operating system sets the real request area 14 in the contiguous area of the store 2 sure and then write the address of the secured real requirement area 14 into the real page address field of the page table entry 15 , the virtual address of the request scope 12 in virtual space 10 and sets the page fix flag F in the page fix flag (see 8th ), thus the contents of the secured real requirement area 14 is not stored out page by page. Then, the operating system generates the request structure unit 12-1 and the place table 12-2 in the virtual request area 12 , as in 7 shown. As described above, the corresponding real request area has become 14 in the virtual request area 12 secured, and the real requirement area 14 was when in the store 2 Resident set, so that this area is not stored page by page. Accordingly, the actual memory without exception corresponds to the request structural unit 12-1 and the place table 12-2 , However, there was still no information stored there.

The operating system continues to set the address of the page table 15 in a predetermined area (not shown) of the initialized process to allow the process to access the page table 15 can relate.

Then the operating system writes the real header address for the real request area 14 , the request structure unit generated as indicated above 12-1 corresponds, in the still unused entry area of the real requirement table 17 ,

By initializing the operating system as stated above, the user process can access the real communication area 13 be accessed by the virtual address of the virtual communication area 11 is used. Access can also be from the operating system or an external device to the real communication area 13 be done by using the real communication area table 16 the real address is used. On the real area, that of the virtual requirement structure unit 12-1 may be from the virtual request area 12-1 be accessed by the virtual address of the virtual request area 12-1 is used. The real area can also be accessed directly from the operating system or external device, where the real address is via the requirement table 17 is used.

Then, the operating system adds the name of the process previously assigned to the initialization process by the programmer or the compiler, the communication area identifier for the real communication area to be used in this process 13 and the address within the network of the cluster together. The operating system transfers this record to all other clusters. When the respective operating system in each of the other clusters has received the process name, the communication area identification and the address within the network of the cluster, it writes the received process name, the received communication area identification and the received address within the network of the cluster into a free entry area of the location table ( the area in real memory, that of the place table 12-2 in 7 corresponds) in the real requirement area 14 provided for the user process in the cluster, the reference to the process names being made beforehand by the programmer or the compiler. The cluster for initializing the above-mentioned user process performs the same processing as mentioned above when the user process using the process within that cluster as the user process of the transmission reception has been initialized in the other cluster. If with the above arrangement in virtual space 10 The process to be executed makes an association of the name of the transmission reception user process, the address of the cluster in which this process exists, and the communication area identification of the communication area 11 which is to be used in the broadcast receiving user process can be obtained without using the operating system, which will be described later.

User processes which were operated in the above manner, work parallel by mutually transferring data to each other.

With reference to 11 Now, the data transfer between processes will be explained with respect to the present embodiment. The procedure to be taken to perform data transfer between user processes is explained by dividing the operations into one for a user process of the transmission origin and one of the transmission reception. In the description of the operation of the user process of the transmission origin, the operations are divided into those of the operation of the user process of the transmission origin, the cluster of the transmission origin, and the cluster of the transmission reception (not shown). Unless otherwise indicated, the operations will be described by the CPU as explained below 1 executed.

step 50 : Invoke the library function "Send".

When the transmission originating process starts to send data from the virtual communication area 11 , z. As an array A, to send the data receiving process, the previously created (not shown) library function "Send" in the following format aufgerugen:
Send ("Transfer Receive Process Name", X, Y, Z, L).

A user determines the name of the transmission receiving process as a first argument. The second argument X is the virtual address of the head in virtual space 10 of the transmission origin process for the transmission data A. The third argument Y is the virtual address of the head of the area in which the data is to be stored in the virtual space (not shown) of the transmission reception process. The fourth argument Z is the virtual address of the data reception flag to be stored in the transmission reception cluster when data is received. The fifth Argu L denotes the volume of the data to be sent. In the present embodiment, the data transfer process knows in advance the location and the size of the virtual communication area of the transmission reception process. Accordingly, the virtual addresses can be assigned to the third and fourth arguments, as they belong to the program according to this communication area. The data volume indicated by the fifth argument is programmed to be smaller than the size of the virtual communication area.

step 51 : Converting the arguments

The library function "Send", which was called, works in virtual space 10 as follows as part of the user process. It reads the cluster address and the communication area identification of the transmission reception process from the location table 12-2 in the virtual request area 12 (the corresponding real request area 14 is in the store 2 resident) based on the name of the transmission reception process. Then it converts the virtual address of the head of the transmission data into the real address of the transmission data in the real communication area 13 of the memory 2 , what by using the side tab le 15 he follows. The library function "Send" pulls the head address of the virtual communication area 11 of the transmission origin cluster from the virtual address of the data reception area and the data reception flag, respectively, to the respective offset within the real communication area 13 to receive the transmission receipt. The correctness of these processes is guaranteed by the fact that in all clusters the head address of the virtual communication area 11 was sent within the user process and that the virtual communication area 11 subsequently from the head of the area in the real communication area 13 of the contiguous area in memory 2 was assigned.

The as above obtained offset volume becomes negative when a Bug is in the user process. In this case, a program interrupt occurs in the operating system.

step 52 : Setting processes in the requirement area

The library function "Send" then writes the address CL of the transmission reception cluster and the communication area identification ID as previously read, the offset SO of the data reception area, the offset FO of the data reception flag, the data length of the transmission data and the real address as previously obtained. each in the requirement structure unit 12-1 in the virtual request area 12 ( 7 ). It also sets the request flag in the request flag field in the request structure unit 12-1 , Because the virtual request area 12 in the real requirement area 14 resident, these parameters are in the real request area 14 enrolled.

step 53 : Execute the next command

If the processes described above completed, the library function "Send" indicates the control the user process back. This leads the subsequent Command of the transfer request parallel with the following procedures by.

step 54 : Setting Parameters in Registers

A request selection circuit 21 always repeats the following procedures. It reads the value of the request table origin register 5 that is, the value as determined by the operating system at its initialization in the request table entry address generation circuit 21-1 within the circuit 21 ( 2 ) generates the real address of the header entry of the request table 17 In the storage room 2 and reads the physical address of the request structure unit (not shown), which is the content of that entry, from the memory 2 , and gives an input via the memory access circuit 7 and the bus 3 to the request flag address generation circuit 21-2 , The latter receives the real address of the request flag field from the read real address of the request structure unit and outputs the contents of this real address from the memory 2 via the memory access circuit 7 and the bus 3 in a request flag decision circuit 21-3 , The latter decides whether the request flag has been written in the request flag field and sends a signal to the request table entry address generation circuit 21-1 if the request flag is not yet written in the request flag field. The circuit 21-1 generates an address for the next entry of the request table 17 ; thereafter, the request flag address generation circuit operates 21-2 and the request flag decision circuit 21-3 in the same manner as described above. When the request flag is written in the request flag field, the request flag decision circuit sends 21-3 in addition to a transmission circuit state decision circuit 21-4 a signal to indicate the state of the transmission circuit 28 of the associated cluster. When the transmission circuit 28 just busy, check the circuit 21-4 the state of the transmission circuit 28 again. If the latter is not busy, a request structure input input address generation circuit will become 21-5 initialized. She reads the Request structure unit (not shown) in the real address space, which includes the virtual request structure 12-1 corresponds to what is based on the address of the request structure unit 12-1 previously performed by the request table entry address generation circuit 21-1 has been read, and places a copy of the cluster address CL in a register 22 a copy of the communication area identification ID in a register 23 , a copy of the offset SO of the data reception area in a register 24 , a copy of the offset FO of the data reception flag in a register 25 and a copy of the data length LEN in a register 26 , After that creates the circuit 21-5 a copy of the data to be sent from the real communication area 13 in a buffer 27 which is done using the real address of the transmission data within the real request structure unit (not shown) that has been read. After that, the circuit sends 21-5 a request flag address and a reset command to reset the request flag field so that the user process originating the transfer request can recognize that the content of the area in which the data to be transferred is stored can be changed since the reading of the data to be transmitted Data was completed.

When the above operations are completed, this becomes the request table entry address generation circuit 21-1 over a line 1000 communicated.

Similar procedures be for the rest of the requirement structure units executed.

step 55: Transferring data

The transmission circuit 28 sends the contents of the registers 22 to 26 along with the contents of the buffer 27 as a packet to the network 4 ,

As described above, in the transmission origin cluster, the library function "Send" transmits the transmission data read circuit 110 and the transmission circuit 28 Data to the network 4 without requiring the operating system. This is done upon request from the origin of transfer process. The operation in the transmission receiving cluster will be described below.

step 56 : Checking the Data Acceptance in the Communication Area

If a package for the network 4 arrived at the transmission reception cluster, receives a receiving circuit 42 the packet and creates a copy of the communication area identifier (ID) in a register 37 , a copy of the offset (SO) of the data reception area in a register 38 , a copy of the offset (FO) of the data reception flag in a register 39 , a copy of the data length (LEN) in a register 40 and a copy of the data in a buffer 41 Then, use a communication area table address generation circuit 31 ( 3 ) based on the communication area ID in the register 37 an offset calculation circuit 31-1 to the offset of the entry corresponding to this identification ID within the communication area table 16 ( 9 ). The communication area table address generating circuit 31 then uses an adder circuit 31-2 for adding the offset to the head address of the communication area table 16 In the storage room 2 as by the communication area table origin register 6 to calculate the input address (real address) of this communication area identification in the communication area table 16 and it creates a copy of the communication area base address BASE of this entry in the register 32 and a copy of the size LN of the communication area in the register 33 what through the memory access circuit 7 and the bus 3 he follows.

When the transmission origin process is normally programmed, the address for storing the received data and the address for storing the data reception flag become the real communication area 13 stored. In the present embodiment, it is decided whether these addresses are in the real communication area 13 can be accommodated to decide whether there is a programming error in the transmission origin process. In other words, this means that a decision circuit 35 ( 4 ) by means of comparison circuits 35-1 and 35-2 makes a decision, taking the offset SO of the data reception area, that is, the contents of the register 38 , the offset FO of the data reception flag, that is, the content of the register 39 , the data length LEN, that is, the contents of the register 40 , and the size LN of the communication area, that is the content of the register 33 , uses. The comparison circuit makes comparisons based on the respective inequalities as described in 4 are shown. When the inequality conditions are filled, a write inhibit signal is generated by these circuits. An OR circuit 35-4 takes an OR operation of the output signals, as determined by the comparator circuits 35-1 and 35-2 be generated. If a signal to this OR circuit 35-4 is output, this means that data in the communication area 11 can not be recorded.

step 59 : Occurrence of an interruption

If data as a result of the decision in the real communication area 13 can not be received causes the decision circuit 35 that a hardware interrupt signal about the pen 3 running.

step 60 : Preventing communication

The hardware interrupt signal is detected by the at least one CPU in the transmit receive cluster. The operating system is controlled by the interrupt processing routine of the CPU 1 Initializing the signal that first detected the signal and subsequent transfer is prevented by communication of that operating system with the operating system of the other cluster.

step 57 : Address translation

If the transmission data is in the real communication area 13 can be picked up using an address generation circuit 34 ( 5 ) an adder circuit 34-1 to generate the real address for the location under which the received data is to be stored. This is done with the help of the offset SO for the receive data area, ie the contents of the register 38 , and the base address BASE of the communication area 13 , that is the contents of the register 32 , In addition, the address generation circuit uses 34 an adder circuit 34-2 to generate the real address of the position under which the data reception flag is to be stored. This is done with the aid of the offset FO for the data reception flag, ie the contents of the register 39 , and the base address BASE of the data reception flag, that is, the content of the register 32 ,

step 58 : Saving data

The memory access circuit 7 transmits the received data in the buffer 41 to the real communication area 13 what they are the real address for the received data, as in step 57 generated, and the data length LEN, so the contents of the register 40 , used. The memory access circuit also sets the data reception flag to the position of the real address of the data reception flag as in step 57 generated.

As described above the received data is written in the real communication area be without this the operating system operates must become.

According to the above-described procedures, the data transfer process sets the positions for the reception data and the data reception flag by the virtual address of the virtual communication area 11 firmly. Because the virtual communication area 11 in the real communication area 13 resident, however, enrolling can never be unsuccessful due to a page fault. In other words, the packet from the originating transmission cluster is not sent back to the transmission receiving cluster. Accordingly, in the present embodiment, it is not necessary to provide an area for storing a copy of the package in order to be prepared for returning the package as required in the prior art.

following becomes the flow of the transmission reception process described.

When the transmission receiving process wants to use data, it checks use of the library function to confirm the arrival of data, and then reads the data reception flag existing in the virtual communication area using the virtual address. Then, based on the value of the data reception flag, the process decides whether the data reception is completed or not. The transmission reception process resets the data reception flag in advance by assigning the programmer or the compiler before transmitting data. When the data reception is completed, the flag is set in the manner described above. Therefore, the transmission reception process can decide based on the flag whether the data reception is completed. After the completion of the data transmission is detected, the transmission reception process accesses the received data by means of the virtual address. If the flag remains reset, there is such a programming that the transmit receive process does not have access to the data within the virtual communication area 11 performs.

The completion of the process will be described below. When finished, the operating system deletes the page table 15 for the process and releases resources, such as the memory area associated with the process; this is done in a similar manner as in the known UNIX operation. According to the present embodiment, furthermore, the entry corresponding to the real communication area 13 corresponds to how it is assigned to the process to be terminated in the communication area table 16 deleted. In addition, the operating system notifies the operating system of the other cluster of the name of the process to be completed over the network. The operating system of the cluster that has been notified of the completion of the process deletes the term corresponding to the process name of the completed process from the location table 12-2 ,

With the above statements is the explanation to the first embodiment completed the invention.

Modification of the embodiment 1 (embodiment 2)

Heim previous embodiment, it was assumed that the virtual communication area 11 is stored under each same address in each virtual space. However, it may also be assumed that a fourth field in each entry of the location table 12-2 ( 7 ), wherein the virtual head address of the virtual communication area 11 is stored for the respective process in this fourth field, and that the content of the fourth field is used for that part in which the offset of the data reception area is calculated by the head address of the virtual communication area 11 of the transmission originating process is calculated as in the above step 51 , Hei this arrangement, it is not necessary, this for the virtual head address of the virtual communication area 11 to put in every virtual space.

In the step described above 56 become the head address and the length of the real communication area 13 obtained by using the communication area identifier ID present in the received packet and in the register 37 is stored. However, it is also possible to make such an arrangement that instead of the communication area identification ID, an identifier which can uniquely identify the process of receiving data, and that a circuit for receiving the head address and the length of the real communication area 13 from this identification is provided within the receive data write circuit.

A second embodiment of the invention will be described with reference to FIG 12 described. The second embodiment is a modification of the first embodiment. Therefore, a description is made mainly for different points. The present embodiment differs from the first in that only the transmission origination process requires the operating system to send data to the network, while the data receiving process receives data without claiming the operating system. Accordingly, there is the advantage that the number of operating system load requests for sending and receiving data is less than in the prior art, but this number is larger than in the first embodiment. 12 shows a cluster 100A according to the second embodiment. In 12 agrees the structure of elements bearing the same reference numerals as elements in 1 , coincide with the structures of these identically labeled elements of the first embodiment.

Notwithstanding the first embodiment, the request table in the present embodiment 17 , the requirement areas 12 and 14 and the request table origin register 5 in each of the clusters 100A unavailable.

In 12 correspond to registers 122 . 123 . 124 . 125 . 126 and 129 each of the registers 22 . 23 . 24 . 25 . 26 and 29 from 1 , These registers are directly to the bus 3 connected so that data from the CPU 1 directly into these registers as main memory 2 can be enrolled. 130 denotes a register attached to the bus 3 is connected and the data directly from the CPU 1 as well as the main memory 2 can read. The registry 122 serves to store the address CL of the transmission reception cluster. The registry 123 serves to store the communication area identification ID of the real communication area 13 which is assigned to the transmission reception process. The registry 124 serves to store the offset SO from the real head address of the real communication area 13 of the data reception area in the real communication area 13 according to the virtual communication area 11 the transmission reception process. The registry 125 is used to store the offset FO of the data reception flag. The registry 126 serves to store the data length LEN of the data to be transmitted. The registry 129 serves to store the real head address ADR of the data as sent by the origin of transmission process. The transmission circuit 28 refers to the register 130 whose state CC shows if the circuit 28 busy or not. 127 denotes a buffer for storing from the main memory 2 data to be sent. 107A denotes a memory access circuit for reading a value as below a position of the memory address from the main memory 2 or to write this value into the displayed register or main memory 2 , or for writing the value on the displayed register or the main memory 2 in a special address of the main memory 2 if the memory address has been specified.

Now, that part of the operation of the parallel processing computer of the present embodiment which differs from the first embodiment will be described with reference to FIG 13 he follows.

First, the initialization of the parallel processing computer will be described. Home before lying embodiment, no processing for a request table 17 and a request table origin register 5 made as per 1 because these functional groups are not present in the present embodiment. The other operations are the same as those in the first embodiment.

Now the process initialization will be described. The present embodiment will not process for a virtual processing area 12 and a virtual request area 14 made, since such areas are not present in the present embodiment. However, within the operating system, a table (not shown) is created that has the same contents as the location table 12-2 in the virtual request area 12 according to 1 , The other operations are the same as those in the first embodiment.

Now, the data transfer between processes according to the invention will be explained. In the present embodiment, the procedure in the transmission originating process is different from that in the first embodiment, and the rest of the procedure is the same as in the first embodiment. Therefore, with reference to 13 only the different functions explained.

step 61 : Send system call

One User Program issues a system call to the operating system and passes the control to the same. This call has the same format as the call command of the library function in the aforementioned first Embodiment.

step 62 : Conversion of arguments

When a system call has been issued, the operating system determines the address of the cluster on the network in which the transmit receive process is present, and determines the communication range identifier of the real communication range 13 which is assigned to the transmission reception process, based on the name of the transmission reception process. In this case, the content stored in advance in the process initialization in the table (not shown) within the operating system is used (corresponding to the content of the location table 12-2 in the first embodiment). The operating system determines the real head address of the data to be transmitted in the real communication area 13 of the main memory 2 based on the virtual head address of the data to be sent, including the page table 15 is used. Then, the operating system obtains the offset values SO and FO of the head address of the virtual communication area 11 within the transmission reception process, from the virtual address of the data reception area and the virtual address of the data reception flag, in the same manner as in the first embodiment.

step 63 : Setting Parameters in Registers

The operating system reads the CC state 130 over the bus 3 to make sure that the transmission circuit 28 is not busy, and sets the address CL of the transmission destination cluster, the communication area ID of the real communication area associated with the transmission reception process 13 , the offset SO of the data reception area, the offset FO of the data reception flag, the data length LEN of the data to be transmitted and the real head address of the data to be transmitted in registers 122 . 123 . 124 . 125 . 126 respectively. 129 , The operating system then passes the flow control to the user program.

step 64 : Execute the next command

To Completing the read operation gives the operating system control back to the user program, around the next Execute command.

step 65 : Data transfer

The transmission circuit 28 forms by using the contents of the registers 122 . 123 . 124 . 125 and 126 and the data buffer ( 2 ) a packet and sends it to the network 4 ,

If the package from the network 4 is received, the same procedure as in the first embodiment takes place, which is why this process is not described here.

Now the completion of the process will be described. In the present embodiment, deviating from the first example, the requirement areas 12 and 14 not used. Therefore, it is not necessary to delete the request areas following completion of the process.

In order to are the processes of the second embodiment sufficiently described.

According to the present embodiment, the transmission origin cluster claims the operating system, so that the overhead becomes slightly larger than in the first embodiment. Unlike the known technique, however, no transmit buffer and no receive buffer must be created within the operating system, as in the case of First embodiment, so that the overhead for the transmission and reception of data compared to the prior art can be reduced. Moreover, the present embodiment has a simpler circuit structure than the first one.

Embodiment 3

A third embodiment of the invention will now be described with reference to FIG 14 described. This third embodiment is a modification of the second embodiment, therefore mainly different points are explained. The present embodiment is the same as the second one in that the origin of transmission process sends data to the network under operating system load, whereas the transmission reception process receives the data without using the operating system. However, the present embodiment differs from the second in that the operating system has parameters, as required for data transfer, in main memory 2 leveled. 14 shows a cluster 100B according to the present embodiment. In 14 are such elements that bear the same reference number as those in the 1 to 12 the same elements as there with the same structure. In 14 designated 218 a request area in the main memory 2 , which requirement area 218 is handled by the operating system. 230 denotes a request area origin register for storing the head address of the request area 218 , 222 . 223 . 224 . 225 . 226 and 227 designate registers that correspond to the registers 122 . 123 . 124 . 125 . 126 respectively. 127 in the second embodiment correspond. The registry 222 serves to store the cluster address CL of the transmit receive cluster in the network. The registry 223 serves to store the communication area identification ID of the real communication area 13 which is assigned to the transmission reception process. The registry 224 serves to store the offset SO of the data reception area in the real communication area 13 , which is assigned to the transmission reception process. The registry 225 is used to store the offset FO of the data reception flag. The registry 226 serves to store the data length LEN of the data to be transmitted. The registry 229 is used to set a value representing the state CC of the transmission circuit 128 displays. The registry 227 is a data buffer for storing the content of the data to be sent over the network. 207 denotes a memory access circuit for accessing the main memory 2 if an address has been specified to store a value in a displayed register or to write a value of the register to main memory.

Of the Operation of the parallel processing computer according to the present embodiment will now be described. It only deals with processes that differ from those of the second embodiment differ.

First, the initialization of the parallel processing computer will be explained. In the present embodiment, when the operating system is started, the request area becomes 218 in main memory 2 ensured, and the real header of the request area 218 is in the request area origin register 230 set. Other procedures agree with those of the second embodiment.

Now, the data transfer according to this embodiment will be explained between processes. In the present example, the flow of the transmission originating process differs from that in the second embodiment. Therefore, only the difference with reference to 15 described.

step 61 : Send system call

Of the The process of issuing a system call by the user process is the same as in the second embodiment.

step 62 : Convert arguments

Of the Process is the same as in the second embodiment.

step 66 : Setting values in the request area

The operating system reads the CC state 229 over the bus to make sure the transmission circuit 28 is not busy and she puts in the requirement area 218 In the storage room 2 the address CL of the transmission receiving cluster, the communication area ID of the real communication area 13 assigned to the transmission reception process, the offset SO of the data reception area, the offset FO of the data reception flag, the data length of the data to be transmitted, and the real head address of the data to be transmitted. The memory access circuit 207 is started based on these set values. It is also possible to have a character holder (semaphore) in the request area 218 to provide and the memory access circuit 247 to start over the character carrier. The operating system then returns the flow control to the user program to execute the next command ( 64 in 15 ).

step 67 : Setting Parameters in Registers

The operating system issues a command to read the request area 218 over the bus 3 to the request area access circuit 21A , This generates every entry of the requirement area 218 from the request range origin register 230 , reads the contents of each entry through the memory access circuit 207 and sets the address CL of the transmission destination cluster, the communication area ID of the real communication area 13 assigned to the transmission reception process, the offset SO of the data reception area, the offset FO of the data reception flag and the data length LEN of the data to be transmitted in the registers 222 . 223 . 224 . 225 respectively. 226 , The memory access circuit 207 copies the data to be sent from main memory 2 in the data buffer 227 based on the real header address of the data to be sent.

step 65 : Data transfer

After the registers specified above are set, the transmit circuit structures 128 a package using the contents of the registers 222 . 223 . 224 . 225 and 226 and the buffer 227 and she transmits the packet to the network.

If the package from the network 4 is received, the flow is the same as in the second embodiment, and therefore the description of this flow is omitted here.

In order to are the processes of the third embodiment sufficiently described.

According to this embodiment Is it possible, an effect corresponding to that of the first embodiment to obtain, however, with a simpler structure than in the first embodiment, where processes are similar in the second embodiment available.

Embodiment 4

Hereinafter, a fourth embodiment of the invention will be explained. This is a modification of the third embodiment. The structure of the cluster of the fourth embodiment is the same as that of the third embodiment, and therefore the explanation is explained with reference to FIG 14 he follows. However, the requirement area becomes 214 used in a different way than the request area origin register 230 , Accordingly, this difference will be mainly explained.

First, the system initialization will be described. In the present embodiment, the request area is 218 not in main memory 2 set, so unlike the third embodiment. Therefore, the request area becomes 218 not ensured when the system is initialized, but it is ensured at the time of data transfer. At the time of system initialization, no value will be in the request scope origin register 230 set.

With reference to 16 the process executed by the operating system in the transmission originating process is explained.

step 61 : Send system call

This Process is the same as in the third embodiment.

step 62 : Convert arguments

This Process is the same as in the third embodiment.

step 68 : Setting values in the request area

The operating system secures the request area 218 In the storage room 2 and sets in the requirement area 218 the address CL of the transmission destination cluster, the communication area ID of the real communication area 13 assigned to the transmission reception process, the offset SO of the data reception area, the offset FO of the data reception flag, the data length LEN of the data to be transmitted and the real head address of the data to be transmitted.

step 69 : Setting Values in the Request Area Origin Register

The operating system reads the CC state 229 to make sure the transmission circuit 128 is not busy, and it sets the header address of the request area 218 to the value of the request area origin register 230 , so that the memory access circuit 207 and the transmission circuit 128 be initialized. The operating system then passes the flow control to the user program so that the next command ( 64 in 16 ) is performed.

step 67 : Setting Parameters in Registers

Of the Process is the same as in the third embodiment.

step 65 : Data transfer

Of the Process is the same as in the third embodiment.

If a package from the network 4 is received, the flow is the same as in the third embodiment, so this is not explained here.

In order to is the process in the fourth embodiment essentially described.

In the present embodiment, the request area 218 be ensured whenever data transmission is carried out. If the control is done so that every CPU 1 in the cluster, the requirement area 218 under a different address in main memory 2 ensures it becomes possible to take the steps 61 . 62 and 68 in every CPU 1 simultaneously execute in parallel. With this arrangement, it is in parallel with the operation of the transmission circuit 128 , after starting by the one of a specific CPU 1 executed step 69 possible for another CPU 1 the steps 61 . 62 and 68 executes and another CPU 1 the step 69 right after the completion of the work of the transmission circuit 128 performs. As a result, with this embodiment, the number of overhead operations in the operating system when transmitting data can be further reduced from the number required in the third embodiment.

Embodiment 5

17 shows the construction of a parallel processing computer according to a fifth embodiment of the invention. In 17 describe 501 . 502 . 503 and 504 Processors that all have the same structure. 505 denotes a main memory in which the processes 501 and 502 share while 506 denotes a main memory into which the processors 503 and 504 share. The processors 501 and 502 and the main memory 505 form a first cluster while the processors 503 and 504 and the main memory 506 form a second cluster. 507 denotes a transmission circuit connected to the first cluster. 508 denotes a receiving circuit connected to the second cluster. The first cluster has a receiving circuit similar to the receiving circuit 508 of the second cluster, but the receive circuit of the first cluster is in 17 not shown to simplify the drawing. Accordingly, the second cluster has a transmission circuit corresponding to the transmission circuit in the first cluster, but also this transmission circuit is omitted in order to simplify the drawing. 509 denotes a network for connecting the first cluster and the second cluster; it transmits a message from the transmission circuit 507 of the cluster to a specified destination.

At the present embodiment Two processors are used to form a cluster, wherein two clusters can be used to simplify the drawing. However, the technique of the invention also use three or more processors to make a cluster, and it can also use three or more clusters.

It will now be the structure of the processors 501 to 504 explained. With the exception of a new command described below, the processors 501 to 504 have the same structure as a known microprocessor, z. For example, the H32 microprocessor from Hitachi Ltd. In 17 is the internal structure only for the processor 501 shown to simplify the drawing. In 17 designated 510 an execution control circuit for controlling the instruction execution sequence of the processor 501 , 511 denotes a PSW (program status word). 511-1 denotes a privilege status panel within the PSW 511 , with the width of a bit. When the display panel 511-1 has the value 1, is the processor 501 in privileged status, whereas it is in nonprivileged status when the display panel 511-1 has the value 0. 511-2 denotes a value PC (Program Counter) for storing the address of the instruction being executed. 512 denotes a command register for storing the executed command. 512 denotes a command decoder. 514 denotes a path table base register for storing the memory address of a path table described later. 515 denotes a path table length register. 516 denotes an adder and 515 a comparator. 518 denotes an address translation circuit for translating a virtual address as indicated by a command into a real address. The address translation circuit 518 can be readily structured according to the prior art. 519 denotes a condition code register for storing a value as determined by a command description based on the result of executing a command. 520 and 521 are circuits for reading values from main memory 505 , 522 denotes a privilege instruction execution decision circuit and 523 denotes an access authorization decision circuit. 524 and 525 denote AND circuits.

The main memory 505 has the following. 528 denotes an access enable circuit for a portion of an operating system. 529 denotes an operating system area. To access the operating system area 529 It is necessary to send a signal into the operating system area access enable circuit 528 enter. It is possible to access other areas without inputting a signal to the latter circuit. 530 denotes a path table given below. The entry in the path table 30 has the in 18 displayed format. 531 denotes egg Necessary for one in the processor 501 currently running process. 502 refers to a virtual space associated with the process as it currently is from the processor 501 is performed. 17 shows only a single virtual space, that of the processor, to simplify the drawing 501 executed process is assigned. However, in the device according to the invention, other virtual spaces can also be used. A virtual space may be readily structured according to the prior art. 533 refers to data to be transferred into the virtual space.

The transmission circuit 507 has a function to send data to the network 509 based on a command from the processor 501 or from the processor 502 on. 534 denotes a transmission register for storing a message to be transmitted to the network, 526 denotes a transmission control circuit for transmitting the content of the transmission register 534 to the network 509 via a line L6, as long as a transmission interruption signal is not via a line L7 from the network 509 was entered from.

The receiving circuit 509 has the following elements. 523 denotes a receive register for storing one over the network 509 via a line L18 and a reception control circuit 527 incoming message. 536 denotes an address translation circuit for deciding whether a real address can be obtained from a page table origin (PTO) value and a virtual address (VA) value, as in a reception register 535 and outputting the real address obtained via a line L10 when this real address has been obtained. The address translation circuit 536 gives a signal to a line L11 if no real address can be obtained. 537 denotes an address generating circuit. 538 and 539 denote write circuits for writing data into the main memory 506 ,

The main memory 506 has the following. 548 denotes an operating system access enable circuit. 549 denotes an operating system area. To access the operating system area 549 it is in case of accessing the main memory 505 required, a signal in the operating system area access enable circuit 548 enter. 550 denotes a page table. 551 denotes a virtual space in which data is to be written in the data transmission as explained by the present embodiment. 525 denotes a data storage area in virtual space 551 , 553 denotes a receive intercept buffer, and 554 denotes a data storage area in the same.

The operation of the parallel processing computer according to this embodiment will now be described. In the parallel processing computer according to the invention, the first and second clusters are closely coupled multiprocessors which load an initial program after the power supply is turned on. This is done in the same way as in closely coupled prior art microprocessors, so that the operating system in each cluster is initialized independently of the other. In this case, the system operation areas become 529 and 549 in the main memories 505 and 506 ensured. In the drawing, units are omitted for the sake of simplicity, as they are required for the initialization, such. B. magnetic disk units.

If a command to initialize a user program into a certain Cluster was entered after initializing the operating system, The operating system of this cluster creates a virtual space and then generates in this one process, as it is to execute the User Program is required. User processes in the above have been generated, then generate processes such as They are required to run the user programs in their own cluster and in other clusters. A group of user programs directly or indirectly through An initialization command is generated, called a job. Every job becomes assigned by the operating system a Jobidentifiziermarkierung. Every user process is going through the user assigned a name, so that each user process under the jobs is unique. If a double-name process within Jobs generated due to a user program error or the like the operating system determines this duplication and terminates the corresponding job in a non-normal way. Several processes can in a cluster when user processes are generated. The method of creating user processes may be similar as in a known method, for. As the method, as in a system with distributed Prozessaren is used by a LAN system are connected. Processes with the above Procedures were generated lead Calculations of how they are displayed by the program, what by mutual transfer of Data takes place.

As indicated above, the processors can 501 to 504 have a construction having an instruction execution circuit related to the invention added to a microprocessor which may be constructed as a known processor. Accordingly, of a series of instructions of a process to be executed by each processor, such instructions are executed within the respective processor can be such. As arithmetic instructions, processed in the same manner as is done by a known microprocessor.

Everyone Processor with the structure as in a parallel processing computer according to the invention, has an address translation circuit on, the similar is like a known microprocessor and the administration of the virtual space. Each process corresponds clearly a virtual space and executes a program in virtual space. Accordingly, in each cluster, the mapping corresponds to a virtual one Space to associate a process.

A process generation process will now be described with reference to FIG 17 described. In the parallel processing computer according to the invention, when generating a user process, the operating system generates a path table corresponding to the process to be created in real memory in the operating system area 529 , (As the operating system operates in privileged state, the command becomes 1 into the privilege status panel 511-1 as a signal to the operating system area access enable circuit 528 given so that the operating system the path table in the operating system area 529 can generate. If the operating system is in nonprivileged status, it is not possible within the operating system area 529 overwrite existing path table). According to 17 becomes one in virtual space 529 to be executed user process associated path table 530 generated in the first cluster. In this case, a field V of the entire entry of the path table becomes 530 initialized to the value 1. The path table is managed by a value BASE that represents the head address, and a value LEN that represents the length of the path table. Both BASE and LEN values are handled as part of the context in which the process is placed. 19 shows the content of the context of the process. According to 19 becomes the content of PSW in a field 103 stored, the contents of the register in a field 104 stored and other control information in a field 105 saved. These contents are consistent with those of related values as managed by a known operating system. In the context area designate 106 and 107 Fields for storing the above values BASE and LEN, which are new according to the invention.

When the timing of a virtual space 532 corresponding process in the processor 501 is set, the operating system of the first cluster stores the contents of the context area 531 into the register in the processor 501 one. In the parallel processor according to the invention are the path table base register 514 and the path table length register 515 in the processor 501 as exclusive registers for storing the newly introduced values BASE and LEN as parts of the context. In addition, the parallel processor has a BASE set command and LEN set command as instructions for storing a respective value in these registers. Both commands are privileged commands, and if these commands are to be executed in nonprivileged status, an interrupt occurs in the processor 501 on. If a straight through the processor 501 executed command is switched for a reason and the processor 501 is released, the value of the register of the processor 501 in the context area 531 stored, contrary to the above.

The scheme of instruction execution in the processor 501 will now be explained. First, from the main memory 505 a command based on the field 511-2 of the PSW 511 in the execution control circuit 510 read out, and this command is in the command register 512 saved. The field OP of the command register 512 stored operation code is put into the privilege instruction execution decision circuit 522 entered. This also includes the value of the privilege status panel 511-1 entered. It gives to the execution control circuit 510 a signal only if the entered operation code indicates a privileged instruction and if the privilege status indicator field 511-1 indicates the nonprivileged status. This arrangement causes an interrupt in the processor 501 on. In other cases, a command is executed when a command decoder 513 decode the operating code and generate a signal as required to process the decoded command. 20 shows the format of the BASE set command. According to 20 will be in one part 108 the operation code of this instruction is stored, and a first operand 109 stores the in the path table base register 514 value to be set. In pieces 110 and 111 stored values are not used. In the processor 501 the present command is executed with the following procedure.

First, the command decoder decodes 513 the command as described above, and outputs a signal to the line L1 when the read command is the BASE set command. Since the command is a privileged command, it is not executed when the contents of the privilege status panel 511-1 not 1. On the other hand, when the content is 1, a signal from the AND circuit becomes 524 output. With the help of this signal, the in the field OP1 of the command register 512 stored value in the path table base register 514 saved.

21 shows a format for the LEN setting command. According to 21 saves a part 112 an operation code for the instruction, and a first operand stores the in the path table base register 514 value to be set. In pieces 114 and 115 stored values are not used. In the processor 501 the command is processed in the following way.

First, the command decoder decodes 513 command, as stated above, and outputs a signal to line L2 if the read command is the BASE set command. Since the command is a privileged command, it will not execute if the value of the display field 511-1 not 1. If, on the other hand, this is the case, the AND circuit 525 a signal is output. With this signal, the field OP1 of the command register becomes 512 stored value in the path table length register 515 set.

A process with the relational value loaded in the register by executing the BASE set instruction and the LEN set instruction, which process is assigned to the processor 501 assigns a path via data transfer before the data transfer to another process within the job.

First, the process invokes a system call to set the path. The specification of this system call is the following:
Path = openpath (name);
"Name": Name of the other process (once within the job)
"Path": value of the path returned by the operating system.

Of the Path is set by the following sequence of steps.

First, will the operating system of the cluster with a process that belongs to the same job as the process executed by the system call, investigated, whether a process with the assigned name exists. The operating system of the cluster, in which the process with the assigned name tells the requesting cluster the Number of the cluster and a page table origin for structuring a virtual space that clearly corresponds to the displayed process. In other cases tells the operating system to the requesting cluster that no process with the given name is present.

If a process with the specified name was not found, the system call returns a special value, to indicate to the user process that the Process not was found.

If a cluster with the specified name was found, an entry with the value 1 in field V becomes optional from the path table 530 is selected according to the user process that performed the associated system call, and 0 is written in this field V, the number of the cluster in which the determined process exists is written in the field CL, and the page table origin of the virtual space corresponding to the determined process is written in the field PTO. Then the number of the associated entry is returned to the user process. In other words, this means that the entry number of the path table 530 the value of the path becomes.

When the above preparation has been completed, the process can transfer data to another process. Next, the specification for a remote storage command for transferring data will be explained. The remote store command is a nonprivileged command and has a format as defined in US Pat 22 is shown. In 22 describe 117 . 118 and 119 virtual addresses within a virtual space that corresponds to the other process. 116 is the operation code, 117 is the virtual address for storing a value of the path for the transmission, 118 is the virtual address for storing the virtual address of the data to be sent in the virtual space of the process for executing the command, and 119 is the virtual address for storing the data to be sent. The command is executed in the following way. The scheme of the expiration of the command is in 23 shown.

* Execution of the remote storage command by the user process ( 150 in 23 ).

The user process reads the command from main memory 505 according to the field 511-2 of the PSW 511 in the execution control circuit 510 and stores the instruction in the instruction register 512 , Since the command is a nonprivileged command, the privilege command execution decision circuit gives 522 no signal off. The command decoder 513 decodes the field OP of the command register 512 stored operating code and generates an output signal on the line L3 when the read command has been turned off, so that a remote storage command is present. Then the following operating sequence is started.

* First examination ( 151 in 23 )

The processor adds the value of the first operand ( 117 in 22 ) with the help of the adder 516 to the in the path table base register 514 stored value to get the entry address that is the path in the path table 530 corresponds, and it generates an output signal for the read circuit 520 , This receives the signal via the line L3, accesses the main memory 505 based on the adder 516 outputted entry address and generates a signal on the line L4, if the value in the field V of the associated entry 1 (in this case access to the main memory is an access to the operating system area 529 , As a signal on the line L3 in the operating system area enable circuit 528 can be entered, the read circuit 512 even in the nonprivileged state to read).

The processor compares the value stored for the path in the first operand with the content of the path table length register 515 What with the help of the comparator 517 he follows. If the value for the path is greater than the content in the path table length register 515 , the processor generates an output signal on line L12.

The access authorization decision circuit 523 determines whether the value for the path given by the instruction corresponds to a valid data transfer, based on the signals on lines L3, L4 and L12, and generates an output signal for the execution control circuit 510 if the value for the path is invalid. The invalid case is the case where a signal has been output on at least one of the lines L4 and L12 as a result of executing the command.

The foregoing describes the first investigation. When a signal from the key slot decision circuit 523 as a result of the first examination by the execution control circuit 510 is received, this locks the execution of the command and interrupts the process 501 ,

* Second investigation ( 152 in 23 )

The processor checks the state of the transmission control circuit 526 based on the signal on line L3.

If, as a result of the second investigation, it turns out that the data stored in the transmit register by the previously executed remote store command 534 set value is not yet complete to the network 509 was transferred, the processor sets the operation code 1 via line L13 in the operating code register 519 and ends the execution of the command. The processor executes the following procedure when in the transmit register 514 completely set value to the network by the remote store command previously executed 509 was transferred.

* Set the values in the fields CL and PTO ( 153 in 23 )

In the same way as in the first investigation, the reading circuit takes effect 520 on the memory 505 with the help of the entry address too, as given by the adder 515 is output and outputs the contents of the field CL and the field PTO of the associated entry to the line L5. The sender register 514 sets the value outputted to the line L5 to the values of the fields CL and PTO based on the signal on the line L3.

* Set the value in field VA ( 154 in 23 )

Then the processor sets the in the third operand ( 119 in 22 ) stored address directly in field VA of the sender register 524 based on the signal on line L3.

Setting the data field ( 155 in 23 )

Subsequently, the address translation circuit translates 518 in the second operand ( 118 in 22 ) stored virtual address in the real address and generates an output signal to the read circuit 521 , This attacks the memory 505 under the real address based on the signal on the line L3 and outputs the data to be sent to the data field of the transmission register 534 out. This sets the data to be sent for the data field based on the signal on line L3.

* Data transfer ( 156 in 23 )

If the data in the manner described above in the transmit register 534 are set, the condition code 0 in the condition code register 519 via the line L13, whereby the execution of the command is terminated. The transmission control circuit 526 , which has received the signal via the line L3, begins with the contents of the transmission register 534 to the network 509 issue.

The expiration of the remote store command ends with the above operations, and the processor 501 executes the next command ( 157 in 23 ).

Whether data succeeds to the network 509 or not, can be checked by a conditional branch instruction, depending on the value of the condition code. If it is clear from the value of the condition code that the data has not been transmitted successfully, the command can be executed again.

The network 509 transmits a message to the receiving circuit, e.g. B. the receiving circuit 508 of the cluster specified in the message. As a result, the values of the field PTO, the field VA and the data field of the transmission register 534 to the values of the field PTO, the field VA or the data field of the receive register 535 set what is done by the receive control circuit 527 he follows.

* Verification of address translation capability ( 160 in 23 )

When a message has been received, the receiving circuit transmits 508 the contents of the PTO and VA fields of the receive register 535 to the address translation circuit 536 , After receiving the contents of these two fields, it sends a signal via line L19 to the operating system area access enable circuit 548 based on the page table origin stored in the field PTO and the virtual address (the content of the field VA) of the associated virtual space 551 which makes it possible to access the operating system area. This accesses the address translation circuit 536 via line L20 to the page table 550 to and checks if the real address of the main memory 506 can be obtained or not.

* Address translation ( 161 in 23 )

If a real storage area corresponding to the virtual address exists and the address translation is possible, access to the operating system area is possible in the manner described above, whereupon the receiving circuit is in the operating system area 549 accommodated page table 550 accesses via line L20, which page table the virtual space 551 corresponds to the field PTO in the receive register 535 equivalent. Thereby, the receiving circuit performs an address translation to the real address from the virtual address in field VA of the receive register 535 and outputs the physical address obtained as a result of the address translation and a write request signal to the line L10.

* Writing data ( 162 in 23 )

The writing circuit 539 which has obtained the above-mentioned output signal, generates an output signal for the address obtained via the line L10 on the line L14 and generates an output signal for the content of the data field of the reception register 535 on the line L15, causing the write circuit 539 the content of the data field of the register 535 in the data storage area 552 of virtual space 551 writes, which completes the process.

* Address generation ( 170 in 23 )

If the above-described address translation is not possible or if the address required for page output can not be obtained, the address translation circuit outputs 536 a signal to the line L11. With the above arrangement, the address generating circuit 537 generate an address for the area within the receive intercept buffer that contains the contents of the receive register 535 can save.

The receive catch buffer 553 was previously within the operating system area 549 of the main memory 506 secured by the operating system of the associated cluster.

* Standby of the receive register ( 171 in 23 )

If that of the address generation circuit 537 generated address via the line L17 of the write circuit 538 has been supplied, this gives a signal via the line L18 to the operating system area access enable circuit 548 off to the writing in the operating system area 549 release. Then there is the write circuit 538 via a line L30 the address to the main memory and writes the contents of each field of the receive register 535 via a line L31.

* Call the operating system with an interrupt ( 172 in 23 )

The address generation circuit 537 generates an interrupt to the processors 503 and 504 via the line L21.

* Page load process ( 180 in 23 )

Of the Processor in which an interrupt occurred orders through a virtual page-reading process Address that the reason for the interrupt formed a real address too.

* Simulation of the receiving circuit ( 181 in 23 )

The operating system removes the receive intercept buffer 553 the message and basically simulates the flow of data processing by the receiving circuit 508 is to execute.

The data transfer is completed as described above.

If an address can not be generated because in the receive catch buffer 553 in the address generation described above ( 170 in 23 ) no space is free, transmits the address generation circuit 537 a signal via the line L16 to the reception control circuit 527 , When it has received the signal, it sends a receive intercept signal to the network via line L9 509 to transfer the message from the network 509 intercept on line L8. The address generation circuit 537 generates an interrupt for the processor via line L21 503 or the processor 504 to call the operating system and one Extension of the receive intercept buffer 553 to request. When the expansion is completed, the operating system announces the completion of the address generation circuit expansion 537 via line L21 with. The address generation circuit 537 that has received this message has the reception control circuit 527 via line L16 to restart the reception. After the reception control circuit 527 received this command, it informs the restart of the reception to the network 509 via line L9 with.

When all required data transfer has been completed, the process executes a system call to release the path. The specification of this system call is the following:
closepath ("path");
"Path": Value for the path

To clear the path, the value 1 in field V is set for the entry, as indicated by the argument "path" in the path table 530 is specified according to the process that has executed the system call.

Embodiment 6

The sixth embodiment is a modification of the fifth embodiment, therefore essentially only different points will be explained. 24 shows the construction of a parallel processor according to the sixth embodiment of the invention. In 24 For example, elements having the same reference numerals as those in the fifth embodiment have the same construction as the elements there.

In 24 describe 501 . 502a . 503a and 504a Processors with the same structure. 505 and 506 denote main memory. 507a and 508 denote a transmitting circuit and a receiving circuit, respectively. 509 denotes a network.

In the processor 501 designated 512a a command register. This is different from the command register 512 of the fifth embodiment in that the former stores three operands while the latter stores only two operands. In the processor 501 are further construction elements as in the processor 501 from 17 present, which are identified by like reference numerals, when they correspond to each other.

In the transmission circuit 507a describe 534a-1 and 534a-2 Sender register, the sender register 534 of the fifth embodiment, however, which is divided into two, as shown in the figure.

rhyme present embodiment is the remote storage command of the fifth embodiment no longer whereas, two commands related to a remote storage preparation command and a remote storage execution command new added are. These two new commands are nonprivileged commands.

25 shows a format for the remote storage preparation command. In 25 designated 200 an operation code for this instruction; a first operand 201 is a value for the path. One in a field 202 stored value is not used.

26 shows a format for the remote storage execution command. In 26 designated 204 an operation code for this instruction; a first operand 205 is the virtual address within the virtual space corresponding to the other process for storing data to be sent. A third operand 206 is a virtual address of the data to be sent as it exists in virtual space corresponding to the process executing this command.

The operation of the parallel processor according to this embodiment will now be explained. The operation is the same as that in the fifth embodiment, except that the operations for the remote storage command no longer existing as compared with the fifth embodiment are executed by the two additional commands, that is, the remote storage preparation command and the remote storage execution command. Therefore, the processes according to these two instructions will be described with reference to FIGS 24 and 27 described.

It will be first the expiration for described the remote storage preparation command. This command is performed as follows.

* Execution of the remote storage preparation command by the user process ( 182 in 27 )

First, the user process reads the instruction from main memory 505 depending on the field 511-2 of the PSW 511 in the execution control circuit 510 and stores the instruction in the instruction register 512a , Since this command is a nonprivileged command, the privilege command execution decision circuit generates 522 no output signal. The command decoder 513 decodes the field OP of the command register 512a stored operating code and generates an output signal on the line L3 when it is clear that the read command is the remote memory preparation command. Then the following series of operations is performed.

* First review ( 151 in 27 )

The processor adds with the help of the adder 516 the value of the first operand ( 201 in 25 ) stored path to that in the path table base register 514 stored value to obtain an area address that corresponds to the path in the path table 530 corresponds, and generates an output signal for the read circuit 520 , After this has received the signal via the line L3, it reaches through the adder 516 output registration address to the main memory 505 and generates on line L4 an output signal when the value of field V of the entry 1 is. (In this case, the memory access is an access to the operating system area 529 , However, because a signal on line L3 enters the operating system area enable circuit 528 is entered, the read circuit 520 perform a read even if it is not in the privileged state). A signal is output via the line L4 if the value of the field V of the entry 1 is.

The processor further compares the path value stored in the first operand with the content of the path table length register 515 what through the comparator 517 he follows. If the value for the path is greater than the contents of the path table length register 515 as determined by the comparison, the processor generates an output signal on line L12.

The access authorization decision circuit 523 decides whether or not the value for the path assigned by this instruction designates a valid data transfer based on the signals on the lines L3, L4 and L12, and generates an output signal for the execution control circuit 510 if it turns out that the value for the path is invalid. The invalid case is when an output signal occurred on at least one of the lines L14 and L12 after the command was executed.

With the foregoing, the description for the first check is completed. When a signal due to the first check from the access authorization decision circuit 523 from the execution control circuit 510 is received, this locks the execution of this command and generates an interrupt for the processor 501 ,

* Second review ( 152 in 27 )

The processor checks the state of the transmission control circuit 526 based on the signal on line L3.

If, as a result of the second review, it is clear that those in the broadcasting registers 534a-1 and 534a-2 values set by the remote store execution command previously executed are not yet fully connected to the network 509 the processor sets the condition code register 519 via line L13 to the condition code 1 and ends the execution of the command. The processor performs the following operations when in the transmit registers 534a-1 and 534a-2 set values, as previously performed by the remote store execution command, all to the network 509 were transferred.

* Set the values of the fields CL and PTO ( 153 in 27 )

First, as in the first review, the reading circuit intervenes 520 with the help of the entry address as given by the adder 516 is output to the main memory 505 and outputs the contents of the fields CL and PTO of the entry to the line L5. The sender register 534a-1 sets the value output to line L5 in field CL and the value in field PTO based on the signal on line L3.

By the above explanations is the process for described the remote storage preparation command.

Now becomes the expiration for the remote storage execution command explained. This command is processed as follows.

* Execute the remote storage execution command by the user process ( 183 in 27 )

The user process first reads the command from the main memory 505 according to the field 511-2 of the PSW 511 in the execution control circuit 510 and stores the instruction in the instruction register 512a , Since this command is a nonprivileged command, the privilege command execution decision circuit generates 512 no output signal. The command decoder 513 decodes the field OP of the command register 512a stored operating code and starts the following series of operations after generating an output signal on a line L99, when it is clear that the read-out command is the remote storage execution command.

* Setting the field VA ( 154 in 27 )

Then, in the first operand ( 205 in 26 ) stored virtual address directly in field VA of the sender register 534a-2 based on the signal on line L99.

* Setting the data field ( 155 in 27 )

The address translation circuit 518 above sets the second operand ( 206 in 26 ) stored virtual address in a real address and generates an output signal for the read circuit 521 , This accesses the main memory 505 with the real address based on the signal on the line L99 and outputs the data to be sent to the data field of the transmission register 534a-2 out. This sets the data to be sent in the data field based on the signal on line L99.

* Data transfer ( 156 in 27 )

When setting the transmit registers 534a-1 and 534a-2 As described above, the transmission circuit sets the condition code 0 via the line L13 in the condition code register 519 and stops the execution of the error. The transmission control circuit 526 which has received the signal from the line L99 starts sending the contents of the transmission registers 534a-1 and 534a-2 to the network 509 ,

In order to becomes the expiration for the remote storage execution command completed.

As is apparent from the above explanation, by executing the remote storage preparation instruction, it is to set the value of the transmission register 534a-1 with subsequent execution of the remote storage execution command, it is possible to obtain an effect which agrees with that obtained when the remote storage command in the fifth embodiment is executed. Accordingly, the operation of the processor for receiving data is exactly the same as in the case of the fifth embodiment.

In order to is the explanation of the sixth embodiment completed the invention.

At the present embodiment the remote storage preparation command will then if in the same Process data to be repeatedly transmitted, executed only once, and the remote storage execution command will be executed according to the required number. In contrast, the fifth embodiment the remote store command repeatedly executed. Since the remote storage command of the fifth Embodiment the remote storage execution command is replaced, for the processing is much easier, the effect is that the Overhead, how to transfer it data is required, can be further reduced.

Embodiment 7

The seventh embodiment is a modification of the fifth Embodiment, However, this can be realized with a simpler structure, if a restriction is accepted in the method, as it is carried out in the fifth embodiment.

A restriction as for the fifth embodiment added becomes the seventh embodiment to receive, will now be explained.

At the fifth embodiment can be a virtual page in the virtual space of the data receiving process, which page to transmit through the remote store command is to be paged by the operating system. At present embodiment However, this becomes the limitation added that the said virtual page to be transmitted by the remote storage command in the virtual space of the data capture process, the real memory is assigned without exception.

Of the Expiration, according to the one virtual page is allocated to the real memory without exception and in which a page-wise output is not allowed, is an expiration with so-called side fixation. This can be done using conventional Technology can be easily realized.

The construction of a parallel process according to this embodiment can be realized by omitting a part of the elements of the construction of the fifth embodiment. 28 shows the structure of the parallel processor according to the present embodiment. This structure lacks the address generation circuit 537 , the write circuit 538 , the receive catch buffer 553 , the data storage area 554 the receive intercept buffer 553 and connected to these elements lines to the parallel processor of 17 ,

The Function of the parallel processor according to this embodiment is almost the same as that of the parallel processor of the fifth embodiment. Therefore, only differences are explained.

One The first difference is in initializing the process of receiving of data as they are to be transmitted by the remote memory command. According to the present Embodiment is when running the processes of the operating system for creating a virtual space for generating a process saved a real storage area, whose capacity with that the virtual page matches, the for the code area and the data area of the process after generation of space is required, and this real storage area becomes the virtual memory area completely associated with a page fix process for the entire virtual pages accomplished becomes.

A second difference is in the reception process in the process of receiving data as transmitted by a remote memory command. As described above, real memory is allocated to the virtual page of the process without exception, so that the processing of the address translation possibility check 160 from 23 that processes the function of the fifth embodiment is not required. Also, there are a number of processes starting from the address generation 170 not mandatory. Accordingly, it is in the process of receiving data through the data transfer 156 from 23 be transmitted, only required, the address translation 161 and then the data storage 162 make.

In order to is the description of the seventh embodiment of the invention essentially completed.

at this seventh embodiment the receive intercept buffer is not required, which makes the real Memory area and receive buffer management are not required. Therefore, there is an effect that the overhead in the Processor receiving data can be reduced.

Embodiment 8

The eighth embodiment of the invention is a modification of the seventh embodiment, but with many common points. Therefore, only differences are explained. 29 shows the structure of the parallel processor according to the eighth embodiment. In 29 are the structures of elements that bear the same reference numbers as elements in 17 the same as those of the elements in the fifth embodiment.

In 29 reference numbers 501c . 502c . 503c and 504c Processors with the same structure. 505 and 506 denote memory. 507c and 508c denote a transmitting circuit and a receiving circuit, respectively. 509 denotes a network.

In the processor 501c designated 999 an address translation circuit which is an arrangement newly introduced for this embodiment. Other components of the processor 501c are such as in the processor 501 from 17 present, wherein the same structural elements bear the same reference numerals.

In main memory 505 designated 530c a path table. Each entry in the path table 530c has a field V and a field CL. 530c denotes a table that corresponds to the table 530 in the fifth embodiment after removal of the field PTO corresponds.

In the transmission circuit 507c designated 534c a sender register that has three fields for values of CL, RA, and data.

In the receiving circuit 508c designated 535c a receive register.

The present embodiment Fig. 10 is a modification of the seventh embodiment in that that the Adreßübersetzungsablauf in terms of virtual space, in the data by the remote memory command to be written by the processor on the transmitting side. Of the Difference between the eighth and the seventh embodiment exists only in the function of the command "openpath", which calls a system call in the seventh embodiment corresponds to, and in the expiration of the remote memory command. Therefore, these become procedures explained. The process "openpath" in the seventh embodiment is the same as the fifth Embodiment.

First, will the process "openpath" explained. The Specification for "openpath" is the same as for seventh embodiment. This system call is executed in the following manner.

First, a cluster asks the operating system of the cluster with the process that belongs to the same job as the Process, which executed the system call whether the process has one given name. The operating system of the cluster, in which a process with given the given name, gives the number of the cluster and an information to the real address from the virtual address to win in virtual space, which clearly corresponds to the indicated process; the input is made to the requesting cluster. In other cases shows the requested cluster indicates to the requesting cluster that no process with the given name is present.

If no process with found the given name as a result of the above query the system call returns a special value to the user process that indicates that no process with the specified name was found.

If a cluster is found where the process with the given name exists, an entry with the value 1 in field V will optionally be in the path table 30 which is associated with the user process that executed the system call. Then, the value 0 is written in this field V, and the number of the cluster in which the detected process exists is written in the field CL inscribed. Moreover, information for obtaining the real address from the virtual address in the virtual space that uniquely corresponds to the associated process is set, and it becomes the entry number of the path table in the address translation circuit 999 is set, and the registration number is passed to the user process. In other words, the entry number of the path table becomes 530c the value for the path.

As a result, the address translation circuit 999 the real address is obtained based on the value for the path and the virtual address of the virtual space corresponding to the path value. The address translation circuit 99 can be structured using conventional technology.

It Now the execution of the remote storage command will be explained.

* Execution of the remote storage command through the user process

First, the command is according to the field 511-2 of the PSW 511 in the execution control circuit 510 from the main memory 505 read, and the command is in the command register 512 saved. This command is a nonprivileged command, therefore the privilege command execution decision circuit 522 no output signal generated. The command decoder 513 decodes the operation code as it does in the OP field of the instruction register 512 is stored. If it turns out that the read command is the remote memory command, a signal is output on the line L3 and the following series of operations are started.

* First review

The value for the path as stored in the first operand and the value as in the Path Table Base Register 514 is stored by the adder 516 summed up to get the entry address that matches the path in the path table 530c equivalent. The result of the input address is sent to the read circuit 520 output. This accesses the main memory 505 based on the entry address as given by the adder 516 after having received a signal via the line L3 and generates a signal on the line L4 when the value in the field V of the entry 1 is.

Then the value for the path as stored in the first operand is passed through the comparator 517 with the contents of the path table length register 515 compared. If the value for the path is greater than the contents of the path table length register 515 , which is determined by the comparison, a signal is output on the line L12.

Based on the signals on the lines L3, L4 and L12, the access decision decision circuit decides 523 Whether or not the data transfer value specified by this command for the path is valid. If the value is invalid, the decision circuit generates 523 an output signal for the execution control circuit 520 , The invalid case is when a signal has been output at least on one of the lines L4 and L12 as a result of executing the command.

The above concerns the first review. After the execution control circuit 510 the signal from the access authorization decision circuit 523 As a result of the first check, it suppresses the execution of this command and generates an interrupt in the processor 501 ,

* Second review

On the basis of the signal on the line L3, the state of the transmission control circuit 526 checked.

If, as a result of the second check, it turns out that the one in the sender register 534 value set by the previously executed remote memory command is not fully connected to the network 509 has been transmitted, the condition code in the condition code register 519 is set to 1 via line L13, completing the execution of this command. If the in the transmit register executed by the previously executed remote memory command 534 set value completely to the network 509 has been transferred, the following procedure takes place.

* Set the field CL

First, the reading circuit picks up 520 in the same way as in the case of the first check on the main memory 505 based on the entry address too, as given by the adder 516 is output, and outputs the content of the field CL of this entry to the line L5. The sender register 534c sets the value output via the line L5 in the field CL based on the signal on the line L3.

* Set the field RA

Subsequently, the value for the path stored in the first operand and the virtual address as stored in the third operand are written to the address translation circuit 999 entered. This outputs the real address for the receiving location of the data transmission. The sender register 534c sets the value outputted from the address translation circuit in the field RA based on the signal on the line L3.

* Set the data field

Subsequently, the data translation circuit translates 518 the virtual address, as stored in the second operand, in the real address and returns the converted real address to the read circuit 521 out. This accesses the main memory with the real address based on the signal on line L3 505 to and gives the data to be sent to the data field of the sender register 534c out. This sets the data to be sent in the data field based on the signal on line L3.

* Data transfer

When setting the station register 534c As is concluded above, via the line L13 of the condition code 0 in the condition code register 519 is set, which ends the process for this command. The transmission control circuit 526 , which has received the signal on the line L3, starts sending the contents of the transmission register 534c to the network 509 ,

If the transferring to the network was successful or not, with the help of a Branch instruction to be checked dependent from the value of the condition code. If it is from the value of the condition code it can be seen that the transmission the network was unsuccessful, the command will be executed again.

The network 509 transmits a message to the receiving circuit of the cluster specified in the message, e.g. B. to the receiving circuit 508c , As a result, the value for the field RA and the data field of the transmission register 534c in the field RA or in the data field of the receive register 535c through the reception control circuit 537 set.

Then the following procedure is executed.

* Writing data

The writing circuit 539 gives the contents of the field RA of the receive register 535c to line L14 and returns the contents of the data field of the receive register 535c to the line L15 and then writes the contents of the data field of the register 535c in the data storage area 552 of virtual memory 551 , which completes the process.

The data transfer is completed as described above.

According to the above embodiment the procedure in the receiving circuit of the cluster in which a Data reception process expires, simplified. Therefore, the operation of reading data and storing data becomes Data in the main memory compared to the procedure in the seventh embodiment faster when transferring data from many processes are concentrated on one cluster. In the result the communication overhead can be further reduced.

Embodiment 9

The ninth embodiment concerns the case that a Processor to an external device, e.g. B. an input / output device for data accesses.

If a processor according to the state the technology requests access to an external data device, prepares the operating system first a memory area for writing the data and protects it Memory area before that page by page is issued. For this purpose, a method exists according to which Memory area z. B. is backed up in real memory or at the space in the virtual space for page fix is secured. Then a command including the address to the external Device issued.

If the external device that received the command that was sent to the Memory has prepared data to be written, she writes the Data in the range given above, not output page by page has been.

According to the above the known technique known may be prepared for the external device Storage area during the response time of the external device not to perform the Program of the processor used when the operating speed the external device is lower than that of the processor.

Around to solve this problem, gives the present embodiment a method in which no problem occurs when the memory area, in the external organization has to write data, page by page was issued.

To solve this problem, a receive intercept buffer as described in connection with the fifth embodiment of the invention may be used. More specifically, the receiving circuit 508 and the receive intercept buffer 553 as shown in the fifth embodiment, connected between the external device and the processor.

When the processor accesses an external device for writing data, the Area for writing the data in the normal virtual memory area, and the virtual address of this area and a page table origin (PTO) command corresponding to the virtual space with this area are transmitted to the external device. If these are the process for reading, z. As the disk unit has started and prepared to write data, the external device transmits the PTO, the virtual address and the data to the receiving circuit, which is connected to the processor that has requested the data. Then, in the same manner as in the fifth embodiment, the receiving circuit judges whether or not the real storage area corresponding to the virtual storage area into which the data is to be written has been allocated by the address translation circuit. If a real memory space has been allocated, the data is written to this area. On the other hand, if a real memory area has not been allocated because of page read-out, an area is allocated which can be used as the receive intercept buffer, in the same way as the address generation circuit 537 in the receiving circuit 508 , and the PTO, the virtual address and the data are written in this area. Then the receiving circuit generates an interrupt in the processor. As a result, the processor pages-in the page output by the PTO, as well as the address stored in the receive intercept buffer, and then writes the data into that area.

According to this embodiment may be the area where the external device will write data can, as an area for normal page reading will be set. Accordingly occupied the external device even then no memory area for this external device during its response time is given when the operating speed the external device is slower than the operating speed of the processor, so that the Memory area for execution the program can be used by the processor.

According to the present Invention is to execute of data transmissions between user processes required, the transfer between the operating systems to initialize the cluster when the user processes start are. If indeed data transfer between user processes takes place when data from the virtual Space of the user process in a special cluster in the virtual Space of the user process can be transmitted in another room, the Transfer data directly be without them be copied to the buffer area of the operating system. Accordingly Is it possible, data transfer with a small overhead, without any unnecessary changes in the virtual space of the user process are needed, not in connection with data transmission stand.

Claims (5)

Intra-processor communication method in a multi-cluster parallel processor system ( 100 ), each of which has at least one processor ( 1 ; 501 . 502 ) and a main memory to be used by this at least one processor ( 2 ; 505 ) and with a network ( 4 ; 509 ) for connecting the plurality of clusters, wherein at least one process is performed with at least one associated virtual space within each cluster under the control of an operating system associated with each cluster, and the intra-processor communication method for transmitting transmission data from a transfer originating process associated with a first cluster to a second one Cluster-associated transmission receiving process is characterized by the following steps: ensuring a resident in the main memory real communication area ( 13 within each cluster for each process associated with the cluster, the real communication area being in a virtual communication area ( 11 ) within the virtual space associated with each cluster; Selecting a real communication area associated with the transmission reception process in the first cluster and a virtual write address at which the transmission data is to be written within a virtual memory allocated to the transmission reception process; Generating a packet in the first cluster containing the transmission data, a transmission range identification code for identifying the selected real communication range and an offset address for indicating the difference between a base address of the virtual communication range corresponding to the selected real communication range and the selected virtual write address; Sending the packet from the first cluster to the second cluster through the network ( 4 ; 509 ); Reading out a base address of the selected real communication area in the second cluster using the transmission area identification code included in the received packet; Generating a real address within the real communication area in the second cluster by adding the offset address contained in the received packet to the read base address; and writing the transmitted data into the second cluster to one of the generated real addresses speaking point in the main memory. The method of claim 1, wherein the writing of the Data without the use of the operating system. Parallel processor system with multiple clusters ( 100 ) and a network ( 4 ; 509 ) for connecting the plurality of clusters, wherein at least one process is performed with at least one associated virtual space within each cluster under the control of an operating system associated with each cluster, characterized in that each cluster comprises at least one processor ( 1 ; 501 . 502 ) and a main memory to be used by this at least one processor ( 2 ; 505 ); a real memory area resident in main memory ( 13 ) for each process associated with the cluster, wherein the real communication area is in a virtual communication area ( 11 ) within the virtual space associated with each cluster; means for selecting a real communication area associated with the transmission reception process ( 13 ) in the first cluster, and a virtual write address in which the transmission data is to be written within a virtual memory associated with the transmission reception process; means for generating a packet in the first cluster containing the transmission data, a transmission range identification code for identifying the selected real communication range ( 13 ) and an offset address for indicating the difference between a base address of the selected real communication area ( 13 ), virtual communication area ( 11 ) and the selected virtual write address; means for sending the packet from the first cluster to the second cluster through the network ( 4 ; 509 ); means for reading a base address of the selected real communication area ( 13 ) in the second cluster using the transmission area identification code included in the received packet; means for generating a real address within the real communication area in the second cluster by adding the offset address contained in the received packet to the read base address; and means for writing the transmitted data to the second cluster at a location in the main memory corresponding to the generated real address. The system of claim 3, further comprising: means ( 42 . 120 ) for receiving second transmission data sent from a second transmission origination process executed by another cluster and writing the received second transmission data into a second real communication area associated with the second transmission reception process performed by each cluster ( 1 ). The system of claim 3 or 4, further comprising: a translation device ( 530 ) associated with each first process as executed by each cluster and responsive to a data transfer command issued by each first process, for issuing a first process identification code predetermined by the instruction for identifying a second process within the system System, which is a transmission data transmission destination, translate into a set of a cluster identifier code associated with another cluster in which the second process exists, and a within cluster process identifier code associated with the second process, the second Identify process in the second cluster; and a facility ( 507 ) to the data transfer command for transmitting the cluster identifier code and the intra-cluster process identifier code to the network ( 4 ; 509 ), as obtained from the translation device together with the transmission data ( 17 ).