DE4202623A1 - Sensing path arrangement for test circuits, e.g. for testing RAM(s) - has two groups of registers in series with controller managing priority of shift operation of first gp. - Google Patents

Abstract

A sensing path arrangement contains a first sensing register group (10) with a number of first sensing registers connected in series, a second group (20, 30) connected in series with the output of the first group and with registers in series and a controller (60). The controller regulates the first and second groups of registers so that the second group's shift operation is interrupted and the first group's shift operation is carried out. It applies a shift clock signal to the first group and applies a clock signal to the second group depending on a defined control signal. ADVANTAGE - wiring of arrangement is simplified and testing efficiency increased.

Description

The invention relates to a scanning path device and a Integrated semiconductor circuit device with this. The In particular, the invention relates to an improvement of an additional one Test circuit for executing a test.

A scan path is used as an additional test circuit for execution testing a semiconductor integrated circuit device such as e.g. B. a RAM (random access memory) used. In the following Description will be a general scan path, a scan path with  Bypass function and a scan path that leads to total random sequences Address setting used, first, second and third Example of the prior art described.

(1) First example of the prior art (a) Establish a general scan path

Fig. 43 is a block diagram showing the structure of an additional test circuit (scanning path) for a RAM.

A plurality of scan registers for addresses (hereinafter referred to as AD scan registers) 10 a, a plurality of scan registers for input data (hereinafter referred to as DI scan registers) 20 a, and a plurality of scan registers for output data (hereinafter referred to as DO scan registers) 30 A are anodized around a RAM 2 . The RAM 2 and the scanning registers 10 a, 20 a, 30 a are formed together with other (not shown) logic circuits on the same semiconductor chip.

The scanning registers 10 a, 20 a and 30 a connect the other logic circuits with the RAM 2 on the semiconductor chip during normal operation and separate the other logic circuits when testing the RAM 2 from the RAM 2 on the semiconductor chip.

The scan registers 10 a, 20 a and 30 a are connected in series between a serial input port SIC and a serial output port SOC in order to implement a scan path (a type of shift register). When testing the RAM 2 , the shift function of the scan path causes an address signal and data such. B. test data, via address input connections A 0 to Am- 1 and data input connections DI 1 -DIn. The test result of the RAM 2 is entered via the data output connections DO 1 -DOn of the RAM 2 to the DO scan register 30 a of the scan path.

(b) AD scan register

Fig. 44 shows the circuit structure of the AD scan register 10 a. The AD scanning register 10 a has N-channel MOS transistors N 51 -N 53 and inverters G 51 -G 54 . Inverters G 51 and G 52 and inverters G 53 and G 54 each implement a ratio type latch circuit. The driving capacity of the inverters G 52 and G 54 is lower than that of the inverters G 51 and G 53 .

The AD scanning register 10 a has a serial input terminal SI, a serial output terminal SO, a parallel input terminal PI 1 and a parallel output terminal PO 1 . The AD scanning register 10 a also has a parallel clock signal connection pck 1 for receiving a parallel clock signal PCK 1 , a serial clock signal connection sck 1 a for receiving a first serial shift clock signal SCK 1 a for an address and a serial clock signal connection sck 2 a for receiving a second serial shift clock signal SCK 2 a for an address.

During normal operation of the RAM 2 , the potential of the serial clock signal connection sck 1 a is set to an L level (logic low), and the potential of the parallel clock signal connection pck 1 is set to an H level (logic high). This causes an address signal to be transmitted from the parallel input terminal PI 1 to the parallel output terminal PO 1 . The potential of the serial clock signal connection sck 2 a can be set to either the H or L level.

During test operation of the RAM 2 , the potential of the parallel clock signal connection pck 1 is set to an L level. This separates the RAM 2 from the other logic circuits. The shift operation is carried out by a first phase clock signal SCK 1 A and a second phase clock signal SCK 2 A, which are supplied to the shift clock signal input connections sck 1 a and sck 2 a. This sets a test address in the AD scan register 10 a.

(c) DI scan register

Fig. 45 shows a circuit structure for the DI scan register 20 a. The structure of the DI scan register 20 a is similar to the structure of the AD scan register 10 a of FIG. 44, the same reference numerals designating the same or corresponding components. The DI sampling register 20 a has a serial clock signal connection sck 1 for receiving a first serial shift clock signal SCK 1 and a serial clock signal connection sck 2 for receiving a second serial shift clock signal SCK 2 .

During normal operation of the RAM 2 , the potential of the serial clock signal connection sck 1 is set to an L level, and the potential of the parallel clock signal connection pck 1 is set to an H level. This transfers data from the parallel input port PI 1 to the parallel output port PO 1 . At this time, the potential of the serial clock signal connection sck 2 can be set to either the H or L level.

During test operation of the RAM 2 , the potential of the parallel clock signal connection pck 1 is set to an L level. This separates the RAM 2 from the other logic circuits. The shift operation is carried out by a first and second phase clock signal SCK 1 and SCK 2 , which are supplied to the serial clock signal connections sck 1 and sck 2 . Test input data are thus set in the DI scanning register 20 a.

(d) DO scan register

Fig. 46 shows a circuit structure for the DO scan register 30 a. In DO scan register 30 a, identical reference numerals denote components which correspond to those in AD scan register 10 a and DI scan register 20 a. The DO sampling register 30 a has N-channel MOS transistors N 61 -N 64 , inverter G 61 -G 64 , an exclusive NOR circuit G 65 and a NOR circuit G 66 . The DO sampling register 30 a has a test clock signal connection tck * for receiving an inverted test clock signal TCK * (hereinafter referred to as an inverted signal or an inverted connection).

During normal operation of the RAM 2 , the potential of the serial clock signal connection sck 1 is set to an L level, and the potentials of the parallel clock signal connection pck 1 and the serial clock signal connection sck 2 are set to an H level. This causes the output data of the RAM 2 to be transferred from the parallel input terminal PI to the parallel output terminal PO. At this time, the potential of the test clock signal terminal tck * can be set to either the H or L level.

During test operation of RAM 2 , the potential of the parallel clock signal connection pck 1 is set to an L level, and the potential of the inverted test clock signal connection tck * is set to an H level. This separates the RAM 2 from the other logic circuits. The shift operation is carried out by the first phase clock signal SCK 1 and the second phase clock signal SCK 2 , which are supplied to the serial clock signal connections sck 1 and sck 2, respectively.

(e) Scan path operation

FIG. 47 is a signal diagram showing the shift operation of the scan path of FIG. 43. Each of the sampling registers 10 a, 20 a and 30 a is supplied with a first phase clock signal via the serial clock signal connections sck 1 and sck 1 a and a second phase clock signal via the serial clock signal connections sck 2 and sck 2 a.

The data of the serial input connection of the respective Sampling registers are sent to the first phase clock signal Node A entered in the scan register. The data of node A are inverted and the second phase clock signal to the Transfer node B. The data of node B are inverted and supplied to the serial output terminal SO.  

This shifts operation for one bit from the serial Input port SI to serial output port SO executed. The shifting operation is thus effected by clock signals of two phases executed to set test data and the test result read out.

Fig. 48 shows a signal diagram showing the operation of the scan path of Fig. 43 during testing. The scanning registers 20 a and 30 a are supplied with serial shift clock signals SCK 1 and SCK 2 via the serial clock signal connections sck 1 and sck 2 . Various serial shift clock signals SCK 1 A and SCK 2 A are supplied to the AD scanning register 10 a via the serial clock signal connections sck 1 a and ack 2 a. This will update the test address.

At the parallel output terminal PO of the DO-scan register 30 a a read data expectation value is set. The data read out from the RAM 2 to the parallel input terminal PI are compared by the exclusive NOR circuit G 65 with the readout expected data. An inverted test clock signal TCK * is supplied to the inverted test clock signal terminal tck * each time data is read out. If an error value (incorrect data) is read out, a clock signal PCK 2 is generated at the output node of the NOR circuit G 66 , which is generated by inversion of the inverted test clock signal TCK *. The data of the parallel input connection PI is thus entered at node A (PO 2 ).

A value that is identical to that of the parallel output connection PO has previously been set at the node PO 2 by a pushing operation. Therefore, the value of node PO 2 is inverted when an error value is read out.

The above-described operation is performed for a plurality of addresses, followed by the shift operation shown in Fig. 47 to read the test result from the serial output terminal SO. Depending on whether the value held in the latch circuit is inverted or not, it can be determined whether a value different from the readout expected value is supplied to the parallel input terminal PI.

(f) Difficulties in the first example of the prior art

In the additional test circuit (scan path) shown in Fig. 43, the DI scan registers and the DO scan registers must all be connected to the respective data input terminals and the respective data output terminals of the RAM. This increases the complexity of the additional test circuit.

(2) Second example of the prior art

Fig. 49 is a block diagram showing the structure of a semiconductor integrated circuit device having a scan path with transfer function.

A plurality of circuit blocks 2 a is formed on a semiconductor chip 1 a. Each circuit block 2 a has z. B. a RAM, ROM (read-only memory) or a multiplier. A test circuit 3 a is formed around each circuit block 2 a. The test circuit 3 a has a plurality of scanning registers 31 , which are connected in series, and a selection device 32 .

The selector 32 is dependent on a mode control signal MD to selectively output either the input signal to the first stage scan register 31 or the output signal from the last stage scan register 31 . When the selector 32 is set to the "1" side, the selector 32 selects the input signal to the first stage scan register 32 . This is known as a bypass condition. When the selector 32 is set to the "0" side, the selector 32 selects the output of the scan register 32 of the last stage. This is called a non-bypass condition.

Between the serial input terminal SIC and the serial output port SOC a plurality of test circuits (additional test circuits) 3a is a switched according to the plurality of circuit blocks 2 in series, to implement on the semiconductor chip 1 a a scan.

Generally, a selector 32 corresponding to a circuit block 2 a, which is not subjected to a test, is placed in the bypass state, and a selector 32 corresponding to a circuit block 2 a to be tested is placed in the non-bypass state. Therefore, the test data only pass through the scan register 31 corresponding to the circuit block 2 a to be tested. The number of shift operations is correspondingly reduced in order to shorten the test time compared to the case in which the test data passes through all shift registers 31 .

Fig. 50 shows the block diagram of an example of the structure of a test circuit in which the RAM 2 represents the circuit block.

The test circuit 3 a has a Adreßabtastregistergruppe (hereinafter referred to as AD-Abtastregistergruppe) 10, an input data Abtastregistergruppe (hereafter DI Abtastregistergruppe hereinafter) 20, a Ausgabedaten- Abtastregistergruppe (hereafter DO-Abtastregistergruppe hereinafter) 30, and a selection means 50 on. The AD scan register group 10 , the DI scan register group 20 , the DO scan register group 30 and the selector 50 are connected in series between the serial input port SI and the serial output port SO to implement a scan path. The AD scan register group 10 , the DI scan register group 20 and the DO scan register group 30 are supplied with a common shift clock signal SCK and the selector 50 with a mode control signal MD. The selector 50 shown in Fig. 50 corresponds to the selection means 32 shown in Fig. 49.

The shift clock signal SCK is a one-phase shift clock signal or a two-phase shift clock signal.

When a RAM 2 of Fig. 50 is to be tested, the test circuits corresponding to the other circuit blocks are set in the bypass state. This state is equivalent to the state in which the serial input terminal SI and the serial output terminal SO of the test circuit 3 a corresponding to this RAM 2 are connected to the serial input terminal SIC and the serial output terminal SOC of the semiconductor chip 1 a shown in FIG. 49. Therefore, the test time depends on the shift operations of the test circuit shown in Fig. 50 3a decreases, and the shift operation of the test circuits of the other circuit blocks need not be considered.

The test is based on the shift operation of the scan path for the testing circuit block executed. Therefore the test time increases proportional to the number of shift operations. This problem occurs even when the circuit block has RAM represents. The following is a March test that describes one typical test algorithm for a RAM represents the problem to explain the increase in test time.

(3) A typical March test

The following is the processing procedure of the test algorithm a typical March test.

(Step 1) "0" is written in all addresses.

(Step 2) For all addresses, "1" after reading "0" written while the address from 0 to the last address is raised successively.

(Step 3) "0" for all addresses after reading out "1" written while the address from the last address down to 0 is successively decreased.  

(Step 4) "1" is written in all addresses.

(Step 5) "0" for all addresses after reading out "1" written while the address from 0 to the last address is raised successively.

(Step 6) For all addresses, "1" after reading out "0" written while the address from the last address down to 0 is successively decreased.

Consider a case where the RAM 2 of Fig. 51 is to be checked. The address signals A (0) to A (n-1), a chip activation signal CE, a write activation signal WE and data DI (0) to DI (m-1) are supplied to the RAM 2 , and data DO (0) to DO (m-1) output from RAM 2 .

The write operation shown in Fig. 52 is carried out in steps 1 and 4. The read / write operation shown in Fig. 53 is carried out for steps 2, 3, 5 and 6. In the write operation of Fig. 52 data DI (i) to be written in response to an active low write enable signal WE. In the read / write operation shown in FIG. 53, DO (i) read out as a function of the active low chip activation signal CE is compared by an external tester at a tester scanning time with a predetermined expected data value, data DI (i) as a function of an active low write activation signal WE to be written. Here, i represents a value 0 to m-1. In the read / write operation shown in Fig. 53, the read operation and the write operation are carried out within the same test cycle.

A RAM with the organization 1024 words _* 8 bits is considered as an example. In steps 1 and 4, the write operation of Fig. 52 is repeated 1024 times each. At steps 2, 3, 5 and 6, the read / write operation of Fig. 53 is performed 1024 times each. The March test is therefore carried out in a total of 6144 test cycles.

The March test for a 2 ⁿ word RAM is implemented by 6 _* 2 ⁿ test cycles. This estimate is applicable in the event that all different signals from an external source, such as. B. the RAM 2 in Fig. 51, can be directly controlled and monitored.

When this March test is performed using the scan path with a bypass function as shown in Figs. 49 and 50, each RAM test is performed by the normal scan test. Because the read operation and the write operation of the RAM 2 can be performed within the test cycle of the shift operation in the scan test, the number of test cycles in the shift operation is considered in the following description.

As shown in Fig. 50, the RAM 2 with an organization of 1024 words _* 8 bits has an AD scan register group 10 with ten scan registers, a DI scan register group 20 with 8 scan registers and a DO scan register group 30 with 8 scan registers.

In steps 1 and 4, it is necessary to set an address signal for each address and a write value by means of the shift operation. Eight shift operations are required to set write data in the DI scan register group 20 , and ten shift operations are required to set an address signal in the AD scan register group 10 . In the following description, it is assumed that a shift operation is carried out by a test cycle. In steps 1 and 4, this test cycle is repeated 1024 times, which leads to (10 + 8) _* 1024 = 18 432 test cycles.

In steps 2, 3, 5 and 6, it is necessary to set the write data and the address signal by a shift operation for each address and to read out the read data by a shift operation for each address. Therefore, eight shift operations are required to set the write data in the DI scan register group 20 , and ten shift operations are required to set the address signal in the AD scan register group 10 . Eight shift operations are also required to feed the readout data to the DO scan register group 30 . In steps 2, 3, 5 and 6, the test cycle is repeated 1024 times, which leads to (10 + 8 + 8) _* 1024 = 26 624 test cycles.

To run the March test, a total of (18 432 _* 2+ 26 624 _* 4) = 143 360 test cycles are necessary.

The number of test cycles required for a scan test is approximately 23 times the number of test cycles (6144 Test cycles), which are necessary for a typical March test. The means an increase in test time (approximately 23 times at this example) cannot be avoided even if a Bypass scan path is used if normal Sampling test is performed for each RAM test.

(4) Third example of the prior art

In the following a test circuit is described, the total Random sequences used for the address setting.

A total random sequence is a certain bit train. By Moving the bit train into a scan path can change the test address of RAM can be set efficiently. "0000111101011001000" is an example of a total fourth order random sequence.

When this bit train is applied to a 4-bit shift register, the data held in the shift register varies for each shift operation. With this, all possible 16 states can be set, although the order is statistical. Provided that the value held in the shift register represents the test address of the RAM, all addresses from address 0 to address 15 can be set as shown in Fig. 38, and even in a statistical order.

It is believed that the total random sequence of Fig. 54 is equal to "000011110101100100", and a bit in this sequence is shifted at once to the shift register having 4 bits. If the first "0000" is inserted, the address is therefore 0. By successively inserting the remaining "111101011001000" the address changes accordingly as address 8, address 12, address 14,. . ., Address 1. The number of test cycles required for this is (4-1) + 2⁴ = 19 test cycles.

Generally, a total random order of order n is used to test a RAM with n address lines. In this case, a total of (n-1) +2 ⁿ test cycles are required to set all test addresses. It is not possible to start the check within the first (n-1) shift operations because the address is not determined. The read and write operation of the RAM can be performed during the subsequent 2 ⁿ shift operations after the address has been set.

(5) Random March test

The following is the processing procedure of a random March test using as an example of the test algorithm described a total random sequence for the address setting.

(Step 1) It gets an address by inserting the total Random sequence set, and "0" is written in all addresses.

(Step 2) It gets an address by inserting the total Random sequence is set, and for all addresses "1" after the Read out of "0" written.

(Step 3) It gets an address by inserting the total Random sequence is set, and for all addresses "0" after the Read out of "1" written.

(Step 4) It gets an address by inserting the total Random sequence set, and "1" is written in all addresses.  

(Step 5) It gets an address by inserting the total Random sequence is set, and for all addresses "0" after the Read out of "1" written.

(Step 6) It gets an address by inserting the total Random sequence is set, and for all addresses "1" after the Read out of "0" written.

For each cycle of steps 1-6 different totals can be made Random sequences can be used.

In Figs. 55 and 56, a test circuit is shown that uses this random March test. In the example of FIG. 55, an AD scan register group 10 , a DI scan register group 20 , a DO scan register group 30 and a comparison circuit 80 are formed corresponding to a RAM 2 . In the example of FIG. 56, a plurality of AD scan register groups 10 , a plurality of DI scan register groups 20 , a plurality of DO scan register groups 30 and a plurality of comparison circuits 80 corresponding to the plurality of RAMs 2 are formed.

The test cycle necessary for the random March test is described below with reference to FIG. 55.

By inserting a total random sequence into the AD scan register group 10 , the address signal can be updated by a shift operation. It is therefore not necessary to insert all bits of an address signal for an address, as was the case with the typical March test.

Since the write data and the read data do not change with each step, it is not necessary to divide the scan path, so that the write data is not changed by the shift operation of the total random sequence. Therefore, the AD scan register group 10 is connected between the serial input port SI 1 and the serial output port SO 1 , and the DI scan register group 20 and the DO scan register group 30 are connected in series between the serial input port SI 2 and the serial output port SO 2 , as shown in Fig. 55. The shift clock signal SCKA is supplied to the AD scan register group 10 and the shift clock signal SCKD to the DI scan register group 20 and the DO scan register group 30 .

A comparison circuit 80 is formed in order to eliminate the pushing out of the readout data. The comparison circuit 80 compares the data held by the DO scan register group 30 (the readout awaiting data) and the data read out by the RAM 2 to output a PASS / FAIL signal indicating a match / mismatch. The shift operation of the DO scan register group 30 is not necessary as long as the readout expectation data does not change.

With the random March test, the write data or the readout data do not change during the update of the address in the respective step. This means that the number of shift operations of the DI scan register group 20 and the DO scan register group 30 is quite small compared to the number of shift operations of the AD scan register group 10 .

For example, let us estimate the number of test cycles required to test a 1024 word _* 8 bit RAM. Because the number of words is 2¹⁰ = 1024, n = 10. Therefore, a total random order of 10 is used.

Nine additional shift operations are necessary until the Address is set. The address can then be updated and the test can be carried out by a shift operation.

Because the shift operations are performed within the same test cycle in which the reading mode or the reading / Write operation is performed, the following description carried out on the assumption that in steps 1 and 4 the Shift operation and the write operation and in steps 2, 3, 5  and 6 the shift operation and the read / write operation during run in the same test cycle.

In steps 1 and 4, nine shift operations are required until an address is determined, and then 1024 test cycles are required. The eight shift operations necessary for setting the write data in the DI scan register group 20 can be performed concurrently with the nine shift operations required to determine the address. Therefore, 9 + 1024 = 1033 test cycles are necessary for steps 1 and 4.

In steps 2, 3, 5 and 6, nine shift operations are required to determine an address and then 1024 test cycles. Eight shift operations are required to set a readout expectation data in the DO scan register group and eight shift operations to set a write value in the DI scan register group 20 . The nine shift operations necessary for determining an address can be carried out during the shift operations for setting the readout expectation data and the write data. Therefore steps 16, 3, 5 and 6 each require 16 + 1024 = 1040 test cycles.

A total of (1033 _* 2 + 1040 _* 4) = 6226 test cycles are required for a random March test.

The number of test cycles required for a random March test shows an increase of only 1.3% compared to the number of Test cycles that are required for a typical March test (6144 test cycles). This is an advantage to the increase in test time to suppress.

(6) Indication of known publications

An example of a conventional scan path is in JP 63- 2 22 399 described, which corresponds to US 49 26 424.  

The test circuits shown in FIGS . 55 and 56 that use total random sequences for address setting are described in "TESTING OF EMBEDDED RAM USING EXHAUSTIVE RANDOM SEQUENCES", 1987 International Conference Paper 4.2, pp. 105-110, H. Maeno et al .

In the test circuits shown in Figs. 55 and 56, the scan path is divided into two rows, namely an address scan path and a data scan path. This requires the formation of two serial input / output connections for each test circuit. This leads to the problem that the wiring of the serial slide path connected to these terminals becomes complicated.

The object of the invention is to wire a Simplify scan path setup and test efficiency too improve. In addition, the mode setting should be without complication the circuit structure in a scan path device with a Bypass feature will be enabled to test efficiency improve. Furthermore, an integrated Semiconductor circuit device with a memory device Test time can be reduced without complicating the wiring. The object of the invention is also to reduce complexity an additional test circuit. Furthermore, the complexity of a scan register can be reduced. In addition, a Sampling registers are created that provide data input / output enables.

The scanning path device according to the invention has a first one Scan register group with a plurality of scan registers, which in Series are connected, and a second scan register group with a plurality of scan registers connected to the output of the first Scan register group are connected in series. The scan path also has a circuit for controlling the first and second Scan register groups so that the second scan register group interrupts its shift operation and the first scan register group carries out their push operation.  

In the scan path device, the first scan register group carry out their push operation while the second Scan register group suppresses its shift operation. Therefore can Data is sequentially input to the first scan register group without changing the data of the scan register group. The improves test efficiency. In addition, the wiring of the serial slide path simplified because the first and second Scan register groups can be implemented with a path.

The scan path device in accordance with another Aspect of the present invention has an input port for Receive serial data, a first scan register group with one A plurality of scan registers in series with the input port are connected, a second scan register group with a plurality of scan registers that match the output of the first Scan register group are connected in series, one Output terminal, a selection circuit and a first Control circuit on. The selection circuit either selects the Data of the input connection or that of the second Sample register group output data to the selected Feed data to the output port. The first control circuit controls the first and second shift register groups so that the second shift register group sets its shift operation and the first scan register group performs its shift operation when from Selection circuit selected the data of the input terminal have been.

The scan path device enables the setting of a Bypass state in which the data of the input port successively fed to the first scan register group and are sequentially discharged from the output port, and the Setting a non-bypass condition in which the data of the Input port successively the first scan register group fed and data from the second scan register group are successively output from the output terminal. If the Scan path device has been placed in the bypass state,  can sequentially transfer data into the first scan register group are entered without the data of the second scan register group to change. This improves the test efficiency.

One scan path device in accordance with another Aspect of the invention further includes a second control circuit on. The second control circuit receives data from one of the Scan registers in the first and second scan register groups are included to make the selection device dependent on these Control data.

In the scanning path device, the selection device corresponding to those in the first or second scan register group entered data controlled so that the wiring for a Control signal is simplified.

An integrated semiconductor circuit device according to one another aspect of the present invention features a Storage device and a scan path. The scan path points an input port for receiving serial data, a first one Scan register group, a second scan register group, a Selector and a first control circuit. The first Scan register group has a plurality of scan registers, which are connected in series to the successively from Input port fed data in parallel to the Output memory device as an address signal. The second Scan register group has a plurality of scan registers, which are connected in series to one after the other from the first Sample register group applied data in parallel to the Output storage device, or that of the storage device to receive data output in parallel. The selector selects either the data from the input port or that from the second scan register group output data to them as submit selected data. The first control circuit controls the first and second scan register groups so that the second Scan register group stops shifting and the first Scan register group performs its shift operation when from the  Selector selected the data of the input port have been.

The integrated semiconductor circuit device enables selective setting of a bypass condition or a non- Bypass state for the scan path. If the scan path is in the Bypass state has been set, data can be sequentially changed first scan register group are supplied without the in the second sample register group held data to modify. Therefore the address signal can be updated in a simple manner, and the Test time is reduced.

Another integrated semiconductor memory device can furthermore have a second control circuit. The second Control circuitry receives data from one of the scan registers in the first or second scan register group to control the selection device in dependence on this data.

In the integrated semiconductor circuit device, the Selector controlled according to the data from the first and second scan register group are supplied so that the Wiring for the control signals is simplified.

The semiconductor integrated circuit device can also be a Holding circuit and a second control circuit. The Hold circuit is in series with the first and second Scan register group formed to set the data for mode setting to keep. The second control circuit controls the Selector depending on the mode setting data be held in the hold circuit.

In the integrated semiconductor circuit device, the Selection device controlled according to the mode setting data, which are held in the holding device so that the wiring for the control signals is simplified.  

An additional test circuit in accordance with one Another aspect of the present invention includes a plurality of Scan registers that are connected in series. Each Scan register has a serial input port, a first and second parallel input port, first and second Hold circuit, a first, second, third and fourth Transmission circuit, a first and a second parallel Output port, a serial output port, a Comparison circuit and an activation circuit.

Each of the first and second hold circuits holds one fed value and outputs it. The first transmission circuit transmits the data of the first parallel input connection to the first hold circuit. The second transmission circuit transfers the data of the serial input connector to the first one Hold circuit. The third transmission circuit transmits the Data of the second parallel input connection to the second Hold circuit. The fourth transmission circuit transmits the Data from the first hold circuit to the second hold circuit. The first parallel output port receives the data from the first Hold circuit. The second parallel output port receives the Data from the second hold circuit. The serial output connector receives the data from the second hold circuit.

The comparison circuit compares the data of the second or first parallel input connector with the data from the first or second hold circuit are output. The Activation circuit activates / deactivates the third or first transmission circuit according to the comparison result of the comparison circuit.

The serial input connection of the respective scan register is with the serial output port of the scan register in the previous one Stage connected.

In the additional test circuit, one of the first and second Holding circuits contained in the respective scan register,  used for entering parallel data, and the other Hold circuit is used for the output of the parallel data. It is therefore possible to input / output data using a Scan registers to perform the complexity of the additional Reduce test circuitry.

Further features and advantages of the invention result from the description of exemplary embodiments with reference to the figures. From shows the figures

Fig. 1 is a block diagram of the structure of the main components according to a first embodiment of the invention;

Fig. 2 is a block diagram of the overall structure of the first embodiment of the invention;

Fig. 3 is a graph showing the relationship between a test circuit and a RAM;

Fig. 4 is a block diagram of an example of the structure of a test circuit;

Fig. 5 is a block diagram of another example of the structure of a test circuit;

Fig. 6 is a block diagram of the structure of an AD scan register group;

Fig. 7 is a block diagram of the structure of a scan register;

Fig. 8 is a block diagram of an example of the structure of a CE scan register;

Fig. 9 is a block diagram of another example of the structure of a CE scan register;

Fig. 10 is a block diagram of the structure of a WE scan register;

Fig. 11 is a block diagram of the structure of a DIO scan register group;

Fig. 12 is a block diagram of an example of the structure of a DIO scan register;

Fig. 13 is a block diagram of another example of the structure of a DIO scan register;

Fig. 14 is a block diagram of the structure of a DMY scan register;

Figure 15 is a diagram showing the structure of a latch circuit.

FIG. 16 is a diagram showing the structure of a resettable latch circuit;

Fig. 17 is a circuit diagram showing the structure of a 2-input latch circuit;

FIG. 18 is a flowchart for explaining the initialization operation;

Fig. 19 is a waveform diagram of a reset cycle;

FIG. 20 is a signal diagram of a scan-in cycle;

Fig. 21 is a signal diagram of a mode setting cycle;

FIG. 22 is a flowchart for explaining a write-all operation;

FIG. 23 is a signal diagram of a write cycle;

FIG. 24 is a flowchart for explaining the read-write All-operation;

FIG. 25 is a signal diagram of a read / write cycle;

Fig. 26 is a signal diagram of a setting cycle;

Fig. 27 is a signal diagram of a scan-out cycle;

Fig. 28 is a flow chart for explaining a random March test;

FIG. 29 is a flow chart for explaining a random March-test;

FIG. 30 is a block diagram of another application of the present invention;

Fig. 31 is a block diagram of the structure of the main components of a second embodiment of the present invention;

Fig. 32 is a block diagram of the structure of the main components of a third embodiment of the present invention;

Fig. 33 is a block diagram of a fourth embodiment of the present invention;

Fig. 34 is a circuit diagram showing an example of the structure of a DIO scan register;

FIG. 35 is a circuit diagram of another example of the structure of DIO-scan register;

Fig. 36 is a circuit diagram of another example of the structure of a DIO scan register;

FIG. 37 is a circuit diagram of another example of the structure of DIO-scan register;

FIG. 38 is a timing chart of the shift operation of an additional test circuit;

FIG. 39 is a timing diagram of the operation of an additional test circuit in the test;

Fig. 40 is a circuit diagram of another example of the structure of DIO-scan register;

Fig. 41 is a circuit diagram of another example of the structure of a DIO scan register;

Fig. 42 is a diagram showing another example of the structures of a comparing circuit and a latch activation circuit;

Fig. 43 is a block diagram of a first example of the prior art;

FIG. 44 is a diagram showing a structure of an AD sample register;

FIG. 45 is a diagram showing a structure for a DIO-scan register;

Fig. 46 is a diagram showing a structure for a DO-scan register;

FIG. 47 is a timing chart of the shift operation corresponding to the first example of the prior art;

48 is a timing chart for illustrating the test mode according to the first example of the prior art.

Fig. 49 is a block diagram of a second example of the prior art;

Fig. 50 is a block diagram of a structure of the test circuit according to the second example of the prior art;

FIG. 51 is a diagram illustrating an example of a RAM;

Fig. 52 is a signal diagram of the write operation;

Fig. 53 is a signal diagram of the read / write operation;

FIG. 54 is a diagram for explaining a total random sequence;

Fig. 55 is a block diagram of a third example of the prior art; and

Fig. 56 is a block diagram of another example of the structure of the third example of the prior art.

(1) Schematic structure and operation

Fig. 1 is a block diagram showing a schematic structure of a test circuit included in a semiconductor integrated circuit device according to a first embodiment of the invention. Fig. 2 is a block diagram showing the overall structure of the semiconductor integrated circuit device.

As shown in Fig. 2, a plurality of RAMs 2, a plurality of test circuits 3 according to the plurality of RAM 2 and a logic circuit 4 are formed on a semiconductor chip 1. Each RAM 2 is connected to the logic circuit 4 via a corresponding test circuit 3 . The plurality of test circuits 3 are connected in series between the serial input terminal SIC and the serial output terminal SOC to implement a scan path.

A reset signal RST, a mode setting signal MDST, a shift clock signal SCK, a scanning signal STB, a test mode signal TM, a test chip activation signal TCE and a test write activation signal TWE are supplied to each test circuit 3 via a test bus TB. In the present embodiment, the shift clock signal SCK is a two-phase clock signal that includes a first phase shift clock signal SCK 1 and a second phase shift clock signal SCK 2 . The shift clock signal SCK can also be a single-phase clock signal.

As shown in Fig. 1, an AD scan register group 10 , a DI scan register group 20 , a DO scan register group 30 , a mode setting scan register 40 and a selector 50 are between the serial input terminal SIB and the serial output terminal SOB of the test circuit 3 in Connected in series to implement the scan path.

The test circuit 3 further includes a gate circuit 60 and a mode control latch 70 . The AD clock register group 10 and an input terminal of the gate circuit 60 are supplied with the shift clock signal SCK. The mode control signal MD output from the mode control latch 70 is supplied to the other input terminal of the gate circuit 60 . The output signal of the gate circuit 60 is applied to the DI scan register group 20 , the DO scan register group 30 and the mode setting scan register 40 .

The selector 50 is placed in a bypass state when the mode control signal MD is "1". At this time, the shift clock signal SCK is not output from the gate circuit 60 . Therefore, the shift operation of the DI scan register group 20 , the DO scan register group 30, and the mode setting scan register 40 can be stopped.

It is therefore possible, when performing the random march test, to insert the total random sequence into the AD scan register group 10 to update an address, the DI scan register group 20 and the DO scan register group 30 still holding the write data and the readout expectation data .

When the mode control signal MD is "0", the selector 50 is placed in a non-bypass state. At this time, in addition to the AD scan register group 10 , the shift clock signal SCK is also supplied to the DI scan register group 20 , the DO scan register group 30, and the mode setting scan register 40 via the gate 60 . Therefore, the scan registers between the serial input port SIB and the serial output port SOB operate as a normal scan path.

The mode setting signal MDST and the reset signal RST are supplied to the mode control latch 70 . The mode control latch 70 holds data from the mode set scan register. The mode control latch 70 outputs the mode control signal MD depending on the mode setting signal MDST, the reset signal RST and the data from the mode setting scan register 40 .

When the reset signal RST is supplied, the mode control signal MD is set to "0". This puts the selector 50 in a non-bypass state. At this time, the shift register groups 10, 20, 30 and 40 can perform shift operations by the shift clock signal. In this case, the scanning registers 10, 20, 30 and 40 of all test circuits 3 on the semiconductor chip of FIG. 2 are connected in series.

A subsequent shift operation sets data "1" or "0" in the mode setting scan register 40 in each test circuit 3 . Then, the supply of the mode setting signal MDST causes the value "1" or "0" held in the mode setting scanning register 40 in each test circuit to be input to the mode control latch 70 , thereby outputting it as the mode control signal MD. Thus, the selector 50 in each test circuit 3 can be selectively put in a bypass or a non-bypass state.

Although the comparison method of the readout data is not shown in FIG. 1, a comparison circuit 80 as shown in FIGS. 39 and 40 can be formed.

If, during the random March test, a total random sequence is inserted into the test circuit 3 in accordance with the RAM 2 to be tested, the write data and the readout expected data should not change. It is therefore necessary to put the test circuit 3 of the RAM 2 under test in a bypass state. In addition, it is necessary to put the test circuits 30 in a bypass state corresponding to the other circuit blocks to reduce the test time. Therefore, all circuit blocks are set to bypass.

This state is equivalent to a case in which a total random sequence applied by the serial input connection SIC of the semiconductor chip 1 is jointly input into all test circuits 3 . Therefore, when the number of words is the same, the total random sequence can be set as an address for all of the plurality of RAMs 2 at the same time. This means that it is possible to test a plurality of RAMs 2 at the same time.

(2) Random March test

The following is the processing procedure of a random March test using a total random sequence for the Address setting described.

(Step 1) It gets an address by inserting the total Random sequence set, and "0" is written in all addresses.

(Step 2) It gets an address by inserting the total Random sequence is set, and for each address "1" after the Read out of "0" written.  

(Step 3) It gets an address by inserting the total Random sequence is set, and for all addresses "0" after the Read out of "1" written.

(Step 4) It gets an address by inserting the total Random sequence set, and "1" is written in all addresses.

(Step 5) It gets an address by inserting the total Random sequence is set, and for all addresses "0" after the Read out of "1" written.

(Step 6) It gets an address by inserting the total Random sequence is set, and for all addresses "1" after the Read out of "0" written.

In the following, a test cycle is estimated in the event that a random March test is carried out using the test circuit 3 of FIG. 1.

A 1024 word _* 8 bit RAM 2 is used as an example. Since the number of words is 2¹⁰ = 1024, n = 10. Therefore, a total random order of 10 is used. For each step of the random March test, nine additional shift operations are necessary to determine an address. The test can then be carried out by updating with each individual shift operation.

The shift operation can be carried out within the same test cycle as the write operation or the read / write operation of the RAM 2 . Therefore, it is assumed that in steps 1 and 4, the shift operation and the write operation are carried out within the same test cycle, and in the other steps the shift operation and the read / write operation are carried out within the same test cycle.

In steps 1 and 4, eight shift operations are necessary to set a write value in the DI scan register group 20 . Nine shift operations are required to determine an address, and shift operations and write operations are required for each of the 1024 addresses. Therefore, 8 + 9 + 1024 = 1041 test cycles are required for each of steps 1 and 4.

In steps 2, 3, 5 and 6, eight shift operations are necessary to set a readout expected value in the DO scan register group 30 , and eight shift operations are necessary to set a write value in the DI scan register group 20 . In addition, nine shift operations are required to determine an address, and shift and write operations are required for each of the 1024 addresses. Therefore, 16 + 9 + 1024 = 1049 test cycles are required for each of steps 2, 3, 5 and 6.

The random March test (1041 _* 2 + 1049 _* 4) = 6278 test cycles.

(3) Special effects

The number of for the random March test corresponding to the necessary test cycles in this embodiment is only 2.2% larger than that of the test cycles (6144 test cycles) required for one general March test are required. That's enough effective to suppress the increase in test time.

Because the shift clock signal SCK in the present embodiment is supplied to the DI scan register group 20 and the DO scan register group 30 via the gate circuit 60, no special shift clock signals are necessary for these scan register groups 20 and 30 . Therefore, the number of shift clock signal terminals is not increased, thereby reducing the complexity of the wiring.

In the present embodiment, it is not necessary to apply an independent mode control signal MD to all test circuits 3 , and a common mode setting signal MDST and a common reset signal RST can be supplied for all test circuits 3 . This further reduces the complexity of the wiring.

(4) Detailed structure of each component (a) Test circuit 3

The relationship between the test circuit 3 and the RAM 2 is shown in FIG. 3. The detailed structure of the test circuit 3 is shown in FIG. 4.

As shown in Fig. 3, the test circuit 3 address signals AX (n-1) to AX (0), a chip activation signal CEX, a write activation signal WEX and write data DIX (m-1) to DIX (0) from the logic circuit 4 (see Fig. 2) supplied. The test circuit 3 outputs readout data DOX (m-1) to DOX (0) to the logic circuit 4 . The test circuit 3 outputs address signals A (n-1) to A (0), a chip activation signal CE, a write activation signal WE and write data DI (m-1) to DI (0) to the RAM 2 . The test circuit are supplied from the RAM 2 read data DO (m-1) to DO (0).

As shown in Fig. 4, the test circuit 3 has an AD scan register group 100 , a chip activation scan register 200 (hereinafter referred to as a CE scan register), a write activation scan register 300 (hereinafter referred to as a WE scan register), data input - / - Output scan register group 400 (hereinafter referred to as DIO scan register group), a blind scan register 500 (hereinafter referred to as DMY scan register), a resettable latch circuit 600 and a multiplexer 700 . The test circuit 3 also has inverter circuits G 1 and G 2 , 2-input AND circuits G 3 -G 5 and a 3-input AND circuit G 6 .

The AD scan register group 100 corresponds to the AD scan register group 10 of FIG. 1 and the DIO scan register group 400 corresponds to the DI scan register group 20 and the DO scan register group 30 of FIG. 1. The DMY scan register 500 corresponds to the mode setting scan register 40 of FIG . 1 and the multiplexer of the selector 50. The resettable latch circuit 600 corresponds to the mode control latch 70 of FIG. 1.

Fig. 5 shows another example of the structure of the test circuit 3. The test circuit 3 shown in FIG. 5 differs from that shown in FIG. 4 in the following points. DMY 500 is not formed and an output signal from one of the plurality of scan registers in the AD scan register group 100 is supplied to the resettable latch circuit 600 .

(b) AD scan register group 100

Fig. 6 shows a structure of the AD-Abtastregistergruppe 100th The AD scan register group 100 has n scan registers 110 (hereinafter referred to as AD scan registers). These AD scan registers 110 are connected in series between the serial input port SIA and the serial output port SOA to implement a short scan path (an n-bit scan path). The serial output port SOR of the respective AD scan register 110 is connected to the serial input port SIR of the AD scan register 110 of the subsequent stage.

During testing, the test address of RAM 2 is set by a shift operation in AD scan register group 100 .

(c) AD scan register 110

Fig. 7 shows a detailed structure of the AD-scan register 110th The AD sample register 110 has a latch circuit L 1 and a 2-input latch circuit L 2 .

The latch circuit L 1 works as follows. When the shift clock signal SCK 2 applied to the activation terminal EN reaches an activation state, data is input from the input terminal D to be held therein, whereby this data is output from the output terminal Q.

The 2-input latch circuit L 2 operates as follows. When the chip activation signal EN 1 supplied to the first activation terminal EN 1 reaches an activation state, data is input from the first input terminal D 1 to be held therein, whereby this data is output from the output terminal Q. When the shift clock signal SCK 1 applied to the second activation terminal EN 2 reaches an activation state, data is input from the second input terminal D 2 to be stored therein, whereby this data is output from the output terminal Q. The simultaneous supply of a signal in the activation state to the first activation connection EN 1 and the second activation connection EN 2 is prevented.

The address signal AX (i) from the logic circuit 4 (see FIG. 2) is supplied to the input terminal axi of the AD scan register 110 . When the chip activation signal CEA reaches an activation state, this address signal AX (i) is input to the 2-input latch circuit L 2 and is output from the output terminal ai as the address signal A (i). More specifically, when the chip activation signal CEA is in an activation state, the address signal is transmitted from the input terminal axi to the output terminal ai. In this state, the address connections of the logic circuit 4 and the RAM 2 are logically connected to one another.

When the chip activation signal CEA is in a deactivation state, the address connections of the logic circuit 4 and the RAM 2 are in a non-connected state. At this time, a shift operation can be performed when non-overlapping two-phase shift clock signals SCK 1 and SCK 2 are supplied to the activation terminals EN 2 and EN, respectively. First, the first phase shift clock signal SCK 1 is supplied to the activation terminal EN 2 of the 2-input latch circuit L 2 , and data is input to the 2-input latch circuit L 2 at the serial input terminal SIR. Since the output terminal Q of the 2-input latch circuit L 2 is connected to the input terminal of the latch circuit L 1 , the second-phase shift clock signal SCK 2 applied to the activation terminal EN is input to the latch circuit L 1 to switch from the serial Output port SOR to be delivered. With this, a shift operation of a bit from the serial input terminal SIR to the serial output terminal SOR is carried out.

(d) CE scan register

Fig. 8 shows a detailed structure of the CE-scan register 200th The CE scan register 200 , like the AD scan register 110, has a latch circuit L 1 and a 2-input latch circuit L 2 , and further comprises inverter circuits G 11 and G 12 and a 2-input NAND circuit G 13 .

The shift operation of the CE scan register 200 is similar to that of the AD scan register 110 . However, shift clock signals SCK 1 M and SCK 2 M are used as shift clock signals, which differ from the shift clock signals of the AD scan register 110 .

In normal operation, the activation signal TCE is set to an L level and the activation signal STBM to an H level. The activation signal CEX is thus transmitted to the output terminal via the inverter circuit G 12 , the 2-input latch circuit L 2 and the NAND circuit G 13 . The activation signal CEX is inverted by the inverter circuit G 12 and further inverted by the NAND circuit G 13 . Therefore, the logic levels of the activation signal CE and the activation signal CEX lead to the same level.

When testing, the activation signal STBM is low Level and the activation signal TCE set to an L level. It is assumed that the activation signals STBM and TCE are both are actively low.  

When the output signal of the output terminal Q of the 2-input latch circuit L 2 is set to an H level by a shift operation, the activation signal CE changes to an L level. This causes RAM 2 to work . When the output signal of the output terminal Q of the 2-input latch circuit L 2 is set to an L level, the activation signal TCE is not transmitted to the output terminal ce, and the activation signal CE maintains the H level. Therefore, the RAM 2 assumes a waiting state.

The operation of the RAM 2 can thus be controlled by the data set in the CE scanning register 200 .

Therefore, when a plurality of RAMs 2 are integrated on the semiconductor chip 1 , as shown in FIG. 2, a desired RAM 2 can be operated selectively for testing when in the SE scan register 200 of each test circuit 3, a desired value by a shift operation is set.

In the CE scan register 200 shown in FIG. 8, the activation signal STBM is output from the output terminal cea as the activation signal CEA to be supplied to the AD scan register 110 .

Fig. 9 shows another example of the structure of the scan register CE 200th A 2-input AND circuit G 14 has been added to the CE scan register 200 . This enables the AD scan register 110 to be used as an address latch in normal operation.

The activation signal STBM is at an H level in normal operation and set to an L level in test mode. Therefore vote in Normal operation, the logic levels of the activation signals CEA and CE match.

In normal operation, the (active low) activation signal CEX is transmitted simultaneously to the output connections CE and cea. When the activation signal CEA goes low, the 2-input latch circuit L 2 of the AD scan register 110 of FIG. 7 reaches a hold state (latches an address signal).

By using the CE scan register 200 shown in FIG. 9, the AD scan register 110 can thus be used as an address latch in normal operation.

The CE scan register 200 shown in FIG. 8 has no such locking function. The CE scan registers 200 of Figures 8 and 9 can be used according to the particular requirement.

(e) WE scan register 300

Fig. 10 shows a detailed structure of the HS-scan register 300th The structure of the WE scan register 300 is similar to that of the CE scan register 200 of FIG. 8.

The shift operation of the WE scan register 300 is similar to that of the AD scan register 110 (see FIG. 7), but as in the case of the CE scan register 200 of FIG. 8, the shift clock signals SCK 1 M and SCK 2 M are used as shift clock signals.

In normal operation, the activation signal TWE is set to an L level and the activation signal STBM to an H level. The activation signal WEX is thus transmitted to the output terminal via the inverter circuit G 12 , the 2-input latch circuit L 2 and the NAND circuit G 13 . The activation signal WEX is inverted by the inverter circuit G 12 and further inverted by the NAND circuit G 13 , so that the logic levels of the activation signals WE and WEX are the same in the end result.

During testing, the activation signal STBM is at an L level set and the activation signal TWE assumes an L level 56161 00070 552 001000280000000200012000285915605000040 0002004202623 00004 56042l. Here it is assumed that the activation signal TWE is active low is.  

When the output signal of the output terminal Q of the 2-input latch circuit L 2 is set to an H level by a shift operation, the activation signal TWE is transmitted to the output terminal we. Therefore, a write operation is carried out when the activation signal CE (see FIG. 3) of the RAM 2 is in an activation state. When the output signal of the output terminal Q of the 2-input latch circuit L 2 is set at an L level, the activation signal TWE is not transmitted to the output terminal WE, and the activation signal WE maintains an H level. Therefore, write operation is not performed by RAM 2 .

The write operation of the RAM 2 can thus be controlled by the data set in the WE scan register 300 .

(f) DIO scan register group 400

Fig. 11 shows a detailed structure of DIO Abtastregistergruppe 400th The DIO scan register group 400 has m DIO scan registers 410 . Write data DIX (m-1) to DIX (0) and readout data DO (m-1) to DO (0) are applied to the DIO scan register 410 . Readout data DOX (m-1) to DOX (0) and write data DI (m-1) to DI (0) are output from the DIO scan register 410 .

The DIO scan registers 410 are connected in series between the serial input port SID and the serial output port SOD to implement a short scan path (a m bit scan path). The serial output port SOR of each DIO scan register 410 is connected to the serial input port SIR of the DIO scan register 410 of the subsequent stage.

(g) DIO scan register 410

Fig. 12 shows the detailed structure of the DIO-scan register 410th The DIO sample register 410 has 2-input latch circuits L 2 a and L 2 b, inverter circuits G 15 and G 16 , 2-input NAND circuits G 17 and G 18 and an exclusive-OR circuit G 19 . Write data DIX (i) from the logic circuit 4 (see Fig. 2) are supplied to the input terminal dix. Data from the RAM 2 (see FIG. 2) or data held in the scan register 410 are supplied to the output terminal dox, which is connected to the logic circuit 4 .

The shift operation is carried out by applying two phases of shift clock signals SCK 1 M and SCK 2 M to the second activation connection EN 2 of the 2-input latch circuits L 2 a and L 2 b. In push mode, it is necessary to set the activation signal STBM and the comparison signal CMP to an L level and the test mode signal TM to an H level. The setting changes the output signal of the NAND circuit G 18 to an H level and the output signal of the NAND circuit G 17 to an L level. Therefore, the potentials of the first activation terminals EN 1 in the 2-input latch circuits L 2 a and L 2 b both reach an L level.

When the shift clock signal SCK 1 M is supplied, data from the serial input terminal SIR is input to the 2-input latch circuit L 2 a of the first stage. This data is inverted by the inverter circuit G 15 and fed to the second input terminal D 2 of the 2-input latch circuit L 2 b of the second stage. Then, when the shift clock signal SCK 2 M is supplied, the inverted data is input to the 2-input latch circuit L 2 b of the second stage. This data is further inverted by the inverter circuit G 16 in order to be supplied to the serial output connection SOR.

The shift operation of a bit is thus carried out by the two-phase shift clock signals SCK 1 M and SCK 2 M. The serial data are inverted twice by the inverter circuits G 15 and G 16 , so that the logic levels of the data of the serial input connection SIR and that of the serial output connection SOR are identical.

In normal operation, the activation signal STBM is set to an H level and the test mode signal TM to an L level. With this setting, the potentials of the first activation connections EN 1 of the 2-input latch circuits L 2 a and L 2 b both reach an H level. At this time, write data DIX (i) applied to the input terminal dix is input to the 2-input latch circuit L 2 a and transferred to the output terminal di. Readout data DO (i) supplied to the input terminal do is input into the 2-input latch circuit L 2 b and transmitted to the output terminal dox.

In this state, the data input / data output terminals of the RAM 2 and the logic circuit 4 are logically connected to each other.

During testing, the test mode signal TM is set to an H level. At this time, the write data and the readout expectation data to be supplied to the RAM 2 are set by a shift operation in the DIO scan register 410 . The write data is set in the 2-input latch circuit L 2 a, and the data inverted by the inverter circuit G 15 becomes the readout expectation data. The data held in the 2-input latch circuits L 2 a and L 2 b by the shift operation have opposite logic levels. Therefore, the readout expectation data is also set in the 2-input latch circuit L 2 b.

The readout data Do (i) output from the RAM 2 are supplied to the input terminal do. These readout data DO (i) are compared by the exclusive OR circuit G 19 with readout expectation data (the output signal of the inverter circuit G 15 ). If the RAM 2 is free of errors, the output signal of the exclusive-OR circuit G 19 reaches an L level. If there is an error in RAM 2 (when reading data from RAM 2 that is different from the readout expectation data), the output signal of the exclusive-OR circuit G 19 assumes an H level.

In this state, the comparison signal CMP changes to an H level. If the RAM 2 is free of errors, the output of the NAND circuit G 18 maintains an H level. If there is an error in RAM 2 , an active low clock signal is generated at the output terminal of NAND circuit G 18 . The output signal of the NAND circuit G 18 is inverted by the NAND circuit G 17 and fed to the first activation terminal EN 1 of the 2-input latch circuit L 2 b. When the RAM 2 is free of errors, the potential of the first activation connection EN 1 is therefore kept at an L level. If an error exists in RAM 2 , an active high clock signal is fed to the first activation connection EN 1 .

When data are read out from the RAM 2 which differ from the readout expected data, the first activation connection EN 1 of the 2-input latch circuit L 2 b is supplied with an active high clock signal. Therefore, the data read out from the RAM 2 (data with a logic level opposite to that of the readout expectation data) is input to the 2-input latch circuit L 2 b. The data held in the 2-input latch circuit L 2 b are thus inverted. If the RAM 2 is error-free, such an inversion of the held data does not occur. This means that the 2-input latch circuit L 2 b holds the test result of the RAM 2 .

Fig. 13 shows another example of a structure of the scan register DIO 410th In the DIO sample register 410 of FIG. 13, the 2-input latch circuit L 2 b represents the latch circuit of the first stage, and the 2-input latch circuit L 2 a is the latch circuit of the second stage . This is the opposite of the DIO scan register 410 of FIG . The 2-input latch circuit L 2 a of the second stage holds write data and readout expectation data, and the 2-input latch circuit L 2 b of the first stage holds the test results in the DIO scan register 410 .

The DIO scan register group 400 shown in FIG. 11 is constructed using the DIO scan register 410 of FIG. 12 or FIG. 13.

The DIO scan register 410 represents an essential structural component of the present invention. The DIO scan register 410 shown in FIGS . 12 and 13 is characterized in that one of the 2-input latch circuits write data and readout expectation data (inverted data of the write data) and the other of the 2-input latch circuits holds the test result.

(h) DMY scan register 500

Fig. 14 shows a detailed structure of the scan register DMY 500th The DMY scan register 500 has latch circuits L 1 a and L 1 b. The DMY scan register 500 is a simple shift register that is operated by two phases of shift clock signals.

When the shift clock signal of the first phase is supplied, data are input to the latch circuit L 1 a at the serial input terminal SIR. Since the output terminal Q of the latch circuit L 1 a is connected to the input terminal D of the latch circuit L 1 b, the supply of the shift clock signal SCK 2 M second phase causes the data to be entered into the latch circuit L 1 b and on serial output port SOR are output.

The shift operation of a bit from the serial Input connection SIR to the serial output connection SOR executed.

(i) Latch circuit L 1

Fig. 15 shows an example of the structure of the latch circuit L is 1 (an example of a CMOS circuit). The latch circuit L 1 has N-channel transistors N 1 -N 3 , P-channel transistors P 1 -P 3 and inverter switching circuit G 20 -G 22 .

When an H-level signal is supplied to the activation terminal EN, the output signal of the inverter circuit G 20 becomes an L-level. The transistors N 3 and P 3 thus switch through and the transistors P 1 and N 1 block. The data supplied to the input terminal D pass through the transistors N 3 and P 3 and are inverted by the inverter circuit G 21 . This value is inverted again by the inverter circuit G 22 and transmitted to the output terminal Q. There is therefore no data inversion between the input terminal D and the output terminal Q.

When an L level signal is supplied to the activation terminal EN, the output of the inverter circuit G 20 assumes an H level. The transistors N 3 and P 3 and the transistors P 1 and N 1 are thus blocked. The source of the transistor P 2 is thus supplied with the supply potential VDD and the source of the transistor N 2 with the ground potential GND. Since the gates and also the drains of the transistors N 2 and P 2 are connected to one another, the transistor pair N 2 and P 2 acts as an inverter circuit.

The inverter circuit with the structure described above implements a memory loop with the inverter circuit G 21 . In other words, the output signal is supplied from one to the input of the other. The data held in this memory loop is supplied to the output terminal Q.

The data held in the memory loop represents the data which are fed to the input terminal D immediately before that Signal at the activation terminal EN changes to an L level.

(j) Resettable latch circuit 600

Fig. 16 shows a detailed structure of the resettable latch circuit 600th The resettable latch circuit 600 differs from the latch circuit L 1 shown in FIG. 15 in that a 2-input NAND circuit G 23 is formed in place of the inverter circuit G 21 .

When a high level signal is supplied to the reset terminal R, the NAND circuit G 23 acts as an inverter circuit. In this state, the resettable latch circuit 600 performs an operation similar to that of the latch circuit L 1 of FIG. 15. More specifically, the data applied to the input terminal D is transmitted to the output terminal Q when an H level signal is supplied to the activation terminal EN. When an L-level signal is supplied to the activation terminal EN, the data is held which is input terminal D immediately before the signal at the activation terminal EN changes to an L-level.

If the reset terminal R is supplied with an L level signal, the output signal of the NAND circuit G 23 changes to an H level, so that an L level signal is supplied to the output terminal Q, which represents an inverted signal of the output signal. In other words, the resettable latch circuit 600 is reset. The reset connection R of the resettable latch circuit 600 is thus actively low.

(k) 2-input latch circuit L 2

Fig. 17 shows an example of a structure of the 2-input latch circuit L 2 (an example of a CMOS circuit). The 2-input latch circuit L 2 has N-channel transistors N 1 -N 5 , P-channel transistors P 1 -P 5 and inverter circuits G 20 , G 21 , G 22 and G 24 .

The first and second activation connections EN 1 and EN 2 are actively high, and it is prevented that both are set to potentials of an H level at the same time.

When an L level signal is applied to both the first activation terminal EN 1 and the second activation terminal EN 2 , the outputs of the inverter circuits G 20 and G 24 both assume an H level. The transistors N 3 , P 3 , N 5 and P 5 and the transistors P 1 , N 1 , P 4 and N 4 are thus blocked. Therefore, the source of the transistor P 2 is supplied with the supply potential VDD and the source of the transistor N 2 with the ground potential GND. Since the gates and drains of the transistors N 2 and P 2 are connected to one another, the transistor pair N 2 , P 2 works as an inverter circuit.

The inverter circuit of the structure described above implements a memory loop with the inverter circuit G 21 . In other words, the output signal of one is fed to the input of the other. The data held in this memory loop is output from the output terminal Q.

The data held in the memory loop represents the data that are supplied to the first or second input connection D 1 or D 2 when one of the signals at the first or second activation connection EN 1 or EN 2 is at an H level.

If a signal with H level is supplied to the first activation connection EN 1 , the output of the inverter circuit G 24 assumes an L level. So that the transistors N 5 and P 5 are turned on and the transistors P 4 and N 4 block. The data supplied to the first input terminal D 1 pass through the transistors N 5 and P 5 and are inverted by the inverter circuit G 21 . This data is inverted again by the inverter circuit G 22 and supplied to the output terminal Q. Therefore, no data inversion occurs between the first input terminal D 1 and the output terminal Q.

If a signal with the H level is fed to the second activation connection EN 2 , the output of the inverter circuit G 20 assumes an L level. So that the transistors N 3 and P 3 are turned on and the transistors P 1 and N 1 block. The data supplied to the second input terminal D 2 pass through the transistors N 3 and P 3 and are inverted by the inverter circuit G 21 . This data is inverted again by the inverter circuit G 22 and supplied to the output terminal Q. Therefore, no data inversion occurs between the second input terminal D 2 and the output terminal Q.

(5) Operation of the test circuit 3 ( Fig. 5)

The operation of the test circuit 3 is explained below: The mode control signal MD is output from the output terminal Q of the resettable latch circuit 600 . The states are referred to as a non-bypass state or a bypass state when the mode control signal MD is "0" or "1". The inverter circuit G 2 outputs an inverted signal of the mode control signal MD.

(a) Bypass operation

The multiplexer 700 selects the data from the serial input port SIB to be supplied to the serial output port SOB. In other words, the serial data bypasses scan register groups 100, 200, 300, 400 and 500 . At this time, the output signal of the inverter circuit G 2 becomes "0" and the output signals of the AND circuits G 4 , G 5 and G 6 are fixed at "0". Therefore, even when the shift clock signals SCK 1 and SCK 2 are output, they are not supplied to the CE scan register 200 , the WE scan register 300 , the DIO scan register group 400 and the DMY scan register 500 . The data held in the scan register groups 200, 300, 400 and 500 therefore do not change.

On the other hand, the shift clock signals SCK 1 and SCKL 2 are directly supplied to the AD scan register group 100 . The AD scan register group 100 thus executes a shift operation even in the bypass state.

When an active low scan signal STB is supplied, the activation signal STBM is fixed at "0" even if the active high comparison signal CMP is generated. This comparison signal CMP is used to test the RAM 2 .

(b) Non-bypass operation

The multiplexer 700 selects the data of the serial output connection SOR of the DMY 500 (see FIG. 14) in order to supply it to the serial output connection SOB. In other words, the serial data passes through scan register groups 100, 200, 300, 400 and 500 .

The output signal of the inverter circuit G 2 becomes "1". When the test mode signal TM is set to "1" and the shift clock signals SCK 1 and SCK 2 are supplied, these shift clock signals pass through the AND circuits G 5 and G 6 and become the scan register groups 200, 300, 400 and 500 as shift clock signals SCK 1 M and SCK 2 M fed. With this, the scan register groups 200, 300, 400 and 500 perform a shift operation.

At this time the shift clock signals SCK 1 and SCK 2 are the AD Abtastregistergruppe fed directly to 100 so that the AD Abtastregistergruppe 100 executes simultaneously with the other Abtastregistergruppen 200, 300, 400 and 500 shift operation. In the non-bypass state, the comparison signal CMP is fixed at "0".

(c) Summary of operations

In the bypass state, the serial data is transferred from the serial input terminal SIB directly to the serial output terminal SOB, and only the AD scan register group 100 carries out the shift operation. In the non-bypass state, the serial data of the serial input port SIB in all the scan registers in the test circuit 3 are shifted to be transmitted to the serial output port SOB. When testing RAM 2 , multiplexer 700 is placed in a bypass state and an active low strobe signal STB is provided to generate comparison signal CMP.

(6) Operation in the Random March Test

A random March test using the test circuit 3 shown in Fig. 4 will be described below.

(a) Initialization operation (see Fig. 18) <1 <reset cycle (step 1; see Fig. 19)

First, the reset signal RST assumes an L level. This causes the mode control signal MD output from the latch circuit 600 to change to "0". This places the test circuit 3 in a non-bypass state. Therefore, all scan registers can perform a shift.

<2 <scan-on cycle (steps S 2 , S 3 ; see Fig. 20)

The majority of the test circuits 3 shown in FIG. 2 are connected in series to implement a long scan path. All of the plurality of test circuits 3 are in a non-bypass state so that all of the scan registers can perform a shift. Therefore, a value can be set by a shift operation in a scan register at any point in the respective test circuit 3 . This is called a scan-on operation. Fig. 20 shows the scan on operation of a bit.

Before the RAM 2 is checked, the scan-on operation sets an initial value in each scan register. The DMY scan register 500 in all test circuits 3 is set to "1". In the test circuit 3 of the RAM 2 to be tested, a "1" is set in the CE scanning register 200 and in the WE scanning register 300 . A desired initial value, e.g. B. An address 0 is set in the AD scan register group 100 and write data is set in the DIO scan register group 400 .

<3 <mode setting cycle (step S 4 ; see Fig. 21)

Next, a mode setting signal MDST with an H-level pulse is supplied. This causes all the mode control signals MD output from the resettable latch circuit 600 in all test circuits 3 to become "1", whereby all test circuits 3 are set in a bypass state. In this state, the same data (data of the serial input connection SIC) are supplied to the serial input connection SIB of all test circuits 3 .

Since the AD scan register group 100 can carry out a shift operation even in the bypass state, the data of the serial input connection SIC can be inserted into the AD scan register group 100 of the respective test circuit 3 .

In the random March test, the test address is updated by inserting the total random sequence into the AD scan register group 100 .

(b) Write All Operation (see Fig. 22)

A random March test procedure writes to all addresses, while the address is updated by inserting the total random sequence. This is called the write-all operation (steps S 11 , S 12 ; see Fig. 23).

The supply of the shift clock signals SCK 1 and SCK 2 causes the content of the AD scan register group 100 to be updated. The address signal A (i) is determined with the clocking of the shift clock signal SCK 1 . When an active low activation signal TCE is supplied, the RAM 2 starts operating in accordance with this address signal. If the active low activation signal TWE is supplied when the activation signal TCE is active, the RAM 2 carries out a write operation in accordance with this address signal.

(c) Read-Write-All operation (see Fig. 24)

A random March test procedure performs a read and Write operation for all addresses while the address is through the insertion of the total random sequence is updated. It will referred to as read-write-all operation.

<1 <read-write cycle (steps S 21 , S 22 ; see Fig. 25)

The supply of the shift clock signals SCK 1 and SCK 2 causes the content of the AD scan register group 100 to be updated. The address signal A (i) is determined with the clocking of the shift clock signal SCK 1 . If an active low activation signal TCE is supplied, the RAM 2 therefore begins to operate in accordance with this address signal. After a predetermined time delay 2 read data DO (i) are output from RAM.

Then, when an active low scan signal STB is supplied, the readout data DO (i) and the readout expectation data held in the DIO scan register group 400 (a logic level opposite to the write data) are compared, and the result is stored in the DIO scan register group 400 .

Thereafter, when an active low activation signal TWE is supplied during the active period of the activation signal TCE, the RAM 2 performs a write operation in accordance with this address signal.

<2 <reset cycle (step S 23 ; see Fig. 19)

The reset signal RST reaches an L level and all test circuits 3 are set to a non-bypass state.

<3 <setting cycle (step S 24 ; see Fig. 26)

Because the test result is held in the 2-input latch circuit L 2 b of each DIO scan register 410 , an adjustment cycle is necessary after the reset cycle when the DIO scan register 410 shown in FIG. 13 is used.

In the setting cycle, only the shift clock signal SCK 2 is supplied, but not the shift clock signal SCK 1 . This causes the test result to the 2-input latch circuit L 2 is transmitted a, to be supplied to the serial output terminal SOR.

Since the test result is supplied to the serial output connection SOR in the DIO scan register 410 of FIG. 12, no adjustment cycle is necessary here.

<4 <scan-off cycle (steps S 25 and S 26 ; see Fig. 27)

The test results held in the DIO scan register group 400 are output by a shift operation. This is called a scan-off cycle. In synchronism with the shift clock signal SCK 2 , the data of all scan registers appear successively at the serial output connection SOC. With an external LSI tester, the data of the serial output connection SOC are checked at a tester sampling time.

(7) Overall operation of the random March test

In the random March test, the test operation is carried out twice with the same procedure and the data "0" / "1". The test procedure for data "0" is shown in Fig. 28, the test procedure for data "1" in Fig. 29. These test procedures are similar except that the data inserted during initialization differs. In other words, the only difference is that either "0" or "1" is set as the initial data in the DIO scan register group 400 . This allows the write data and the readout expectation data for the RAM 2 to be changed .

The test procedure shown in Fig. 28 will be explained below.

<1 <initialization operation (0) (step S 31 )

Write data "0" is set in the DIO scan register group 400 .

<2 <write-all operation (step S 32 )

A write operation with the value "0" is carried out for all addresses. executed.

<3 <initialization operation (1) (step S 33 )

Write data "1" is set in the DIO scan register group 400 . This causes "0" to be set as readout expectation data.

<4 <Read-Write-All-Operation (step S 34 )

A readout of "0" and a write of "1" are carried out for all addresses. At this time, the readout data is compared with the readout expectation data in the DIO scan register group 400 .

<5 <initialization operation (0) (step S 35 )

Write data "0" is set in the DIO scan register group 400 . Thereby, data "1" is set as readout expectation data.

<6 <Read-Write-All-Operation (step S 36 )

A read of "1" and a write of "0" are carried out for all addresses. At this time, the readout data is compared with the readout expectation data in the DIO scan register group 400 . Steps S 41 -S 46 of the test procedure shown in Fig. 29 correspond to steps S 31 -S 36 shown in Fig. 28, except that the data "0" / "1" are different.

(8) Operation of the test circuit 3 ( Fig. 5)

The operation of the test circuit 3 shown in FIG. 5 will now be described. The operation of the test circuit 3 shown in Fig. 5 is similar to that of the test circuit 3 shown in Fig. 4, except that the setting of the mode control signal MD which controls the bypass / non-bypass state is different. Therefore, only the method for setting the mode control signal MD will be explained.

In the latch circuit shown in FIG. 4, the data set by the scan-on operation is input to the latch circuit 600 . The test circuit 3 shown in FIG. 5 has set data in a predetermined AD scan register 110 in the AD scan register group 100 that has been input to the latch circuit 600 . Therefore, when desired data is set in the AD scan register 110 in the initialization operation, this data is set in the latch circuit 600 when the mode setting signal MDST is output. The mode (bypass state / non-bypass state) of the respective test circuit 3 is thus determined.

Although the latch circuit 600 is connected to the serial output port SOR of the last stage AD scan register 110 in the AD scan register group 100 of FIG. 5, the latch circuit 600 may be connected to the serial output port SOR of another AD scan register 110 in of the AD scan register group 100 .

Because the DMY scan register 500 in the test circuit 3 shown in FIG. 5 is not necessary, the complexity of the test circuit can be reduced compared to the test circuit 3 of FIG. 4. In the test circuit 3 shown in Fig. 5, the mode setting data and the start address are stored in an AD scan register 110 so that they cannot be set independently. Therefore, the test circuit shown in Fig. 4 3 and the test circuit 3 shown in Fig. 5 must be used according to the requirements.

(9) Other applications

The test circuit 3 shown in FIGS . 4 and 5 can be applied not only to a single-port RAM but also to a multi-port RAM. Fig. 30 shows the case in which the test circuit 3 is applied to a dual-port RAM 2 b. One test circuit 3 is assigned to one of the two ports (port A, port B) of the dual-port RAM 2 b.

In each test circuit 3 , a serial input terminal SIB, a serial output terminal SOB and control terminals for various control signals RST, MDST, SCK 1 , SCK 2 , STB, TM, TCE and TWE are formed independently and connected within the semiconductor chip. The random march test can be performed on each port in a similar way to that of a single port RAM.

(10) Second embodiment

Fig. 31 shows the structure of the main components of a second embodiment of the present invention. This embodiment differs from that shown in Fig. 1 in that the mode control latch 70 is not formed and the mode control signal MD is supplied directly from an external source.

(11) Third embodiment

Fig. 32 shows a structure of the main components of a third embodiment of the present invention. In this embodiment, the AD scan register group 10 is supplied with the shift clock signal SCKA and the DI scan register group 20 and the DO scan register group 30 with the shift clock signal SCKD. Because the shift clock signal SCKA and the shift clock signal SCKD are separate, the AD scan register group 10 can perform a shift operation while the operation of the DI scan register group 20 and the DO scan register group 30 is stopped.

In Figs. 1, 31 and 32 shown test circuits may also be integrated semiconductor circuit shown 49 are applied to the in Fig..

(12) Fourth embodiment (a) Forest

Fig. 33 shows a block diagram of a structure for the additional test circuit (scan) of a semiconductor integrated circuit device according to a fourth embodiment.

A plurality of AD scan registers 10 a and a plurality of data input / output scan registers (hereinafter referred to as DIO scan registers) 25 a are arranged around a RAM 2 . The structure of the respective AD scan register 10 a is similar to that of the AD scan register 10 a of FIG. 44.

The scan register 10 a are similar to the AD scan register 10 a of FIG. 44.

The scan registers 10 a and 25 a connecting the normal operation of the RAM 2 (not shown) other logic circuits on the semiconductor chip with the RAM 2 and separate testing of the RAM 2, the other logic circuits of RAM 2 from.

These scan registers 10 a and 25 a are connected in series between the serial input port SIC and the serial output port SOC to implement a scan path. The address signal and the test data are supplied to the RAM 2 by the shift function of the scan path. The test result of the RAM 2 is entered in the DIO scan register 25 a within the scan path.

(b) First example of the DIO scan register

Fig. 34 shows a first example of the DIO scan register 25 a. This scan register 25 a has a structure which is similar to that of the scan register 410 of Fig. 12.

The serial input terminal SI is connected to the input terminal D 2 of the first latch circuit L 2 a. The first parallel input terminal PI 1 is connected to the input terminal D 1 of the first latch circuit L 2 a and the first parallel output terminal PO 1 to the output terminal Q of the first latch circuit L 2 a. The second parallel input terminal PI 2 is connected to the input terminal D 1 of the second latch circuit L 2 b. The second parallel output terminal PO 2 is connected to the output terminal Q of the second latch circuit L 2 b and the serial output terminal SO to the output terminal of the inverter G 16 .

The serial clock signal connection sck 1 , which receives the serial shift clock signal SCK 1 of the first phase, is with the activation connection EN 2 of the first latch circuit L 2 a and the serial clock signal connection sck 2 , which receives the serial shift clock signal SCK 2 of the second phase connected to the activation terminal EN 2 of the second latch circuit L 2 b. The parallel clock signal connection PCK 1 , which receives the parallel clock signal PCK 1 , is connected to the activation connection EN 1 of the first latch circuit L 2 a. The test clock signal terminal tck, which receives the test clock signal TCK, is connected to an input of the NAND circuit G 18 and the test mode terminal tm, which receives the test mode signal TM, is connected to an input of the NAND circuit G 17 .

The data of the serial input connection SI and the data of the first parallel input connection PI 1 are fed to the first latch circuit L 2 a. Data obtained by inverting the output signal from the first latch circuit L 2 a and data of the second parallel input terminal PI 2 are input to the second latch circuit L 2 b.

The data of the second parallel input connection PI 2 are compared by the exclusive OR circuit G 19 with the inverted data held in the first latch circuit L 2 a. The comparison result is supplied to the other input terminal of the NAND circuit G 18 . The output signal of the NAND circuit G 18 is passed to the other input terminal of the NAND circuit G 17 . The output signal PCK 2 (the second test clock signal) of the NAND circuit G 17 is supplied to the activation terminal EN 1 of the second latch circuit L 2 b as a latch activation signal.

A pair of a data input connection and a data output connection of the RAM 2 is assigned to a DIO sampling register 20 a. The second parallel input terminal PI 2 of the respective DIO sampling register 25 a is connected to the data output terminal DOi (i = 1, ..., n) of the RAM 2 . Here n is a natural number. The first parallel output terminal PO 1 of the respective DIO scan register 25 a is connected to the data input terminal DIi of the RAM 2 . Specifically, A of Fig. 34, the input data to the RAM 2 associated with a master latch in the scan register 25 DIO said, and the output data of the RAM 2 will be assigned to a slave latch.

Fig. 35 shows an example of a structure of the DIO-scan register 25 a as a MOS circuit having a function that matches with that of DIO-scan register 25 a of Fig. 34. . The DIO-scan register 35 shown in Figure 25 has a N-channel MOS transistors N 31 - N 34 and inverter 31 to G 34 -G. The inverters G 31 and G 32 and also the inverters G 33 and G 34 implement a latch circuit L 31 and L 32 of the ratio type. The driving capacity of the inverters G 32 and G 34 is lower than that of the inverters G 31 and G 33 . Components with similar reference numerals in Figs. 35 and 34 indicate equivalent or corresponding components.

Instead of the N-channel MOS transistors shown in FIG. 35, P-channel MOS transistors can also be used.

Using a CMOS 2-input latch circuit shown in Figs. 36 and 37 is shown, of the latch circuit in place of Fig. 35, a DIO-scan register 25 a implemented with a function similar to that of 34 DIO scan register 25 a shown in FIG . In the DIO scan register 25 a shown in FIG. 36, the second parallel output connection PO 2 is connected directly to the node B. In the DIO scan register 25 a shown in FIG. 37, the second parallel output connection PO 2 is connected to the node B by two inverters. The components in FIGS. 36 and 37 with identical reference numerals to the components in FIGS. 34 and 35 denote equivalent or corresponding components.

(c) Operation of the DIO scan register

Referring to Fig. 35, the operation of DIO scan register 25 a will now be described.

During normal operation of the RAM 2 , the potentials of the serial clock signal connections sck 1 , sck 2 and the test mode connection TM are set to an L level, and the potential of the parallel clock signal connection pck 1 is set to an H level. This causes data to be input to the RAM 2 to be transferred from the first parallel input port PI 1 to the first parallel output port PO 1 . The second test clock signal PCK 2 also reaches an H level. This causes the data output from the RAM 2 to be transmitted from the second parallel input port PI 2 to the second parallel output port PO 2 . At this time, the potential of the test clock signal terminal tck can be set to either an H or an L level.

When testing the RAM 2 , the potential of the parallel clock signal connection pck 1 is set to an L level, the potential of the test clock signal connection tck to an L level and the potential of the test mode connection TM to an H level. This separates the RAM 2 from the other logic circuits. The first and second phases of the clock signals SCK 1 and SCK 2 , which are fed to the shift clock signal connections sck 1 and sck 2 , furthermore perform a shift operation, as a result of which the test result is read out.

(d) Operation of the fourth embodiment

Fig. 38 shows a timing diagram of the shift operation of the additional test circuit of Fig. 33. The clock signal of the first phase is supplied to the serial clock signal connection sck 1 a of each AD scanning register 10 a and the serial actual signal connection sck 1 of each DIO scanning register 25 a. The second phase text signal is fed to the serial clock signal connection sck 2 a of each AD scanning register 10 a and the serial clock signal connection sck 2 of each DIO scanning register 25 a.

The data of the serial input connection SI of the respective Scan registers are sent to the node with the first phase clock signal A entered in it. The data of node A are inverted and transmitted to node B by the second phase clock signal. The Data of node B is inverted and the serial Output terminal SO supplied.

This is a shift operation of a bit from the serial Input port SI to serial output port SO executed. The shift operation is from the clock signals first and second Phase executed, causing the setting of test data and that Reading out test results is carried out.

FIG. 39 shows a timing chart of the operation of the additional test circuit shown in FIG. 33 at the time of testing. When testing the RAM 2 , the potential of the test mode terminal tm is set to an H level. The serial clock signal connections sck 1 and sck 2 of the DIO sampling register 25 a are supplied with the shift clock signals SCK 1 and SCK 2 first and second phase. The serial clock signal connections sck 1 a and sck 2 a of the AD scanning register 10 a are supplied with shift clock signals SCK 1 a and SCK 2 a, which differ from the shift clock signals. This will update the test address.

Inverted data of the readout expected data are set in the first parallel output terminal PO 1 . These inverted data are further inverted by inverter G 15 (inverter G 31 in FIG. 35). The read-out expected data are thus compared with the data read from the RAM 2 to the second parallel input terminal PI 2 by the exclusive-OR circuit G 19 .

A test clock signal TCK is supplied to the test clock signal terminal tck whenever data is read out from the RAM 2 . If an error value (incorrect data) is read out from the RAM 2 , a second test clock signal PCK 2 is therefore generated, the phase of which corresponds to that of the test clock signal TCK of the test clock signal terminal tck. The data of the second parallel input connection PI 2 is thus transmitted via the node B to the second parallel output connection PO 2 . A readout expected value is set beforehand at node B via a shift operation (a value opposite to the inverted data of the first parallel output connection PO 1 ). If an error value is read out from RAM 2 , the data of the second parallel output connection PO 2 are therefore inverted.

After the above-described operation is performed for a plurality of addresses, the test result is read out by performing the shift operation shown in FIG. 38. This allows corresponding to the fact that the are a held data inverted in the latch circuit in DIO scan register 25 or can not be determined whether the second parallel input port PI 2 data has been supplied, which differ from the read-out expectation data, or not .

(e) Second example of the DIO scan register

Fig. 40 shows a circuit diagram of another example of the DIO sample register 25 a. The illustrated in Fig. 40 DIO-scan register 25 a has a structure similar to that of DIO-scan register 410 in Fig. 13. The components in FIG. 40 with the same reference numerals as in FIG. 34 denote equivalent or similar components.

Data from the serial input terminal SI and data from the second parallel input terminal PI 2 are fed to the second latch circuit L 2 b. The first latch circuit L 2 a is supplied with inverted data of the output from the second latch circuit L 2 b and the data of the first parallel input terminal PI 1 .

The data of the second parallel input connection PI 2 are compared by the exclusive-OR circuit G 19 with the inverted of the data held in the first latch circuit L 2 a. The comparison result is fed to the NAND circuit G 18 . The output signal of the NAND circuit G 18 is supplied to the NAND circuit G 17 . The output signal PCK 2 (second test clock signal) of the NAND circuit G 17 is supplied to the activation terminal EN 1 of the second latch circuit L 2 b as a latch activation signal.

The second parallel input port PI 2 is connected to the data output port of RAM 2 and the first parallel output port PO 1 to the data input port of RAM 2 .

In the DIO scan register 25 a, which is shown in FIG. 34, the data input to RAM 2 is assigned to a master latch and the data output from RAM 2 to a slave latch. In the DIO scan register 25 a, which is shown in FIG. 40, the data output from RAM 2 is assigned to a master latch and the data input to RAM 2 is assigned to a slave latch.

Fig. 41 shows an example of a DIO-scan register by a function which is a of FIG. 40 similar to that of DIO-scan register 25, and a latch used on the ratio type. The components in FIG. 41 with the same reference numerals as those in FIG. 34 denote equivalent or similar components.

The operation of the shown in Fig. 41 DIO-scan register 25 a is substantially that of in Figs. 34 to 37 shown DIO scan register 25 a similar. Because the test result is held in the master latch in the scan registers shown in FIGS . 40 and 41, it is necessary to be somewhat careful when reading out the test result by a shift operation. More specifically, the test result must first be transmitted to the slave latch by supplying a shift clock signal to the serial clock signal port sck 2 , followed by the shift operation shown in Fig. 38 to read the test result in a non-destructive manner.

(f) Another example of the comparison circuit and the latch Activation circuit

In the embodiments shown in FIGS. 34 to 41, the exclusive OR circuit G 19 is used as a comparison circuit in order to compare the data of the second parallel input terminal PI 2 and the data held in the first latch circuit 2 a. Furthermore, the NAND circuits G 17 and G 18 are used as a latch activation circuit in order to lock the data of the second parallel input connection PI 2 to the second latch circuit L 2 b in accordance with the comparison result. However, the comparison circuit and the latch activation circuit are not limited to the combination of such logic circuits.

For example, an exclusive NOR gate G 41 can be used as a comparison circuit, and a NOR circuit G 42 or an OR circuit G 43 can be used as a latch activation circuit, as shown in FIG. 42. One input terminal of the NOR circuit G 42 is connected to the output terminal of the exclusive NOR circuit G 41 and the other input terminal is connected to the test clock signal terminal tck *, which receives the inverted test clock signal tck *. One input terminal of the OR circuit G 43 is connected to the output terminal of the NOR circuit G 42 and the other input terminal is connected to the test mode terminal tn *, which receives the inverted test mode signal TM *.

(g) Advantage of the fourth embodiment

According to the fourth embodiment, the data input is one of two latch circuits and the data output to the other latch Associated circuit that form a scan register. Hence the Data input / output possible with a scan register. Leading to reduce the complexity of the additional Test circuit in an integrated Semiconductor circuit device.

As shown in Figs. 34 and 40, the implementation of each scan register by two ratio type latch circuits significantly reduces the number of parts to be used. This is very effective for reducing circuit complexity.

(h) Other applications

In the fourth embodiment, the circuit under test is RAM 2 , and the data output terminal of RAM 2 is connected to the additional test circuit. The additional test circuitry of the present invention may be connected to a data bus connected to a plurality of RAMs.

The circuit under test is not limited to a RAM. The additional test circuitry of the present invention can be implemented any circuit that is applied continuously Outputs data "0" or "1". This leads to similar effects.

Claims (30)

1. Scanning path device, comprising
a first scan register group ( 10 ) with a plurality of first scan registers ( 110 ) connected in series,
a second scan register group ( 20, 30 ) connected in series with the output of the first scan register group ( 10 ), with a plurality of second scan registers ( 410 ) connected in series, and
a control device (SCK, 60 ) for controlling the first and second scan register groups ( 10, 20, 30 ) so that the second scan register group ( 20, 30 ) interrupts their shift operation and the first scan register group ( 10 ) carries out their shift operation. 2. Scanning path device according to claim 1, characterized in that the control device
means for applying a shift clock signal (SCK) to the first scan register group ( 10 ), and
a device ( 60 ), which is dependent on a predetermined control signal (MD), for applying the shift clock signal (SCK) to the second scan register group ( 20, 30 ). 3. Scanning path device according to claim 1, characterized in that the control device
means for applying a first shift clock signal (SCKA) to the first scan register group ( 10 ), and
has a device for applying a second shift clock signal (SCKD), which is dependent on the first shift clock signal (SCKA), to the second scan register group ( 20, 30 ). 4. Scanning path device according to claim 1, characterized in that
the first scan register group ( 10 ) has a function for parallel output of serial data and a function for serial output of serial data to the second scan register group ( 20, 30 ), and
the second scan register group ( 20, 30 ) has a function for parallel output of serial data from the first scan register group ( 10 ) and a function for serial output of parallel data. 5. Scan path device according to claim 4, characterized in that each of the plurality of second scan registers ( 410 )
a serial input port (SIR),
a first parallel input connection (dix; do),
a second parallel input connection (do; dix),
a first holding device (L 2 a; L 2 b) for holding and outputting a supplied value,
a second holding device (L 2 b; L 2 a) for holding and outputting a supplied value,
a first transmission device (EN 1 ) for transmitting data from the first parallel input connection (dix; do) to the first holding device (L 2 a; L 2 b),
a second transmission device (EN 2 ) for transmitting data from the serial input connection (SIR) to the first holding device (L 2 a; L 2 b),
a third transmission device (EN 1 ) for transmitting data from the second parallel input connection (do; dix) to the second holding device (L 2 b; L 2 a),
a fourth transmission device (EN 2 ) for transmitting data from the first holding device (L 2 a; L 2 b) to the second holding device (L 2 b; L 2 a),
a first parallel output connection (di; dox) for receiving data which are output by the first holding device (L 2 a; L 2 b),
a second parallel output terminal (dox; di) for receiving data output from the second holding device (L 2 b; L 2 a);
a serial output port (SOR) for receiving data output from the second holding device (L 2 b; L 2 a),
a comparison device (G 19 ) for comparing the data of the second or first parallel input connection (do, dix) with data which are output from the first or second holding device (L 2 a, L 2 b), and
an activation device (G 17 , G 18 ) for activating / deactivating the third or first transmission device (EN 1 ) in accordance with the comparison result of the comparison device (G 19 ), wherein
the serial input port (SIR) of every other scan register ( 410 ) is connected to the serial output port (SOR) of the scan register ( 410 ) of the previous stage. 6. Scanning path device, comprising
an input port (SIB) for receiving serial data,
a first scan register group ( 10 ) having a plurality of first scan registers ( 110 ) connected in series with the input terminal (SIB),
a second scan register group ( 20, 30 ) connected in series with the output of the first scan register group ( 10 ) with a plurality of second scan registers ( 410 ) connected in series,
an output connection (SOB),
a selector ( 50 ) for selecting either the data of the input port (SIB) or the data output from the second scan register group ( 20, 30 ) to supply the selected data to the output port (SOB), and
first control means (SCK, 60 ) for controlling the first and second scan register groups ( 10, 20, 30 ) so that the second scan register group ( 20, 30 ) stops shifting and the first scan register group ( 10 ) does its shift operation when the Selector ( 50 ) the data of the input port (SIB) have been selected. 7. Scanning path device according to claim 6, characterized by a device for receiving a control signal (MD) which controls the selection state of the selection device ( 50 ), the first control device
means for applying a shift clock signal (SCK) to the first scan register group ( 10 ), and
a device ( 60 ), which is dependent on the control signal (MD), for applying the shift clock signal (SCK) to the second scan register group ( 20, 30 ). 8. scan path device according to claim 6, characterized by a second control device ( 70 ) for receiving data from a scan register ( 40 ) contained in the first or second scan register group ( 10, 20, 30 ) for controlling the selection device ( 50 ) depending on the data received. 9. scan path device according to claim 8, characterized in that the first control device
means for applying a shift clock signal (SCK) to the first scan register group ( 10 ), and
a device ( 60 ), which is dependent on the output signal of the second control device ( 70 ), for applying the shift clock signal (SCK) to the second scan register group ( 20, 30 ). 10. scan path device according to claim 6, characterized in that
the first scan register group ( 10 ) has a function for parallel output of serial data and a function for serial output of serial data to the second scan register group ( 20, 30 ), and
the second scan register group ( 20, 30 ) has a function for parallel output of serial data from the first scan register group ( 10 ) and a function for serial output of parallel data. 11. Scan path device according to claim 10, characterized in that each of the plurality of second scan registers ( 410 )
a serial input port (SIR),
a first parallel input connection (dix; do),
a second parallel input connection (do; dix),
a first holding device (L 2 a; L 2 b) for holding and outputting supplied data,
a second holding device (L 2 b; L 2 a) for holding and outputting supplied data,
a first transmission device (EN 1 ) for transmitting data from the first parallel input connection (dix; do) to the first holding device (L 2 a; L 2 b),
a second transmission device (EN 2 ) for transmitting data from the serial input connection (SIR) to the first holding device (L 2 a; L 2 b),
a third transmission device (EN 1 ) for transmitting data from the second parallel input connection (do; dix) to the second holding device (L 2 b; L 2 a),
a fourth transmission device (EN 2 ) for transmitting data from the first holding device (L 2 a; L 2 b) to the second holding device (L 2 b; L 2 a),
a first parallel output connection (di; dox) for receiving data which are output by the first holding device (L 2 a; L 2 b),
a second parallel output connection (dox; di) for receiving data which are output by the second holding device (L 2 b; L 2 a),
a serial output port (SOR) for receiving data output from the second holding device (L 2 b; L 2 a),
a comparison device (G 19 ) for comparing the data of the second or first parallel input connection (do; dix) with data which are output from the first or second holding device (L 2 a, L 2 b), and
an activation device (G 17 , G 18 ) for activating / deactivating the third or first transmission device (EN 1 ) in accordance with the comparison result of the comparison device (G 19 ), wherein
the serial input port (SIR) of every other scan register ( 410 ) is connected to the serial output port (SOR) of the scan register ( 410 ) of the previous stage. 12. Integrated semiconductor circuit device, comprising
a storage device ( 2 ) for storing data, and
a scan path device ( 3 ), wherein
the scan path device ( 3 )
an input port (SIB) for receiving serial data,
a first scan register group ( 10 ) with a plurality of first scan registers ( 110 ), which are connected in series, for parallel output of data, which are applied serially from the input connection (SIB), to the memory device as an address signal,
a second scan register group ( 20, 30 ) with a plurality of second scan registers ( 410 ), which are connected in series, for the parallel application of data to the memory device ( 2 ), which are supplied serially by the first scan register group ( 10 ), or for Receiving parallel data output from the memory device ( 2 ),
a selector ( 50 ) for selecting either the data of the input port (SIB) or the data output from the second scan register group ( 20, 30 ) to output the selected data, and
first control means (SCK, 60 ) for controlling the first and second scan register groups ( 10, 20, 30 ) so that the second scan register group ( 20, 30 ) stops shifting and the first scan register group ( 10 ) does its shift operation when the Selection device ( 50 ), the data of the input connection (SIB) have been selected. 13. The semiconductor circuit device according to claim 12, characterized in that the scan path device ( 3 ) comprises a second control device ( 70 ) for receiving data from a scan register ( 40 ) which is contained in the first or second scan register group ( 10, 20, 30 ), for controlling the selection device ( 50 ) depending on this data. 14. A semiconductor circuit device according to claim 13, characterized in that the first control device
means for applying a shift clock signal (SCK) to the first scan register group ( 10 ), and
a device ( 60 ), which is dependent on the output signal of the second control device ( 70 ), for applying the shift clock signal (SCK) to the second scan register group ( 20, 30 ). 15. A semiconductor circuit device according to claim 12, characterized in that the scanning path device ( 3 )
holding means ( 49 ), formed in series with the first and second sample register groups ( 10, 20, 30 ), for holding a mode setting value, and
a second control device ( 70 ), which is dependent on the mode setting value which is held in the holding device ( 40 ), for controlling the selection device ( 50 ). 16. A semiconductor circuit device according to claim 15, characterized in that the first control device
means for applying a shift clock signal (SCK) to the first scan register group ( 10 ), and
a device ( 60 ), which is dependent on the output signal of the second control device ( 70 ), for applying the shift clock signal (SCK) to the second scan register group ( 20, 30 ). 17. The semiconductor circuit device according to claim 12, characterized in that each of the plurality of second scanning registers ( 410 ) has a serial input connection (SIR),
a first parallel input connection (dix; do)
a second parallel input connection (do; dix),
a first holding device (L 2 a; L 2 b) for holding and outputting supplied data,
a second holding device (L 2 b; L 2 a) for holding and outputting supplied data,
a first transmission device (EN 1 ) for transmitting data from the first parallel input connection (dix; do) to the first holding device (L 2 a; L 2 b),
a second transmission device (EN 2 ) for transmitting data from the serial input connection (SIR) to the first holding device (L 2 a; L 2 b),
a third transmission device (EN 1 ) for transmitting data from the second parallel input connection (do; dix) to the second holding device (L 2 b; L 1 a),
a fourth transmission device (EN 2 ) for transmitting data from the first holding device (L 2 a; L 2 b) to the second holding device (L 2 b; L 2 a),
a first parallel output connection (dox; di) for receiving data which are output by the first holding device (L 2 a; L 2 b),
a second parallel output connection (di; dox) for receiving data which are output by the second holding device (L 2 b; L 2 a),
a serial output port (SOR) for receiving data output from the second holding device (L 2 b; L 2 a),
a comparison device (G 19 ) for comparing the data of the second or first parallel input connection (do; dix) with data output by the first or second holding device (L 2 a, L 2 b), and
an activation device (G 17 , G 18 ) for activating / deactivating the third or first transmission device (EN 1 ) in accordance with the comparison result of the comparison device (G 19 ), wherein
the serial input port (SIR) of every other scan register ( 410 ) is connected to the serial output port (SOR) of the scan register ( 410 ) of the previous stage. 18. Additional test circuit, having
a plurality of scan registers ( 25 a) which are connected in series, wherein
each of the plurality of scan registers ( 25 a) has a serial input connection (SI),
a first parallel input connection (PI 1 ; PI 2 ),
a second parallel input connection (PI 2 , PI 1 ),
a first holding device (L 2 a; L 2 b) for holding and outputting supplied data,
a second holding device (L 2 b; L 2 a) for holding and outputting supplied data,
a first transmission device (EN 1 ; N 32 ; N 34 ) for transmitting data from the first parallel input connection (PI 1 ; PI 2 ) to the first holding device (L 2 a; L 2 b),
a second transmission device (EN 2 ; N 31 ; N 33 ) for transmitting data from the serial input connection (SI) to the first holding device (L 2 a; L 2 b),
a third transmission device (EN 1 ; N 34 ; N 32 ) for transmitting data from the second parallel input connection (PI 2 ; PI 1 ) to the second holding device (L 2 b; L 2 a),
a fourth transmission device (EN 1 ; N 33 ; N 31 ) for transmitting data from the first holding device (L 2 a; L 2 b) to the second holding device (L 2 b; L 2 a),
a first parallel output connection (PO 1 ; PO 2 ) for receiving data which are output by the first holding device (L 2 a; L 2 b),
a second parallel output connection (PO 2 ; PO 1 ) for receiving data which are output by the second holding device (L 2 b; L 2 a),
a serial output connection (SO) for receiving data which are output by the second holding device (L 2 b; L 2 a),
a comparison device (G 19 ) for comparing the data of the second or first parallel input connection (PI 2 ) with data output from the first or second holding device (L 2 a), and
an activation device (G 17 , G 18 ) for activating / deactivating the third or first transmission device (EN 1 ; N 34 ) in accordance with the comparison result of the comparison device (G 19 ), wherein
the serial input port (SI) of each scan register ( 25 a) is connected to the serial output port (SO) of the scan register ( 25 a) of the previous stage. 19. Test circuit according to claim 18, characterized in that the comparison device (G 19 ) compares data of the second parallel input connection (PI 2 ) with data which are output by the first holding device (L 2 a), and the activation device (G 17 , G 18 ) the third transmission device (EN 1 ; N 34 ) activated / deactivated. 20. Test circuit according to claim 18, characterized in that the comparison device (G 19 ) compares data of the first parallel input connection (PI 2 ) with data which are output by the second holding device (L 2 a), and the activation device (G 17 , G 18 ) the first transmission device (EN 1 ; N 34 ) activated / deactivated. 21. Test circuit according to claim 18, characterized in that each of the first and second holding devices (L 2 a, L 2 b) has a latch circuit (L 31 , L 32 ) of the ratio type (a ratio-type latch circuit) . 22. Test circuit according to claim 18, characterized in that each of the first and second holding devices (L 2 a, L 2 b) has a CMOS circuit. 23. Test circuit according to claim 18, characterized in that the activation device (G 17 , G 18 ) activates the third or first transmission device (EN 1 ; N 34 ) when the comparison result of the comparison device (G 19 ) indicates a mismatch, and that the activation device (G 17 , G 18 ) deactivates the third or first transmission device (EN 1 ; N 34 ) when the comparison result indicates a match. 24. Test circuit according to claim 23, characterized in that the first or third transmission device (EN 1 ; N 32 ) is activated as a function of a parallel shift clock signal (PCK 1 ),
the second transmission device (EN 2 ; N 31 ; N 33 ) is activated as a function of a first serial shift clock signal (SCK 1 ), and
the fourth transmission device (EN 2 ; N 33 ; N 31 ) is activated as a function of a second serial shift clock signal (SCK 2 ). 25. Test circuit according to claim 24, characterized in that the activation device (G 17 , G 18 ) activates the third or first transmission device (EN 1 ; N 34 ) as a function of a test mode signal (TM). 26. Test circuit for an integrated semiconductor circuit device, comprising
a plurality of scan registers ( 25 a) connected in series to implement a scan path, wherein
each of the plurality of scan registers ( 25 a) a first latch device (L 2 a) with a first serial input connection (D 2 ) and a first parallel input connection (D 1 ) for locking data,
a second latch device (L 2 b) with a second serial input connection (D 2 ) and a second parallel input connection (D 1 ) for locking data,
a comparison device (G 19 ) for comparing the data of the second parallel input connection (D 1 ) with the data which are locked in the first latch device (L 2 a), and
a latch activation device (G 17 , G 18 ) for locking data of the second parallel input connection (D 1 ) in the second latch device (L 2 b) in accordance with the comparison result of the comparison device (G 17 ). 27. Test circuit according to claim 26, characterized in that the integrated semiconductor circuit device has a random access memory ( 2 ) with a plurality of data output connections (DO 1 -DOn) and a plurality of data input connections (DI 1 -DIn), the second parallel input connection (D 1 ) of each scan register ( 25 a) is connected to one of the plurality of data output connections (DO 1 -DOn), and the output of the first latch device (L 2 a) of each scan register ( 25 a) is connected to one of the plurality of data input connections (DI 1 -DIn) is connected. 28. Operating method for a scan path device having a first scan register group ( 10 ) with a plurality of first scan registers ( 110 ) connected in series and a second scan register group ( 20, 30 ) connected to the output of the first scan register group ( 10 ) and includes a plurality of second scan registers ( 410 ) connected in series, characterized by the steps:
Controlling the first and second scan register groups ( 10, 20, 30 ) so that the second scan register group ( 20, 30 ) interrupts their shift operation and the first scan register group ( 10 ) carries out their shift operation. 29. Operating method according to claim 28, characterized by the steps:
Selecting either the data supplied to the first scan register group ( 10 ) or the data output from the second scan register group ( 20, 30 ) to output the selected data, wherein
the step of controlling includes the step of controlling the first and second scan register groups ( 10, 20, 30 ) so that the second scan register group ( 20, 30 ) will shift when the data corresponding to the first scan register group ( 10 ) are supplied. 30. Operating method for an additional test circuit with a plurality of scan registers ( 25 a) connected in series, each scan register ( 25 a) having a serial input connection (SI), a first and a second parallel output connection (PI 1 , PI 2 ) and a first and second holding device (L 2 a; L 2 b), characterized by the steps:
Applying the data of the serial input connection (SI) to the first holding device (L 2 a; L 2 b) as a function of a first serial shift clock signal (SCK 1 ),
Applying the data which are output by the first holding device (L 2 a; L 2 b) to the second holding device (L 2 b; L 2 a) as a function of a second serial shift clock signal (SCK 2 ),
Comparing the data from the second or first parallel input terminal (PI 2 ) with the data output from the first or second holding device (L 2 a), and
Applying the data of the second or first parallel input connection (PI 2 ) to the first or second holding device (L 2 a) if the comparison result indicates a mismatch.