DE4143584C2 - Bus system for information processing appts. - Google Patents

Abstract

A bus system for an information processing device contains a processor (111) bus connected to at least one processor (101), a memory bus (112) connected to at least one main memory (104) and a system bus (113). Data path control signals are generated by a connection controller which also generates a control signal and an address signal for one of the processor, system and memory buses. A data switching device is connected to data buses of each of the processor bus, memory bus and system bus for direct transfer, in response to the data path control signal, of data between data buses.

Description

The present invention relates to an information processing system a bus system. Examples of such information processing systems are a workstation, a personal computer and a word processor.

A bus system which is arranged in an information processing system is structured like a bus system, which is written in a report "EISA" by L. Brett Glass on pages 417 to 424 of "BYTE", volume 14, no. 12 (1989); such that memory and system buses each with connected to a processor bus, or processor and memory buses are each connected to the system bus.

In the former structure, the processor bus can be used during a common Action of the system and memory buses, namely during the so-called direct memory access (DMA) does not work in an independent manner, which consequently leads to a deterioration in the use efficiency of the Processor bus leads. In the latter case, the system bus can be different partly during a joint operation of the processor and memory bus se, d. H. during the so-called memory access, not to an independent kind of work, which leads to the problem of deterioration of the user efficiency of the system bus.  

In this regard, the structure and problems of bus systems in conventional information processing systems later in detail under Described with reference to the drawing pages.

EP 0141302 A1 describes a data processing system architecture known. This known data processing system architecture has three buses connected to tri-directional communication control gates. The Communication control gates serve to connect the buses and ver to implement different communication states. However, it is not before seen a system bus regardless of a connected pair of one Processor bus and a memory bus to use.

From "measure, test, automate", July / August 1985, pp. 404-408 a structure with three buses is known, in which a RAM memory with Double access (internal and external) is required.

DE 33 38 341 A1 describes a multiprocessor system in which the Connection between processors and memories via a multiple bus order is made. Each processor is made up of one processor connection bus via one coupler each with at least one bus and each memory through one memory connection bus each over one Coupler connected to at least one bus.

Starting from this prior art, the object of the invention based on an information processing system with multiple buses of the Specify the type mentioned above, which is an operation of a bus enabled independently of the other buses.

According to the invention, this task is accomplished with information processing System solved according to claim 1. Advantageous further developments are in the Subclaims defined.

In the present invention, a control device is provided which a three-way connection of three types of buses including one Processor bus connected to at least one processor, one Memory bus connected to a main memory and one System bus that with at least one connected device such as for example connected to an input / output (I / O) device, which establishes connections between different buses.  

In other words, an information processing system includes one Processor bus connected to at least one processor, one Memory bus connected to a main memory and one System bus that ver with at least one connected device is bound, and a connection control device for connecting these buses together.

The data switch and the bus / memory link controller can each be built as integrated circuits or together in be connected to an integrated circuit.

The number of buses of any kind is not limited to one. Also when a plurality of buses of each of the three types can be arranged namely the connection control device to be constructed similarly to a Establish connection between these buses.

In the construction of the present invention described above, wherein connecting the three types of buses, the processor, memory and contains system buses, z. B. if a processor on the Processor bus performs a processor / main memory access to to access the main memory on the memory bus, data only through the Processor and memory buses transferred; d. H. the system bus is used for the Data transfer not needed. Consequently, the system bus can be set to one independent way of working. On the other hand, if an attached Device on the system bus performs a DMA to access the To access main memory on the memory bus, data is only through transfer the system and memory buses. That means that the Processor is not used for transmission, and therefore one can perform independent surgery.  

As a result, it is possible to maximize the usage efficiency for to develop each of the three types of buses.

Further advantages, features and possible uses of the present the invention result from the following description of Embodiments in connection with the drawing, wherein:

Fig. 1 is a schematic diagram showing the processing system according to the present invention showing the structure of a first embodiment of a Informationsverarbei;

Figs. 2 and 3 are diagrams that schematically show the construction of bus systems and information processing systems according to the prior art;

Fig. 4 is a diagram that illustratively shows an embodiment of a three-way connection control 103 in the shown in Figure 1 first embodiment of the constricting vorlie invention.

Fig. 5 and 6 are block diagrams, each of embodiments of a data path switch 402 and a bus / memory connection control 401 in the embodiment of the three-way connection controller 103 of Figure 4 zei gene, which is used before lying invention, in the first embodiment.

Figure 7 is a schematic diagram showing the processing system according to the present invention showing the structure of a second embodiment of a Informationsverarbei.

Figure 8 is a schematic diagram showing the processing system according to the present invention showing the configuration of a third embodiment of a Informationsverarbei.

Fig. 9 is a diagram showing the correlation between a data path control signal 420, the decoding operation according to the present invention by a decoder 510 of the data path switch 402 of Figure 5 is to dekodie reindeer, and results.

Fig. 10 to 15 are diagrams, each of relationships between the data path control signal (DT_CNT) 420 and other Singalen in the various stages of a transition state in the processor / Hauptspeicherlese-, Pro zessor- / Hauptspeicherschreib-, processor / vorrichtungslese- system bus, Processor / system bus device write, DMA read and DMA write operations;

FIG. 16 is a transition diagram showing an example of a transition of a stand to Datenzuordners or a flow control device 601 in the bus / Speicherverbin dung controller 401 of Figure 6 shows.

. 17 and 18 are signal timing diagrams FIG showing examples of data tragungsoperationen show that belong to Figures 9 to 16. and

19 is Fig. A diagram showing a structure, in particular Ver compounds of signals of FIG. 17 and 18 between the three-way connection controller 103 of Fig. 4 and the respective buses 111 to 113 shows.

If one now makes reference to the drawing pages, games of an information processing system according to the present Invention described.

First, a first embodiment of the present invention will be described with reference to FIGS. 1 to 6. In this regard, FIGS . 2 and 3 show structures of a bus system in conventional technology, which is described in detail here for comparison with the present invention.

Processors 101 (n processors; where n is an integer), a cache memory system 102 , main memory 104 and system bus connection devices 105 (M devices; where M is an integer) are arranged in each of FIGS. 1 to 3. The connected devices 105 can be so-called I / O devices such as a controller for diskette files, a controller for drawing and displaying images and a controller for networks and telecommunications connections. A processor bus is designated 111 , a memory bus 112 and a system bus 113 . In Fig. 1, a three-way connection controller is designated 103 . In FIGS. 2 and 3, bus controllers are designated by 201 and 301 and controls Speicherver bond respectively with 202 and 302.

In the conventional bus systems of these figures, the system bus 113 and the memory bus 112 of FIG. 2 are each connected to the process sorbus 111 in an independent manner via the bus connection controller 201 and the memory connection controller 202 . On the other hand, in FIG. 3, the processor bus 111 and the memory bus 112 are each connected to the system bus 113 in an independent manner via the bus connection controller 301 and the memory connection controller 302 .

In the construction of Fig. 2, the data between a connected device 105 on the system bus 113 and main memory 104 the data is for a DMA operation that transfers on the memory bus 112, sent through the processor 111th As a result, it is impossible to simultaneously perform the DMA operation and an independent operation of the processor bus 111 , for example for data transfer between the processor 101 and the cache 102 or between a plurality of processors 101 . On the other hand, in the structure of FIG. 3, in the so-called processor / main memory access, in which data is transferred between the processor 101 and the main memory 104 , data is passed through the system bus 113 . As a result, it is impossible to simultaneously perform processor / main memory access and independent system bus 113 operation , for example, for data transfer between a plurality of devices 105 connected to system bus 113 .

In contrast, the bus system shown in FIG. 1 as the first embodiment of the present invention is constructed so that three types of buses, that is, the processor bus 111 , the memory bus 112, and the system bus 113 are connected in a three-way manner connection through the three-way connection controller 103 . Thus, for a DMA operation, data is not passed through the process sorbus 111 , and therefore an independent operation of the processor bus 111 and the DMA operation can be performed simultaneously. In addition, since the system bus 113 is not used for processor / main memory access, independent operation of the system bus 113 and processor / main memory access can be accomplished at the same time. With the above arrangements for DMA operation and processor / memory access, maximized usage efficiency can be developed for each of the three types of buses.

Next, an example of an evaluation of the performance of the bus system of the first embodiment of the present invention shown in FIG. 1 and the prior art bus systems shown in FIGS. 2 and 3 will be described together with quantitative characteristics of the effect caused by the first embodiment is developed in accordance with the present invention.

In the bus system of FIGS. 1 to 3 it should be assumed that the processor bus 111 , the memory bus 112 and the system bus 113 have a maximum data throughput of 400, 400 and 200 megabytes per second (MB / s). In addition, it is assumed that the ratio of main memory access to processor bus 111 is 40%, the ratio of the DMA through bus system 113 is 70%, and the maximum bus acquisition ratio or bus acquisition ratio for bus connection controllers 201 and 301 is 50%. Under these conditions, when each of processor bus 111 and system bus 113 is operating at maximum throughput, the performance of each bus system is estimated as follows.

First, in the conventional bus system of FIG. 2, when the system bus 113 tries to operate at the maximum throughput of 200 MB / s, a DMA demand that is equal to 70% of 200 MB / s, ie 140 MB / s, is enabled to be led to the bus connection controller 201 . For bus link controller 201 , the system allows a processor bus acquisition ratio up to 50% of 400 MB / s, namely 200 MB / s. As a result, the DMA demand of 140 MB / s is fully accepted. As a result, although bus system 113 operates at a transfer rate of 200 MB / s, processor bus 111 receiving a DMA request can essentially only operate at a transfer rate of (400-140) = 260 MB / s. In this situation, the processor / main memory access is equipped with a bus acquisition ratio of 40% of 260 MB / s, namely 104 MB / s. As a result, a request for a transfer rate of 140 + 104) = 154 or 244 MB / s is sent to the memory bus 112 , and the request may match the request described above. Briefly, bus usage efficiency for each of the three types of buses in the conventional bus system of FIG. 2 is achieved as follows: 260/400 × 100 = 65% for processor bus 111 , 254/400 × 100 = 63.5% for the memory bus 112 and 200/200 × 100 = 100% for the system bus 113 .

Next, in the prior art bus system shown in FIG. 3, when the processor bus 111 tries to operate at the maximum throughput of 400 MB / s, a main memory access request that is 40% of the throughput, ie 160 MB, is requested / s, is output to the bus connection controller 301 . However, the bus connection controller 301 is allowed to operate the system bus 113 with a throughput of up to 50% of 200 MB / s, namely 100 MB / s. As a result, processor / main memory access is only processed at a transfer rate of up to 100 MB / s. As a result, processor bus 111 can only operate at a transfer rate up to 250 MB / s (100 MB / s corresponds to 40% of 250 MB / s). In addition, the system bus 113 essentially works with a throughput of (200-100) = 100 MB / s in this situation. As a result, the DMA request is issued at a 70% transfer rate of 100 MB / s, ie 70 MB / s. As a result, a request of (100 + 70) = 170 MB / s is generated to the memory bus 112 , which can accept this request as above. In summary, the bus usage efficiency for each of the three types of buses in the conventional bus system of FIG. 3 is obtained as follows, namely: 250/400 × 100 = 62.5% for processor bus 111 , 170/400 × 100 = 42.5% for the memory bus 112 and 100/200 × 100 = 50% for the system bus 113 .

In contrast, in the information processing system shown in FIG. 1 as the first embodiment according to the present invention, when the processor bus 111 tries to operate at a transfer rate of 400 MB / s, a main memory access request is made to the three-way link controller 103 for one transfer rate sent, which is 40% of 400 MB / s, ie 160 MB / s. In addition, when system bus 114 attempts to operate at 200 MB / s throughput, a DMA request for a transfer rate equal to 70% of 200 MB / s, ie 140 MB / s, to the three-way link controller 103 is performed. In response, the three-way connection controller 103 outputs a transfer request to the system bus 112 from which the Prozes sorting / / s includes main memory access request and the DMA request with a resul animal border transfer rate of (160 + 140) = 300 MB. The memory bus 112 can process this request. As a result, the processor bus 111 and the system bus 113 can operate at 400 and 200 MB / s, respectively. This means that the bus use efficiency for each of the three types of buses in the bus system or information server shown in FIG. 1 as the first embodiment of the present invention is obtained as follows, namely: 400/400 × 100 = 100% for processor bus 111 , 300/400 × 100 = 75% for memory bus 112 and 200/200 × 100 = 100% for system bus 113 .

The above results are shown in Table 1 below. As can be seen therein, based on the information processing system of the present invention of FIG. 1, it can be understood that bus use efficiency is maximized for the three types of buses.

table

Incidentally, before a description of an embodiment showing a particular structure of the present invention, information processing systems or bus systems as a second and a third embodiment according to the present invention will be described with reference to FIGS. 7 and 8.

In Figs. 7 and 8 single type processors 701 and 703 and multi-type processors to see 801 1-N, each of these processors may be associated with a single cache memory system. Process sorbuses 711 and 712 connect processors 701 and 703 to a four-way link controller 705 . The four-way connection controller 705 further connects processor buses 711 and 712 , a memory bus 112 and a system bus 113 . In addition, cache memory systems 702 , 704 and 802 are individually connected to processors 701 , 703 and 801 , respectively. In this regard, the devices 105 connected to the system bus 113 are similar to the I / O devices of the previous embodiment.

In the second embodiment of the present invention shown in FIG. 7, four buses, including three types of buses, that is, the two processor buses 711 and 712 , the memory bus 112 and the system bus 113 are connected to form a four-way connection by the four-way connection controller 705 . Processors 701 and 703 are single-type processors to which cache memory systems 702 and 704 can be connected, respectively. As a result, although processors 701 and 703 can directly access individual cache memories 702 and 704, respectively, without using the processor buses, the processor buses cannot be shared between them.

In Fig. 7, four-way link controller 705 establishes link control between four buses, including three types of buses, such that, for example, a connection between processors 701 and 703 is achieved in competition with a DMA operation, or main memory access from processor 701 and system bus access from processor 702 are performed concurrently. With the above arrangements, in this embodiment as well as the previously described embodiment, the bus use efficiency can be increased to the maximum extent for the four buses, including three types of buses.

Fig. 8 is structured as the first embodiment of FIG. 1 with three types of buses including a processor bus 111, a memory bus 112 and the system bus 113, which geverbindung each other in a Dreiwe are connected by a three-way joint controller 103. A single cache memory system 802 can be connected to a multi-type processor 801 . As a result, each processor 801 can access cache memory system 802 without using processor bus 111 . In addition, the processor bus 111 can be used as a shared unit. In addition, in the bus system shown in FIG. 8 as a third embodiment according to the present invention, as in the embodiment in FIG. 1, the above operations are possible, for example, a DMA operation and an independent operation of the processor bus 111 can be achieved simultaneously, or one Main memory access from processor bus 111 can be performed in parallel with an operation of system bus 113 . As a result, as in the first embodiment, the maximum use efficiency of the three buses belonging to three different types can be further developed in this case as well.

Next, concrete embodiments of essential portions of the above-described embodiments according to the present invention will be described with reference to FIGS. 4 to 6. Although a detailed structure of the three-way link controller 103 will be described in detail in connection with the first and third embodiments, respectively, as shown in FIGS. 1 and 8, the four-way link controller 705 of FIG. 7 can also be constructed in a similar manner.

In this connection, Fig. 4 shows the structure of the three-way connection controller 103 , which contains two integrated circuits. In FIG. 4, the three-way connection control 103 is connected to a processor 111, a memory 112 and a system bus 113th These buses each include address buses 411 , 414 and 417 ; Control buses 412 , 415 and 418 ; and data buses 413 , 416 and 419 . In this embodiment, the three-way link controller 102 is constructed with two integrated circuits, that is, a bus memory link controller 401 and a data path switch 402 . However, the three-way connection controller 103 may be constituted by one integrated circuit or many integrated circuits.

Data path switch 402 is arranged to establish a three-way connection between three bus types, including processor data bus 413 , memory data bus 416 and system data bus 419 . The data path switch 402 responds to a data path control signal 420 output by the bus memory link controller 401 to establish connections and disconnections between the three data bus types 413 , 416 and 419 and to control data I / O directions on the buses.

On the other hand, bus memory link controller 401 is connected to processor address bus 411 , processor control bus 412 , system address bus 417, and system control bus 418 to monitor processor bus 111 and system bus 113 states. In addition, bus memory link controller 401 generates signals for spoke wheel address bus 414 and memory control bus 415 , and data path control signal 420 to control main memory 104 and data path switch 402 . The data path control signal 420 will be described in detail later.

The bus memory link controller 401 , in response to a request issued by the processor bus 111 for processor / main memory access, causes the processor bus 111 and the memory bus 112 to cooperate, and then sets the memory bus 113 to an independent operation. Further, when a DMA operation request is issued from the system bus 113 , the bus memory connection controller 401 enables the system bus 113 and the memory bus 112 to perform a cooperative operation and causes the processor bus 111 to achieve an independent operation. In addition, when the processor bus 111 sends an access request to the system bus 113 or when the system bus 113 issues an access request to the processor bus 111 , the bus memory connection controller 401 sets the processor bus 111 and the system bus 113 to cooperate. In addition, if a conflict arises between a request from processor bus 111 and a request from system bus 113 , e.g. For example, if the memory accesses are received therefrom, the bus memory link controller 401 is a function that provides a mediation control, for example, to put one of the buses 111 and 113 in a waiting state.

FIG. 5 is a diagram showing the internal structure of an embodiment of the data path switch 402 shown in FIG. 4. Fig. 5 includes data input / output drivers 507 , 508 and 509 , respectively, which are connected to a processor data bus 413 , a memory data bus 416 and a system data bus 419 ; Data latch circuits or data delay circuits 501 , 502 and 503 ; and data selectors 504 , 505 and 506 . A decoder 510 is arranged in this structure to decode a data path control signal 420 generated by the bus memory link controller 401 to output enable signals 511 , 512 and 513 for the data I / O drivers 507 , 508 and 509 and also off Generate selection signals 514 , 515 and 516 for the data selectors 504 , 505 and 506 .

The data delays 501 , 502 and 503 are arranged to store input data from the processor data bus 413 , the memory data bus 416 and the system data bus 419 therein. The selectors 504 through 506 are used to select data from input data from the two remaining data buses to be supplied to the processor data bus 413 , the memory data bus 416 and the system bus 419 , respectively, thereby providing a control operation as follows. Namely, input data of an arbitrarily selected one of the three types of data buses is output to the buses of other types; alternatively, who led the input data to only one of the other buses. Thus, based on the data path control signal 420, all three types of data buses can be operated in a cooperative manner, or a cooperative operation of two arbitrary types of buses and an independent operation of the other type of bus can be achieved.

Fig. 6 is a diagram showing an embodiment of the inner construction of the on Busspeicherverbindungssteuerung four hundred and first Fig. 6 contains I / O drivers 601 to 604 , delay circuits 605 to 608 , decoding circuits 609 and 610 , coding circuits 611 and 612 , a data allocator or a sequencer 613 , which is constructed with an arithmetic logic unit, a memory control signal generator 616 and a data path control signal generator 617 .

Input signals from a processor address bus 411 , a processor control bus 412 , a system address bus 417 and a system control bus 418 are respectively stored in the delay circuits 605 , 607 , 606 and 608 via the T / O drivers 601 , 602 , 603 and 604 . The addresses entered by two types of buses and thus loaded in delay circuits 605 and 606 are then decoded by decoder circuits 609 and 610, respectively. Results from the decoding operations are processed along with data from delay circuits 607 and 608 , ie, input signals from the two types of control buses 412 and 418 . The coding circuits 611 and 612 encode the associated inputs in order to generate signals which determine the states of the processor bus 111 and the system bus 113 . As a result, the bus memory connection controller 401 can monitor the states of the processor bus 111 and the system bus 113 , respectively.

The thus coded by the decoding circuits 611 and 612 to status signals for the processor bus 111 and the system bus 113 are supplied to the data allocator 613 , which contains an arithmetic logic unit. Depending on the status signals of the two types of buses 111 and 113 , the data allocator 613 calculates matches of the respective buses and determines an operation for the memory bus 112 , whereby code information is generated. The data allocator 613 will be constructed by a general-purpose microprocessor and an exclusive hardware structure.

The code information that is generated by the data allocator 613 is decoded by the decoding circuit 614 , the respective output enable signals 618 to 621 to the I / O drivers 601 to 604 , a selection signal 622 to the selector circuit 615 , a memory control code 623 and a respectively Data path control code signal 624 to memory control signal generator 616 and data path control signal generator 617 and control output signals 625 and 616 , which are respectively sent to processor control bus 612 and system control bus 418 via I / O drivers 602 and 604 , respectively.

The I / O driver 601 responds to a request issued by the system bus 113 for access to the processor bus 111 to output an I / O address to the address bus 411 as received by the system address bus 417 . In addition, the I / O driver 602 provides the processor control bus 412 with a control output signal 625 , which is determined in connection with the processor bus 111 . Ande hand, the I / O driver 603 operates when the processor issues an access request to the system bus 113 111 to the system address bus 417 to send an I / O address from the processor address 411th In addition, the I / O driver 604 outputs a control output signal 626 to the system control bus 418 that is defined in accordance with specifications of the system bus 113 .

The selector circuit 615 receives addresses from the processor address bus 411 and the system address bus 417 such that when access to the memory bus 112 occurs, each of the received addresses is selected to send the selected address to the memory address bus 414 . The memory control signal generator 616 serves as a code conversion circuit so that a memory control code 623 generated by the decoding circuit 614 is converted into a memory control signal required according to the specifications of the memory bus 112 , thereby outputting the resulting signal to the memory control bus 415 , The data path control signal generator 617 also works as a code conversion circuit for converting a data path control codes 614, which is generated by the decode circuit 614 in a data path control signal 420 which is supplied to the data path switch 402 to the resulting signal 420 output.

As described above, the bus memory link controller 401 disposed in the three-way link controller 103 can further develop control operations such as links, disconnections, and wait operations for the three types of buses.

In addition, with reference to FIGS. 9 to 19, execution examples of various data and signals that are processed in the three-way link controller 103 will be described in detail.

Fig. 9 shows an example of relationships between the data path control signal 420 which is output from the Busspeicherverbindungssteuerung 401 to the data path switch 402, release signals 511, 512 and 513 by the decoding circuit 510 for each of the I / O driver 507, 508 and 509 are decoded in connection with the control signal 420 , and selection signals 514 , 515 and 516 for the data selectors 504 , 505 and 506 . In this diagram, the main, sub and read / write fields in the top row show a main unit, a sub unit or a read or write request for data transmission from the main unit to the sub unit. The remaining fields of the top row contain signal names that correspond to signals 511 to 516 of FIG. 5. In particular, DT_CNT in the field on the far right of the row denotes the data path control signal 420 . This signal DT_CNT contains three bits in this embodiment. In an idle state where data is not being transmitted, DT_CNT 40 is set to 0 ("000").

The enable signals (DIR_P, DIR_M and DIR_S) 511 , 512 and 513 are "0" or "1" when the associated I / O drivers 507 , 508 and 509 are in the input or output state, respectively. The selection signal (SEL_P) 514 is set to "0" or "1" when the selector 504 selects the gate of the memory bus 112 or the system bus 113 . Furthermore, the selection signal (SEL_M) 515 is "0" or "1" when the selector 505 selects the gate of the processor bus 111 or the system bus 113 . In addition, the selection signal (SEL_S) 516 is "0" or "1" when the selector 506 selects the gate of the processor bus 111 or the memory bus 112 . According to this diagram, based on DT_CNT 420 input to the decoder 510 of the data path switch 402 , the selectors 504 to 506 and the I / O drivers 507 to 509 in the data path switch 402 can be controlled, thereby establishing three-way connection between the three types controlled by buses.

Subsequently, operations of the three-way joint controller 103 with reference to the configuration diagram of Fig. 19 beschrie ben showing in detail the buses which are connected to the three-way connection controller 103 of FIG. 4 are connected, and the signal timing diagrams of FIGS. 17 and 18.

In these diagrams, the same components as those of Figs. 1 and 4 are designated by the same reference numerals. A main DMA I / O device 1910 and a sub-I / O device 1911 correspond to the devices 105 connected to the system bus 113 . In Fig. 19, a feedback signal (ACK) 1902 is a response signal to a processor 101 and shows confirmation of data or detection of data in the reading or writing operation.

A row address clock signal (RAS) 1903 , a column address clock signal (CAS) 1904 and a write enable signal ( 1905 ) form part of the memory control signals to be sent to the memory control bus 415 of the main memory 104 . The address division multiplex signal (AD_MPX) is an internal signal of the bus memory link controller 401 and is put in a high state or a low state to output a row address and a column address, respectively. A system bus approval signal (S_GNT) 1906 is used to prioritize a bus, that is, to allow an I / O device 1910 that is one of the connected devices 105 and that can be set to a main DMA unit, the system bus 113 to use. As a result, the I / O device 1910 can operate as a main DMA unit. The address / data clock signal (S_STB) 1907 is generated by a system bus main unit. For a DMA access or a processor I / O access, this signal 1907 is output to the DMA main I / O device 1910 or the bus memory connection device 401 . For a read or write operation, the system bus clock signal (S_STB) 1907 is continuously output for a confirmation period of an address or an address and data. System bus sub-notification signal (S_ACK) 1908 is a response signal from the system bus sub-unit. For a DMA access or a processor system I / O access, this signal 1908 is output by the bus memory controller 401 or the sub-I / O device 1911 . The system bus feedback signal (S_ACK) 1908 shows confirmation of the data during a read operation and acquisition of data of a write operation. The signals S_GNT 1906 , S_STB 1907 , S_ACK 1908 and S_READ 1909 , which designate a distinction between a read operation and a write operation, belong to the control output signal 262 to be sent to the system control bus 418 . The system bus address (S_ADD) is fed to the system address bus 417 . Incidentally, the system bus read / write signal (S_READ) 1909 is set to a high (H) state for a read operation.

Fig. 16 shows an embodiment of a state transition of the data allocator 613, which is in the angeodnet Busspeicherverbindungssteuerung four hundred and first In addition, FIGS. 10 to 15 are diagrams showing the signals which are output in a plurality of steps of the state transition of the respective transfer operations, and in each case, with the processor / Hauptspeicherlese-, processor / Hauptspeicherschreib-, processor / Systembusvorrichtungslese- Processor / system bus device write, DMA read and DMA write operations are related. In the diagrams, a small circle (○) denotes confirmation of an associated signal; in addition, "H" and "L" of the signal S_READ 1909 each indicate, for example, a high state and a low state of the signal value. In addition, a swipe associated with a signal name indicates negative logic of the signal.

In Fig. 16, in a step S2 of the processor / system bus device reading related to Fig. 12, there is a waiting operation for data confirmation from the system bus sub-unit. In step S3 of processor / system bus device writing referring to Fig. 13, the system starts a wait operation for a write response. In step S1 of the DMA reading associated with FIG. 14, a wait operation for an S_STB recording is initiated; thereafter, based on a read / write assessment when S_STB is recorded, a decision is made about a transition determination for a subsequent step S2. In addition, in a step S8 of DMA reading and a step S5 of DMA writing, the system starts a wait operation to negate the signal S_STB from the DMA main unit.

In the signal timing diagrams of Figs. 17 and 18 relating to signal transmissions made in accordance with the specifications of Figs. 9 to 16, those items enclosed in parentheses indicate output sources of the respective signals. This means, for example, that (BMCC) determines that the signal from the bus memory connection controller (BMCC) 401 is output; moreover, (I / O) indicates that the main DMA I / O device 1910 or the sub-I / O device 1911 is set as a subunit of processor / system bus I / O access.

In addition, the delay circuits 501 to 502 of the data path switch 402 shown in FIG. 5 are constructed with edge-triggered flip-flops, ie the delay operation of each delay circuit is started on a rising edge of a clock signal (CLK) of FIGS. 17 and 18. In this context, a START signal ( 1901 ) is a transmission start signal; namely, while the start signal is being output, an address is delayed on a rising edge of the clock (CLK), the address being used in a subsequent operation. In addition, a signal M_ADD designates a memory address to be sent to the memory address bus 414 , whereas signals P_Data, M_Data and S_Data indicate data which are led to the processor data bus 413 , the memory data bus 416 and the system data bus 419 , respectively. In addition, signals P_Latch, M_Latch and S_Latch denote data that are loaded in the delay circuits 501 , 502 and 503.

As can be seen from Fig. 16, the step S3 of processor / system bus device writing shown in Fig. 13 includes a cycle of a wait operation to confirm the signal S_ACK. In addition, processor / system bus device reading step S2 of FIG. 12 includes two cycles of a wait operation to acknowledge the S_ACK signal ( 1408 ). In the DMA reading of FIG. 14, step S1 contains a cycle of a waiting operation for confirming the signal S_STB ( 1407 ) and step S3 contains a cycle of a waiting operation for negating the signal S_STB ( 1407 ).

In Fig. 18, the step S1 of DMA writing includes a cycle of a wait operation to confirm the signal S_STB ( 1407 ); however, the wait to negate the signal in step S5 is ended only by performing a wait operation. As indicated above, the operations of bus / memory controller 401 and data path switch 402 of Figs. 4, 5 and 6 have been written in connection with the methods associated with Figs. 9-18 , which is an understanding of the operation of Figs Embodiment of the three-way connection controller 103 shown in FIG. 1 will be helpful.

Although structures and operations of the four-way link controller 705 and the like of FIG. 7 are not described, the structures and operations are easily understood from the description of the structure and operation of the three-way link controller.

Furthermore, although processor bus 111 , memory bus 112, and system bus 113 are each of the address / data separation type in the description given with reference to Figs. 4 to 19, the present invention can of course be applied to address / data multiplex type buses , For example, if processor bus 111 and system bus 113 are of an address / data multiplex type, the system of Figure 4 will be constructed such that processor address bus 411 and processor data bus 413 are structured as one bus; in particular, the system address bus 417 and the system data bus 419 are combined to form a bus. The resulting buses are connected to both the bus / memory controller 401 and the data path switch 402 .

Although the exemplary embodiments according to the basic concept of the have been described, it is to be understood that  various changes and modifications are made can without departing from the present invention.

According to the present invention described in detail above, can be in the bus system that has at least three types of many buses including processor, memory and system buses, while two Types of buses achieve collaboration, the rest of them perform an independent operation, resulting in an effect of a Maximizing the usage efficiency of each bus leads. in the especially in a case where the processor bus with a variety of Processors or cache systems connected, can at the same time tig operations can be advantageously achieved. For example, a DMA operation and data transfer between a plurality of processors or between a processor and a cache system can be the same be reached in time; processor / main memory can also be added handle and data transfer between a variety of devices connected to the system bus at the same time leads.

Claims (44)

1. Information processing system comprising:
a processor ( 101 );
a processor bus ( 111 ) coupled to the processor ( 101 ),
a main memory ( 104 );
a memory bus ( 112 ) coupled to the main memory ( 104 ),
an input / output device ( 105 );
a system bus ( 113 ) coupled to the input / output device ( 105 ), and
a three-way connection controller ( 103 ) for selectively coupling any two of the buses, namely the processor bus ( 111 ), the memory bus ( 112 ) and the system bus ( 113 ), for data communication between these buses, said data communication between any two buses being independent is from a data communication of the remaining processor bus, memory bus or system bus. 2. Information processing system according to claim 1, characterized in that at least one of the buses of processor bus ( 111 ), memory bus ( 112 ) and system bus ( 113 ) is an address / data multiplex type. 3. Information processing system according to claim 2, characterized in that the three-way connection control device ( 103 ) comprises:
a connection control circuit ( 401 ) for outputting a data bus control signal ( 420 ) for selecting a connection mode of any two in response to information from the processor ( 101 ) or the input / output device ( 105 ); and
a data switching circuit ( 402 ) responsive to the data bus control signal ( 420 ) provided by the link control circuit ( 401 ) to couple the two arbitrary buses to be coupled. 4. Information processing system according to one of claims 1, 2 or 3, characterized in that the input / output device ( 105 ) is a control of disk files. 5. Information processing system according to one of claims 1, 2 or 3, characterized in that the input / output device ( 105 ) is a controller for drawing and displaying images. 6. Information processing system according to one of claims 1, 2 or 3, characterized in that the input / output device ( 105 ) is a controller for networks and communication connections. 7. Information processing system according to one of claims 1, 2 or 3, characterized in that each of the buses, namely the processor bus ( 111 ), the memory bus ( 112 ) and the system bus ( 113 ), a data bus, an address bus and a control bus and that the three-way link controller ( 103 ) comprises:
a coupling control circuit for outputting a data bus control signal ( 420 ) for coupling any two in response to information from the processor ( 101 ) or the input / output device ( 105 );
a data switching circuit that responds to the data bus control signal provided by the connection control circuit to couple the data buses of any two buses to be coupled, namely the processor bus, the memory bus and the system bus. 8. Information processing system according to claim 7, characterized in that the data bus and the address bus at least one of the buses of processor bus ( 111 ), memory bus ( 112 ) and system bus ( 113 ) is a multiplex type bus. 9. Information processing system according to claim 1, characterized in that
the three-way link controller ( 103 ) is physically coupled to the processor bus, memory bus and system bus for selectively coupling any two of the buses, processor bus ( 111 ), memory bus ( 112 ) and system bus ( 113 ), for data communication therebetween Buses, regardless of the physical coupling between the three-way connection control device and the remaining processor bus, memory bus or system bus,
wherein the three-way connection controller ( 103 ) selects one of a plurality of connection modes, the connection modes including:
a first operating mode in which the processor bus and the memory bus for data transmission are coupled independently of the system bus,
a second mode in which the memory bus and the system bus are coupled independently of the processor bus for data transmission, and
a third operating mode in which the system bus and the process sorbus for data transmission are coupled independently of the memory bus. 10. Information processing system according to claim 9, characterized in that at least one of the buses of processor bus ( 111 ), memory bus ( 112 ) and system bus ( 113 ) is an address / data multiplex type. 11. Information processing system according to claim 9 or 10, characterized in that the three-way connection device ( 103 ) comprises:
a connection control circuit for outputting a data bus control signal when one of the first, second or third connection mode is selected in response to information from the processor or the input / output device; and
a data switching circuit responsive to the data control signal provided by the link control circuit to couple any two buses to be coupled. 12. Information processing system according to claim 9, 10 or 11, characterized in that the input / output device ( 105 ) is a control of disk files. 13. Information processing system according to claim 9, 10 or 11, characterized in that the input / output device ( 105 ) is a control for drawing and for displaying images. 14. Information processing system according to claim 9, 10 or 11, characterized in that the input / output device ( 105 ) is a control for networks and communication connections. 15. Information processing system according to claim 9, 10 or 11, characterized in that each of the buses, namely the processor bus ( 11 ), the memory bus ( 112 ) and the system bus ( 113 ), has a data bus, an address bus and a control bus, and that the three-way link controller ( 103 ) comprises:
a connection control circuit for outputting a data bus expensive signal ( 420 ) for coupling any two in response to information from the processor ( 101 ) or the input / output device ( 105 );
a data switching circuit that responds to the data bus control signal provided by the connection control circuit to couple the data buses of any two buses to be coupled, namely the processor bus, the memory bus and the system bus. 16. Information processing system according to claim 15, characterized in that the data bus and the address bus at least one of the buses of processor bus ( 111 ), memory bus ( 112 ) and system bus ( 113 ) are a multiplex type bus. 17. Information processing system according to claim 1, characterized in that the processor bus ( 111 ) has a data bus ( 413 ), an address bus ( 414 ) and a control bus ( 415 );
that the system bus ( 113 ) has a data bus ( 419 ), an address bus ( 417 ) and a control bus ( 418 ) to enable coupling of at least two connected input / output devices to enable transmission from one of the connected input / output devices enable directions to another of the connected input / output devices if the two input / output devices are coupled to the system bus; and
that the three-way connection control device ( 103 ) is physically separately coupled to the processor bus, the memory bus and the system bus,
wherein the three-way connection controller selects one of a plurality of connection modes, the connection modes including:
a first operating mode in which the processor bus and the memory bus are coupled and the system bus is separated from the process sorbus and the memory bus,
a second mode in which the memory bus and the Sy stembus is coupled, and
a third operating mode in which the system bus and the process sorbus are coupled. 18. Information processing system according to claim 17, characterized in that at least one of the buses of processor bus ( 111 ), memory bus ( 112 ) and system bus ( 113 ) is an address / data multiplex type. 19. Information processing system according to claim 18, characterized in that the three-way connection device ( 103 ) comprises:
a connection control circuit ( 401 ) for outputting a data bus control signal ( 420 ) for selecting a connection mode of any two in response to information from the processor ( 101 ) or the input / output device ( 105 ); and
a data switch circuit ( 402 ) responsive to the data bus control signal ( 420 ) provided by the link control circuit ( 401 ) to couple any two buses to be coupled. 20. Information processing system according to claim 19, characterized in that the input / output device ( 105 ) is a control of disk files. 21. Information processing system according to claim 17 or 18, characterized in that the input / output device ( 105 ) is a control for drawing and for displaying images. 22. Information processing system according to claim 17 or 18, characterized in that the input / output device ( 105 ) is a control for networks and communication connections. 23. Information processing system according to claim 17 or 18, characterized in that the three-way connection control device ( 103 ) comprises:
a connection control circuit for outputting a data bus expensive signal ( 420 ) for coupling any two buses in response to information from the processor ( 111 ) or the input / output device ( 105 );
a data switching circuit that responds to the data bus control signal provided by the connection control circuit to couple the data buses of any two buses to be coupled, namely the processor bus, the memory bus and the system bus. 24. Information processing system according to claim 1, characterized in that
at least one further input / output device ( 105 ) is provided,
the system bus ( 113 ) is coupled to the at least two input / output devices ( 105 ) to enable coupling of the two connected input / output devices in order to transmit from one of the connected input / output devices to another of the enable connected input / output devices when the two input / output devices are coupled to the system bus ( 113 ); and
the three-way connection control device ( 103 ) is adapted to control the coupling of any two of the buses, namely the processor bus ( 111 ), the memory bus ( 112 ) and the system bus ( 113 ), the connection control device being physically separate from the processor bus, the memory bus and the System bus is coupled,
wherein the three-way connection controller selects one of a plurality of connection modes, the connection modes including:
a first mode of operation in which the processor bus and the memory bus are coupled, the system bus being separate from the processor bus and the memory bus, and the two input / output devices transmitting data over the system bus;
a second mode in which the memory bus and the Sy stembus are coupled; and
a third operating mode in which the system bus and the process sorbus are coupled. 25. Information processing system according to claim 24, characterized in that at least one of the buses of processor bus ( 111 ), memory bus ( 112 ) and system bus ( 113 ) is an address / data multiplex type. 26. Information processing system according to claim 25, characterized in that the three-way connection device ( 103 ) comprises:
a connection control circuit ( 401 ) for outputting a data bus control signal ( 420 ) for selecting a connection mode of any two in response to information from the processor ( 111 ) or one of the at least two input / output devices ( 105 ); and
a data switch circuit ( 402 ) responsive to the data bus control signal ( 420 ) provided by the link control circuit ( 401 ) to couple any two buses to be coupled. 27. Information processing system according to claim 24, 25 or 26, characterized in that one of the at least two input / output devices ( 105 ) is a control of disk files. 28. Information processing system according to claim 24, 25 or 26, characterized in that one of the at least two input / output devices ( 105 ) is a controller for drawing and displaying images. 29. Information processing system according to claim 24, 25 or 26, characterized in that one of the at least two input / output devices ( 105 ) is a controller for networks and communications connections. 30. Information processing system according to claim 24, 25 or 26, characterized in that each of the buses, namely the processor bus. the memory bus and the system bus having a data bus, an address bus and a control bus, and that the three-way connection control device ( 103 ) comprises:
a connection control circuit for outputting a data bus control signal ( 420 ) for coupling any two buses in response to information from the processor ( 101 ) or one of the at least two input / output devices ( 105 );
a data switching circuit that responds to the data bus control signal provided by the connection control circuit to couple the data buses of any two buses to be coupled, namely the processor bus, the memory bus and the system bus. 31. Information processing system according to claim 1, characterized in that
at least one further processor ( 101 ) is provided, the processor bus ( 111 ) being coupled to both processors ( 101 );
at least one further input / output device ( 105 ) is provided;
the system bus ( 113 ) is coupled to the input / output devices ( 105 ) in order to enable a connection between the input / output devices to enable a transfer from one of the connected input / output devices to another of the connected input devices. / Enable output devices if one and the other of the connected input / output devices are coupled to the system bus; and
the three-way connection control device ( 103 ) is designed to control the coupling of any two of the buses, namely the processor bus ( 111 ), the memory bus ( 112 ) and the system bus ( 113 ), the connection control device being physically separate from the processor bus, the memory bus and the System bus is coupled;
wherein the three-way connection controller ( 103 ) selects one of a plurality of connection modes, the connection modes including:
a first operating mode in which the processor bus and the memory bus are coupled, the system bus being separated from the processor bus and the memory bus,
a second mode in which the memory bus and the Sy stembus are coupled, and
a third operating mode in which the system bus and the process sorbus are coupled. 32. Information processing system according to claim 31, characterized in that at least one of the buses of processor bus ( 111 ), memory bus ( 112 ) and system bus ( 113 ) is an address / data multiplex type. 33. Information processing system according to claim 32, characterized in that the three-way connection device ( 103 ) comprises:
a connection control circuit ( 401 ) for outputting a data bus control signal ( 420 ) for selecting a connection mode of any two in response to information from the processor ( 101 ) or the input / output device ( 105 ); and
to any of the two coupling a data switching circuit (420) responsive to the Datenbussteue approximate signal (420), which is wiring of the call control (401) provided to be coupled to buses. 34. Information processing system according to claim 31, 32 or 33, characterized in that the input / output device ( 105 ) is a control of disk files. 35. Information processing system according to claim 31, 32 or 33, characterized in that the input / output device ( 105 ) is a control for drawing and for displaying images. 36. Information processing system according to claim 31, 32 or 33, characterized in that the input / output device ( 105 ) is a control for networks and communication connections. 37. Information processing system according to claim 31, 32 or 33, characterized in that the three-way connection device ( 103 ) comprises:
a connection control circuit for outputting a data bus control signal ( 420 ) for coupling any two in response to information from the processor ( 101 ) or the input / output device ( 105 ); and
a data switching circuit that responds to the data bus control signal provided by the connection control circuit to couple the data buses of any two buses to be coupled, namely the processor bus, the memory bus and the system bus. 38. Information processing system according to claim 1, characterized in that a cache memory ( 102 ) is provided;
the processor bus ( 111 ) is coupled to the processor ( 101 ) and the cache memory ( 102 );
at least one further input / output device ( 105 ) is provided, the system bus ( 113 ) is coupled to the input / output device ( 105 ), the system bus comprising a data bus ( 419 ), an address bus ( 417 ) and a control bus ( 418 ) has to enable a coupling of at least two connected input / output devices, in order to enable a transfer from one connected input / output device to another connected input / output device if one and the other of the at least two connected Input / output devices are coupled to the system bus; and
the three-way connection control device ( 103 ) is adapted to control the coupling of any two of the buses, namely the processor bus ( 111 ), the memory bus ( 112 ) and the system bus ( 113 ), and this device is physically separate from the process sorbus, the memory bus and the system bus is coupled;
wherein the three-way connection controller selects one of a plurality of connection modes, the connection modes including:
a first operating mode in which the processor bus and the memory bus are coupled, the system bus being separated from the processor bus and the memory bus;
a second mode in which the memory bus and the Sy stembus are coupled; and
a third operating mode in which the system bus and the process sorbus are coupled. 39. Information processing system according to claim 38, characterized in that at least one of the buses of processor bus ( 111 ), memory bus ( 112 ) and system bus ( 113 ) is an address / data multiplex type. 40. Information processing system according to claim 39, characterized in that the three-way connection control device ( 103 ) has:
a connection control circuit ( 401 ) for outputting a data bus control signal ( 420 ) for selecting a connection mode of any two in response to information from the processor ( 101 ) or the input / output device ( 105 ); and
a data switch circuit ( 402 ) responsive to the data bus control signal ( 420 ) provided by the link control circuit ( 401 ) to couple any two buses to be coupled. 41. Information processing system according to claim 38, 39 or 40, characterized in that the input / output device ( 105 ) is a control of disk files. 42. Information processing system according to claim 38, 39 or 40, characterized in that the input / output device ( 105 ) is a control for drawing and for displaying images. 43. Information processing system according to claim 38, 39 or 40, characterized in that the input / output device ( 105 ) is a control for networks and communication connections. 44. Information processing system according to claim 38, 39 or 40, characterized in that each of the buses, namely the processor bus, the memory bus and the system bus, has a data bus, an address bus and a control bus, and that the three-way connection device ( 103 ) comprises:
a connection control circuit for outputting a data bus control signal ( 420 ) for coupling any two in response to information from the processor ( 101 ) or the input / output device ( 105 );
a data switching circuit that responds to the data bus control signal provided by the connection control circuit to couple the data buses of any two buses to be coupled, namely the processor bus, the memory bus and the system bus.