DE4136729A1 - Cache control unit for fault tolerant computer system - Google Patents

Abstract

A fault tolerant computer system operates with a cache memory control unit in which there is a stack memory (25) that has a FIFO structure. The memory connects to a control module (23). Address and control lines (7,8) provide a link between a microprocessor (1), a characteristic memory (21), a comparator (22), a bus monitor (24), a cache memory (3), an interface (4) and the stack memory. The input addresses for a cache block are held in the stack memory. Information is read and is subjected to a comparison process before being written back into the memory.

Description

The invention relates to cache control direction for a multiprocessor fault tolerance ranzcomputer or the like is used in which each processor has a back cache spelling type, and still refers to a fault tolerance computer and a data transfer system stem in fault tolerance at the time of the cache flush computer.

Fig. 15 shows a cache controller of the type mentioned above according to the prior art. The figure is in the article "You will be familiar with 32-bit microproccor cache", "Yokota, Nikkei Electronics", No. 434, pages 159 to 174, November 16, 1987 represents Darge. With reference to the figure, 1 is a microprocessor, 2 is a cache control device, 3 is a cache memory, 4 is an interface circuit, 5 is a system bus, 6 is main memory, 7 is an address line, 8 is a data line and 9 is a Control line designated. The cache control device 2 comprises a tag memory 21 , a comparator 22 , a control unit 23 and a bus monitor 24 .

The microprocessor 1 , the identifier memory 21 , the comparator 22 , the bus monitor 24 , the cache memory 3 and the interface circuit 4 are connected to one another via the address line 7 . The microprocessor 1 , the cache memory 3 and the interface circuit 4 are also connected to one another via the data line 8 . The microprocessor 1 , the control unit 23, the bus monitor 24 , the cache memory 3 and the interface 4 are connected to one another via the control line 9 . Furthermore, the control unit 23 , the identification memory 21 , the control unit 23 and the cache memory 3 are each connected to one another by the control lines 9 a and 9 b. The system bus 5 and the bus monitor 24 are directly connected to each other by the address line 7 a and the control line 9 c, ie not via the interface circuit 4 . The memory 21 and the comparator 22 are miteinan on the address line 7 c and the control unit 23 and the bus monitor 24 are connected to each other via the address line 7 d.

The mode of operation is described below. The microprocessor 1 delivers an access request for the main memory 6 to the label memory 21 and the comparator 22 . In the label memory 21 , addresses for the data in the cache memory 3 and the type of data indicating bits (such as effectiveness and change) are kept for each cache block.

A description will be given with reference to FIG. 16 in the case that the request of the microprocessor 1 is a read request. First, a check is made to see if the requested data is in the cache 3 ( 1601 ). If there is an address matching the tag memory 21 , the valid bits of the cache block are checked ( 1608 ). When the valid bit of the cache block containing the data is in the "ON state", the data is read out from the cache memory 3 ( 1607 ). When the valid bit of the cache block is "OFF", the newest value is read out from main memory 6 or another module ( 1606 ) and data is also supplied to microprocessor 1 ( 1607 ). If no entry to cache memory 3 has been found in the meantime, a check is made as to whether a vacant block is provided in cache memory 3 or not ( 1602 ). If a vacant block is present, the block having the data necessary for the block is read out ( 1606 ) and the data are supplied to the microprocessor 1 ( 1607 ). If there is no vacant block, a spare block is selected ( 1603 ) and the modified bit of the selected cache block is checked ( 1604 ). If the modified bit is "ON", the associated cache block is written back to main memory 6 ( 1605 ). Then the block that has the data required for the write-back cache block is read out ( 1606 ) and it is also the data supplied to the microprocessor 1 ( 1607 ). When the modified bit in the spare block is "OFF", the data required for the block is read out from main memory 6 or a different module ( 1606 ) and data is also supplied to microprocessor 1 ( 1607 ).

Next, a description will be given below with reference to Fig. 17 in the event that a request provided by the microprocessor 1 is a write request. First, a check is made to see if the request data is in cache memory 3 ( 1701 ). If there is an address matching the tag memory 21 , the valid bit of this cache block is checked ( 1709 ). If the valid bit of the data block of the cache block is "ON", a modified bit of the cache block is checked ( 1710 ). If the modified bit is also "ON", the microprocessor 1 writes data to the cache block ( 1708 ). If the valid bit of the cache block is "ON" and the modified bit is "OFF", the modified bit in the cache block is set to "ON" ( 1707 ) and data is also written to cache memory 3 ( 1708 ). If the valid bit of the matching cache block is "OFF", a newest value is read from main memory 6 or a different module into the cache block ( 1706 ) and after the modified bit is set to "ON" ( 1707 ) , are written to the data ( 1708 ). If there is no entry into cache 3 , a check is made to see if there is a vacant block in cache 3 ( 1702 ). If there is a vacant block, a block having the data required for the block is read out ( 1706 ) and after the modified bit is set to "ON" ( 1707 ), the data is written ( 1708 ). If there is no vacant block, a spare block is selected ( 1703 ) and the modified bit of the selected spare block is checked ( 1704 ). If the modified bit is "ON", this block is written back to main memory 6 (1705 ). Then a block containing the data required for the write back block is read out ( 1706 ) and after the modified bit is set to "ON" ( 1707 ), the data is written ( 1708 ). In the event that the modified bit of the spare block is set to "OFF", the data required for this block are read out from the main memory or a different module ( 1706 ) and after the modified bit is set to "ON" ( 1707 ), the data is written ( 1708 ).

The bus monitor 24 comprises an internal number plate memory which is adapted to the number plate memory 21 . The operation of other microprocessors on the system bus 5 is monitored. If a bus cycle is determined on the basis of a read error, a write hit or a write error, the relevant address is compared with the content of the internal identifier memory.

If, in the event of a read error, the tag memory corresponds to the address and the valid and modified bits are each "ON", the cache controller supplies data to the module requesting the cache block and / or the main memory 6 and then the modified bit is set to "OFF". If the modified bit is "OFF", the cache controller does no operation.

If in the case of a writing hit the license plate If the address matches, the valid bit this cache block is set to "OFF".

If, in the case of a typing error, the indicator memory corresponds to the address and the valid and  the modified bit is "ON" as in the case of the Reading error, data is provided and then is the "ON" valid bit of the block is set to "OFF".

In the above situations, when an updated block is replaced and the updated data is referenced by a different microprocessor, a restore point is set. The term "recovery point" means a point to which the routine or program goes back to restore and restart the process in cases where an error occurs in the microprocessor 1 during processing. At the restore point, the control unit 23 checks all modified bits of the tag memory 21 and all the updated cache blocks in the cache memory 3 are written back to the main memory 6 (what is referred to as a "cache flush"). When the write back is complete, the modified bits of the cache block are set to "OFF".

Fig. 18 shows a block diagram of an arrangement of a fault tolerance computer according to the prior art, as described in US Pat. No. 4,819,154. In the illustration, 1801 shows the same processor module including a processor for executing a user and a supervisor program, 1802 denotes a system bus which is designed twice to increase reliability and throughput, and 1803 denotes a memory module for storing the Program / data of the user / supervisor. Although it is sufficient to run the system bus 1802 as a single bus, it is arranged twice to prevent an operation stop of the entire system due to difficulties in the bus and thereby to improve the system throughput. Although only shown as one line in FIG. 18, system bus 1802 is designed as a multi-wire bus, comprising a number of data and signal lines. The data to be stored in the memory module are stored as countermeasures against errors in two physically different memory modules.

Fig. 19 shows in more detail the arrangement of the Prozes sormoduls. In the illustration, 1901 shows a memory organization unit for converting a virtual address into a physical address, 1902 denotes a processor for implementing user / supervisor programs, 1903 denotes a local address bus, 1904 denotes a local data bus, 1905 denotes a bus adapter for Checking the parity of the data from the cache to the local data bus to generate byte parity with respect to the data from the local data bus to the cache, 1906 is a cache address bus. Furthermore, in 1907 an internal sequencer, 1908 a cache memory that is not of the "write-through" type (ie, a write-back memory), 1909 a cache data bus, 1910 a block state memory (block-state) memory) (of a construction similar to the tag memory 21 of FIG. 15 has), 1911 is an external sequence controller 1912 be characterized a data bus and 1913 denotes a Sy stembus interface. The processor module always has the same structure and is handled in a similar way.

Fig. 20 is an illustration of a more detailed Anord voltage of the memory module. 2001 designate a system bus interface, 2002 an internal address bus, 2003 coding / decoding devices, 2004 a sequence control unit for generating a control signal and a synchronous signal for the sequence of the memory module, 2005 an address acquisition / generation device for decoding addresses to the address to be recorded, for which the corresponding memory module is responsible, in 2006 a RAM time / control unit for producing a row address, a column address and a chip select signal and in 2007 a RAM field.

The description of the operation is explained below. The memory access request from processor 1902 is processed in internal control unit 1907 . Internal control unit 1907 checks, with reference to block state memory 1910 , whether or not the requested data is present in cache memory 1908 . In the event that the processor 1902 request is a read request and the requested data is in the cache memory 1908 , the data is provided directly from the cache memory 1908 to the processor 1902 . In the event that the requested data is not in the cache memory 1908 or the data is invalid, after the address conversion has been performed in the memory handling unit 1901 , the address is via the external sequencer 1911 and the system bus interface 1913 transferred to the memory module. The memory module is responsible for the transfer of the cache block including the requested data. The transferred cache block is fed to processor 1902 and stored in cache memory 1908 at the same time.

It is assumed that the processor 1902 request is a write request and that the requested data is in the cache 1908 . In the event that the cache block including the data has already been updated, the write operation is carried out immediately. On the other hand, in the event that the cache block has not been updated, the bit in block state memory 1910 that corresponds to the cache block and that indicates that the update or update is being performed is changed before the write operation is performed. In cases where the requested data is not in the cache memory 1908 or the data is invalid, the address is supplied to the memory module via the system bus interface 1913 after the address conversion in the memory handling unit 1911 . The memory module is responsible for the transfer of the block including the requested data. The data block to be fed is updated after being fed to the processor 1902 and then written to the cache memory 1908 . At this time, the block state memory 1910 is also updated.

Because the prior art device includes a cache memory 1908 that is not of the write-through type (ie, that of the write-back type), the data in the cache memory does not always coincide with the data from the memory module. In addition, as a recovery countermeasure against the occurrence of errors, a method is selected in which the state that the system is operating normally is maintained, with reference to this as a recovery point, so that the method depends on the last recovery point in the memory module is switched on again when the error occurs. Thus, in the event that the recovery point is set, it is necessary that the processor's internal register information be written to the cache and that all cache blocks that have been updated locally in the cache must be written to the Memory module are written, which is hereinafter referred to as "cache flush", so that the cache memory matches the data with the memory module. In the prior art device, in accordance with the "overflow" in context and in the cache, the occurrence of the "overflow" is determined to perform the cache flush operation.

The operation performed at the time of the cache flush will be described with reference to FIG. 21. In response to the occurrence of the cache flush, processor 1902 starts the cache flush operation with respect to internal sequencer 1908 . The internal control unit 1908 calls at each input of the frame status memory 1910 bits, which is responsible for whether the cache block aktuali is Siert or not (2101), and checks it by means of the comparator in the internal sequence controller 1908 (2102). If the modified bit is "ON", the data block corresponding to this input is retrieved from the cache memory 1908 ( 2103 ) and transmitted to the memory module ( 2104 ) via the system bus interface ( 1913 ). After the transfer, the flush address is incremented ( 2105 ) to be compared to the termination address ( 2106 ). If the completion address is not exceeded, the flow of operations returns to process 2101 to go through the process steps. If the modified bit of the cache block is "OFF", the flush address is incremented ( 2105 ). If it does not exceed the termination address, the flow of operations returns to process 2101 to repeat the processes.

In the prior art device, the above-mentioned cache flush operation is performed in unity with the duplicated memory modules. The cache flush operation is carried out twice, so that correct data is always displayed in one of the memory modules. First, the cache flush operation is performed with reference to one of the memory modules. In the cache flush operation, the cache block is written directly into the RAM field 2007 via the system bus interface 2001 or the coding / decoding device 2003 . In the system bus interface 2001 or the coding / decoding device 2003 , the parity check, the error detection and the correction process are carried out with respect to the data block. If the first cache flush succeeds, the cache flush is performed on other memory modules.

If the second cache flush operation normally is finished, the processor module carries out the process the cache flush again. If a mistake in the the first cache flush operation occurs, the pro eat up from the latest restore point taken that earlier in the other memory module was arrested. For this recovery ko the memory module in which the error occurred ten is the content of a memory module. In  Answer to one in the second cache flush opera The process will implement errors that occur tated using the data in the storage mo dul, which is updated by the first cache flush were. In the event that an error occurs during the second Cache flush occurs, a memory area for a different memory module reassigned and the content will be in this area again manufacturing copied.

If so with a cache controller the structure described above according to the state of the Technique a recovery point is set it is necessary to recover the Indicator of the cache addresses for writing back all updated cache blocks in the cache memory to perform. Consequently, the processing takes writing back all updated cache Blocks, i.e. H. the cache flush process, a long time a.

Because in a similar way the fault tolerance computer according to the prior art as described above is ordered so that all of the updated cache Blocks in the cache memory to the memory module to star the cache flush operation ten, it is necessary to update the cache block search by all inputs of the block state memory chers can be called, creating a long time for the cache flush operation is needed.

In addition, in the device according to the prior art Technique the setting interval of the recovery points is unspecified, there is a difficulty the time it takes for the process to start again  manufacture after finding an error such as that is called, and thus a real-time operation to adhere to.

Furthermore, it is in a device according to the prior art technology necessary to transfer data from the cache Store twice in the cache flush operation as they transfer to the two memory modules gen, and so there is the problem that the Bus load is increased, the performance system is sacrificed.

In addition, in the device according to the prior art of technology all in the cache flush operation transferred cache blocks to the memory module it is necessary to repeat the trans carry out each cache block and thus there is a problem that the system bus load is increased, increasing system performance is sacrificed.

The present invention is therefore the object based on solving the above problems and a ca che control device to provide a cache Allows flush high speed.

Another object of the present invention is it, the cache flush operation at high speed ability to perform a fault tolerance computer to get with a real time function.

Another object of the present invention is it to provide a data transfer system that in the Is able to reduce the system bus load at the time of the cache Reduce flush surgery.  

According to the present invention, a ca che control device provided a memory device for storing the input address of a updated cache blocks and a controller device that causes the input address of the updated cache block in memory direction is registered and the beyond affects the cache flush transfer with respect to the registered entry address with reference to the Storage facility at the time of the cache flush Surgery is performed.

In addition, according to the invention, a pro provided a fault tolerance computer, the one storage device for storing the on starting address of the updated cache block and a Control device for registering the input addresses the updated cache block in memory direction and continue to transfer the cache Blocks corresponding to all the registered input addresses with reference to the storage device in the cache flush operation.

In addition, there is a timer for counting the elapsed time and the number of updated Cache blocks provided for recovery point, and there is also a bus monitor provided for monitoring the system bus.

In addition, according to the invention Memory module of a fault tolerance computer vorese hen, which consists of a communication device, which are duplicated in the same physical storage space is a communication between two storage mo dulen and one for each memory module  Buffer memory and a control device for control buffers and communication direction.

It is also necessary to perform a cache flush ope ration at high speed according to the Invention provided a data transfer system that a cache flush information facility, the In structures relating to all memory modules that in turn, a preparation for the reception of the Ca hit flush, a cache block transfer facility device to transfer the address and data every cache block and for continuous execution transfer of all updated cache blocks and a response device which receives the The cache block from the last stored memory returns module to the processor module.

In the cache control unit according to the present Er the control unit registers the input addresses of the updated cache blocks in the memory chereinrichtung, such as a stack cher, and when the cache block is executed, d. H. when all updated cache blocks are returned are written, the control device refers on the storage device to do the input address that was written back in a short time should be preserved.

Similarly, stores and registers in the Fault tolerance computers as described above Control device the input address of the cache Blocks in the storage device to originally at the time of the processor write operation write and reads the registered input address  from the storage device in the cache flush, those for setting the restore point is necessary in order to find the appropriate cache block to transfer to the memory module.

Furthermore, the setting or setting of the how the manufacturing point in response to production the interruption to the processor started under the condition occurs that the control device of the Cache determines that the number of cache Blocks that are not in the respective cache lines of the cache are updated reach the agreed value, whereby the counter determines that the total number of updated cache Blocks in the cache a predetermined value reach, and the bus monitoring circuit determines that a different processor module over the System bus to the locally updated cache block in refers to the cache, or where the time circuit detects that one of the previously mentioned Findings within a predetermined period of time it was not carried out.

The buffer memory stores in the two memory modules intermittently the cache block received and after the tax receipt confirms the completion of the receipt direction the state for the synchronization between the two memory modules to get data from the buffer memory to the RAM field via the communication device write.

Additionally informs in response to the instruct cache flush from the processor the cache flush Information device all memory modules that the Cache flush is started, and the cache block over  carrying device continuously transmits the data and the address of the cache block with respect to all updated cache blocks. Furthermore the reply device only makes the reply from the memory module effective by the data end Lich be written into the RAM field.

The above and other tasks, features and advantages the invention will become apparent from the following description still evident in connection with the drawings licher. Show it

Fig. 1 is a block diagram of an arrangement dung a cache control device according to an embodiment of OF INVENTION,

FIG. 2 is a flowchart illustrating the operation of the embodiment of FIG. 1 at the time of writing data.

Fig. 3 is a block diagram showing an arrangement of a fault tolerant computer accordingly to an embodiment of the present invention,

Fig. 4 is a block diagram of a detaillier th arrangement of a processor module according to FIG. 3,

Fig. 5 is a diagram for describing the signal states between the system bus interface and the system bus,

Fig. 6 is a block circuit diagram showing a detailed arrangement of profiled doubled SpeI chermodulen of FIG. 3 represents

Fig. 7 is a flowchart illustrating the Betriebswei se of the embodiment of Fig. 4, the Runaway in response to the reading request of the processor executes,

FIG. 8 is a flowchart showing the operation of the embodiment of FIG. 4 performed in response to the processor write request.

Fig. 9 is a flowchart showing the Betriebswei se of the embodiment of Fig. 4, the gene or adjusting the restore is performed at the time of Festle mount point,

Fig. 10 is a flowchart indicative of the cache flush operation in the embodiment according to Fig. 4,

Fig. 11 is an illustration of the signal flow of the embodiment of Fig. 3 at the time of the cache flush operation,

Fig. 12 is an illustration of signal flows of the embodiment of Fig. 3 at the time of the cache block transfers,

Fig. 13 is a representation of the time sequence of signals in an embodiment according to Fig. 3,

Fig. 14 is an illustration of the distributed Erwi alteration operation in the execution example according to Fig. 3,

Fig. 15 is a block diagram showing the arrangement of a case-control device according to the prior art,

Fig. 16 is a flow chart means the operation of the cache control shown in Fig. 15 according to the prior art at the time of reading data representing,

Fig. 17 is a flowchart representing the operation of the cache controller according to the prior art at the time of writing data,

Fig. 18 shows an arrangement of a fault tolerant computer according to the prior art,

Fig. 19 shows a detailed arrangement of a Pro zessormoduls, in the computer of FIG. 18

Fig. 20 shows a detailed arrangement of a memory module in the computer of FIG. 18,

FIG. 21 is a flow diagram illustrating the cache flush operation in the computer of FIG. 18; and

Fig. 22 is an illustration of the coordinates Zvi rule the main memory and the cache memory.

FIG. 1 shows a block diagram of an arrangement of a cache control device according to an exemplary embodiment of the present invention, parts 1 to 9 and 21 to 24 being similar to those of the cache control device according to the prior art corresponding to FIG. 15.

25 1, a stack is shown in FIG. Marked net which is formed by a FIFO (First-In First-Out). The stack corresponds to the storage device in the present invention. The stack 25 and the control unit 23 are connected to each other by the line 9 d. This control unit 23 realizes the control device in the present invention. A microprocessor 1 , a label memory 21 , a comparator 22 , a bus monitor 24 , a cache memory 3 , an interface 4 and the stack 25 are connected to each other by the address line 7 .

The mode of operation is described below.

The mode of operation is the same as in the arrangement according to the prior art, insofar as it relates to the read request of the microprocessor 1 (see FIG. 16).

In the event that a request provided by the microprocessor 1 is a read request, it will now be described with reference to FIG. 2. First, a check is made to see if the request data is in the cache memory 3 (step 201 ) or not. If there is an address coinciding with the tag memory 21 , valid bits of this cache block are checked ( 210 ). If there is an "ON" valid bit of the cache block containing this data, modified bits of this cache block are checked (step 211 ). If there is an "ON" modified bit, the microprocessor 1 writes data to this cache block (step 209 ). If there is an "ON" valid bit of the cache block and also an "OFF" modified bit, the modified bit of this cache block is set to "ON" (step 207 ) and it also becomes the input address of this cache block registered in the stack 25 ( 208 ). Furthermore, data is written into the cache memory 3 (step 209 ). If valid bits of the pas send cache block are "OFF", the latest value is read from main memory 6 or a different module into the same cache block (step 206 ), a modified bit is set to "ON" (step 207 ) and the entry address is registered in the stack 25 (step 208 ). Then the data is written (step 209 ). If there is no entry into cache 3 , a check is made to see if there is a vacant block in cache 3 (step 202 ). If an unoccupied block is present, a block containing data required for this block is read out (step 206 ), a modified bit is set to "ON" (step 207 ) and an input is registered in the stack memory 25 (step 208 ) . Then the data is written (step 209 ). If there is no vacant block, a spare block is selected (step 203 ) and modified bits of the selected spare block are checked (step 204 ). If there is a "ON" modified bit, this block is written back to main memory 6 (step 205 ). Then, a block containing data required for the restored block is read out (step 206 ), a modified bit is set to "ON" (step 207 ), and an input address is registered in the stack memory 25 (step 208 ). Then the data is written (step 209 ). If the modified bits of the spare block are "OFF", the data requested for that block is read out from the main memory 6 or another module (step 206 ), a modified bit is set to "ON" (step 207 ) and then one Entry address registered in the stack 25 (step 208 ). Then the data is written (step 209 ). It has been described that steps 201 through 209 occur in succession. However, it is possible to provide such parallel processing that a modified bit to "ON" (step 207 ) is performed concurrently with the storage of an input address in the stack 25 to be written into the cache block.

The operation of the bus monitor 24 is the same as that in the prior art structure.

As in the prior art design, a restore point or recovery point is set when an updated cache is replaced and when updated data is referenced by another microprocessor. At the restore point, the control unit 23 effects a write-back of only input addresses of the cache blocks registered in the stack 25 with reference to the stack 25 . In this case, in a prior art structure, it was necessary to recover cache address flags once. With the vorlie invention, however, this is unnecessary and thus the time required for a "cache flush" is greatly reduced.

Although the FIFO memory is used for the stack memory 25 in the above exemplary embodiment, a static memory can also be provided.

Fig. 3 shows an arrangement of a fault tolerance Com puter according to the present invention. In the illustration, 301 denotes a processor module, 303 a memory module and 302 is a system bus for their use. The processor module or processor block 301 is constructed with M × N (M and N are integers equal to 1 or more than 1). Backup (backup arrangements) comprising M running systems and N replacement (backup) systems. The processor module from the replacement system follows the interrupt process in the event that the processor of the running system fails. The processor modules have the same structure regardless of whether they are in the running system or in the replacement system. Although it is sufficient for the system operation to be constructed as a single bus, the system bus 302 has a double arrangement to prevent the operation of the entire system from being stopped due to difficulties in the bus. Although shown in FIG. 3, the system 302 only as a single line, it consists of an address / data bus, a synchronization bus and a control bus. The address / data bus is a bus which consists of a plurality of signal lines for the transmission of addresses which designate the memory addresses for storing the data and also for transmitting the data to be stored in this address. The synchronization bus is used to transmit a quit signal to provide the synchronization of the addresses and the data transfer, and includes address transfer synchronization AS *, AK *, AI * and data transfer synchronization DS *, DK *, DI * (* designated a negative logic signal). The control bus is for routing the addresses, data and necessary information different from the synchronizing signal, and includes CT * for providing the information of the cache flush bus operation, BS * for providing the information that it is impossible to carry out the request process because one of the memory modules is in a different operation, EB * for indicating the last data transfer of the data of a cache block and IR *, a memory module that is in operation invalidating the response in with respect to the other memory module that generates the response indicating completion of the process for data transfer from the FIFO memory to the RAM array. These buses are coupled to the processor / memory modules via the bus interface. Although the system bus is duplicated in this embodiment, these two buses are arranged to perform the same operation, and therefore the following description is given only with reference to one bus.

The memory module 303 is double, so that it comprises a master and a slave (main and secondary storage), the same amount of physical memory (in Fig. 3, 303 a, 303 b and 303 c, 303 d) and which are arranged on physically different carriers so that they can be used for a large number of processor modules.

Fig. 4 shows a detailed arrangement of a processor module, the reference numerals 1902 , 1908 , 1910 and 1913 representing the same parts as in the device according to the prior art. In the figure, 401 is a stack (storage device), which consists, for example, of a FIFO (First-In First-Out), 402 a counter for counting the number of updated cache blocks in the cache memory 1908 , and 403 a control unit (control unit) for the cache memory, 404 a comparator for comparing the addresses of the data requested by the processor 1902 with the addresses in the block state memory 1910 . Furthermore, 405 denotes a bus monitoring circuit for monitoring the operation of the other modules coupled to the system bus in order to determine the time required for the operation in order to maintain the adjustment of the data and to inform the control unit 403 or the processor 1902 of this that the operation is requested, 406 is a multiplexer for combining the data and data supplied to the memory module, 407 is a timer for counting the elapsed time, 408 , 411 to 413 are control lines, 409 is an address line, and 410 denotes a data line.

The processor 1902 , the cache memory 1908 and the multiplexer 406 are connected to one another by the data line 410 . In addition, processor 1902 , cache memory 1908 , block state memory 1910 , multiplexer 406 , comparator 404, and stack memory 401 are interconnected via address line 409 . Furthermore, the processor 1902 , the control unit 403 , the bus monitoring circuit 405 and the multiplexer 406 are connected to one another via the control line 408 . The control device 403 , the stack 401 and the counter 402 are coupled to one another via the control line 411 . The cache memory 1908 , the block status memory 1910 , the control unit 403 and the timer 407 are connected to one another via the control line 412 . Furthermore, the processor 1902 and the timer 407 are coupled to one another via the control line 413 .

Fig. 5 is a circuit for the signal status between the system bus interface 1913 and describing the system 302nd In the illustration, a signal 503 is arranged on the system bus 302 such that in the negative logic the "assert" (valid) denotes a low level and the "release" (invalid) denotes a high level. In the following description, the signal in the module is identified with a small letter and the signal on the system bus with a large letter. Thus, the output signal 501 from the module is indicated by a and this signal becomes a negative logic signal a * at the output 502 of a NOT (not) circuit 505 and becomes a signal A * on the system bus 503 . a * and A * are coupled by a wired OR circuit. This means that if at least one of the signals a * of all bus interfaces coupled to the system bus 503 is required (asserted), A * goes into the low level state and if all a * signals are not released (released) A * not on the high level.

Fig. 6 shows a detailed arrangement of the double-th memory modules 303 , 2001 and 2007 representing parts which have the same structure as those of the device according to the prior art. In the illustration, 602 denotes a FIFO buffer (buffer memory) for briefly storing data supplied via the system bus 302 , 603 a driver for driving the data of the RAM field 2007 onto the memory bus 302 , 604 a communication signal line (communication device) for the communication between the two memory modules and 601, a control section (controller) for controlling the reading / writing of the data with respect to the RAM array 2007 and further for controlling the communication signal line 604 and the FIFO buffer 602 , the buffer memory being a FIFO Memory is formed. One of the memory modules is the main memory and the other is the secondary memory (master / slave). The main memory / secondary memory is confirmed by the control section 601 , respectively. In the event that both are normal, the "assert" and "release" of the signal to system bus 302 and the transfer of data through main memory are represented. The storage of the data is carried out by both memory modules.

As in the prior art device, the recovery method of this embodiment at the time of the occurrence of an error is arranged so that the state it will hold when the system is operating normally is kept in the memory module (a recovery point is set) when a predetermined condition is satisfied (described below), the process restarts from the last restore point in the memory module in response to the generation of the error. Here, a description is given regarding the setting of the restore point and the stack 401 shown in FIG. 4. The memory request from processor 1902 is processed by control unit 403 . The operation at the time of the read request from processor 1902 is explained with reference to FIG. 7. The control unit 403 first checks whether the requested data is contained in the cache memory 1908 ( 701 ). If the matching address is in block state memory 1910 and the valid bit of the corresponding cache block is "ON" ( 706 ), the process is performed in the same manner as in the prior art system and the requested data is immediately processed by processor 1902 read out ( 705 ). If the valid bit of the cache block is "OFF", the requested cache block is read ( 704 ) from the memory module 303 via the system bus interface 1913 and passed to the processor 1902 while it is being written to the cache memory 1908 become ( 705 ). In the event that the requested data is not in the cache 1908 , it is checked whether there is an unoccupied input in the cache 1908 ( 702 ). If there is an unoccupied input, the flow of operations proceeds to operation 704 mentioned above. If there is no vacant input, the cache block whose modified bit is "OFF" and which is initially used in the cache line is selected ( 703 ) and then the operation flow goes to operation 704 mentioned above. Here, cache line or the like is understood to be a group of cache blocks for storing a block in the main memory (memory module in the embodiment), and as shown in Fig. 22, the correspondence between the main memory and the cache memory shows, the block in the main memory and the cache block are coordinated in advance.

The operation at the time of the write request due to the processor 1902 is described below with reference to FIG. 8. The control unit 403 first checks whether the requested data is present in the cache memory 1908 ( 801 ). In the event that the matching address exists in the block memory 1910 , the valid bit of the requested cache block is checked ( 811 ). If the valid bit of the cache block is "ON", the modified bit is checked ( 812 ). If the modified bit is also "ON", the data from processor 1902 is immediately written to this cache block ( 813 ). In the event that the valid bit is "ON" and the modified bit is "OFF", the modified bit is set to "ON" ( 805 ) and the input address of the cache block is registered in the stack memory 401 ( 806 ) and in addition, the value of counter 402 is incremented by one ( 807 ) and the data is written to this block ( 808 ). The number of non-updated blocks in the cache line is then checked ( 809 ). If it is not one, the value of counter 402 is compared to a predetermined value ( 810 ). If they do not match, the write operation is ended. In the event that the number of non-updated blocks is one in operation 809 or if the match is found in operation 810 , the setting of the restore point is started, as shown in FIG. 9. On the other hand, if the valid bit of the requested cache block is "OFF", the cache block corresponding to the address is read from the memory module and the operation proceeds to operation 805 . If the data requested by processor 1902 is not in cache 1908 , a decision is made as to whether there is an unoccupied input in cache 1908 ( 802 ). If there is an unoccupied input, the operation proceeds to operation 804 . If there is no vacant input, the cache line of the cache line with the modified bit "OFF" and which was initially used is selected ( 803 ) and then the operation proceeds to operation 804 .

According to this embodiment, the restore point is set in the event that the cache line of the cache line in which the modified bit is "OFF" becomes one after the mentioned cache block is updated or the number of updated ones Cache blocks in the cache memory reach a predetermined value. If these cases do not occur within a predetermined period of time, the restore point is also set by means of the timing circuit 407 , as shown in FIG. 9.

In this embodiment, although the operations 805 to 808 are arranged to be carried out continuously, it is appropriate to perform these operations in parallel. In addition, it is also expedient in this exemplary embodiment that the number of updated cache blocks in the cache memory is fixed or programmable by the system. Although the number of un-updated cache blocks per cache line is set to one, this embodiment is not limited to this, but it is enough if the un-updated cache block is present around the internal register of processor 1902 at the time of setting of the recovery point.

Further, in the embodiment described above, in the event that the bus monitor circuit 405 is provided in the processor module, as shown in FIG. 4, and that the bus monitor circuit 405 determines that the system bus 302 caches the updated cache block. If memory 1908 requests, it is also possible to set the restore point as shown in FIG . In this case, the condition that the setting of the recovery point due to the bus monitoring circuit 405 is not performed within a predetermined period of time can further be added to the setting conditions of the recovery point due to the timing circuit 407 .

The operation of the restore point setting will be described with reference to FIG. 9. When the condition for setting the restore point as described above is satisfied, an interrupt request is generated by the control unit 403 or the timer 407 via the control lines 408 and 413 to the processor 1902 . In response to the interrupt request, processor 1902 interrupts the process and then writes the contents of the internal register to the non-updated cache block of cache memory 1908 at the time the interrupt request is received ( 901 ). The modified bit of the cache block in which the contents of the internal register have been written is set to "ON" ( 902 ) and the input address of this block is registered in the stack 401 ( 903 ).

Furthermore, the description will be made with reference to Fig. 10 regarding the cache flush operation ( 904 ). The control unit 403 is equipped with an operation counter which is reset at the time the cache flush operation is started ( 1001 ). The input address of the cache block stored in the stack 401 is read out ( 1002 ), so that the cache block corresponding to this address is retrieved from the cache memory 1908 ( 1003 ) in order to be sent via the system bus interface 1913 to the relevant one Memory module to be forwarded ( 1004 ). In response to the normal transfer, the work counter is incremented ( 1005 ) and a check is made to see if the value of the work counter matches the value of counter 402 ( 1006 ). If there is no match, the process is repeated until the match is reached. In response to the completion of the cache flush operation, a check is made to see if the data has been fed normally or not ( 905 ). In the event of normal termination, the input of stack memory 401 is enabled and the modified bit is set to "OFF" ( 907 ). The counter 402 is then reset ( 908 ) and the timer 407 is reset ( 909 ). If abnormally ended, the process is started again ( 910 ). The second repeat is treated as an error ( 911 ).

The following is the description regarding the communication operation between the memory modules. In Fig. 6, in the event that a signal from the processor module is supplied via the system bus 302 , the main memory 303 a (master) and the secondary memory ( 303 b) (slave) are arranged independently and respond to the supplied signal. In cases in which the main memory 303 a and the sub-memory 303 b normally receive the signal, the control section 601 sends the signal to the other from section via the communication signal line 604th In the event that both receive the signal normally, the main memory represents the implementation of the operation. On the other hand, in this condition, the secondary memory 303 b does not implement the operation. In the event that the signal is not supplied by the main memory 303 a, the fact of the occurrence of a fault is supplied to the process module via the system bus interface 2001 .

The following is the description of the write operation from the FIFO buffer 602 to the RAM field 2007 . After the FIFO buffer 602 normally obtains the cache block through the cache flush transaction, the control section 601 reads the cache block from the FIFO buffer 602 to generate an error correction code which, in turn, enters the RAM field 2007 is registered. This process is repeated until all of the data in the FIFO buffer 602 is written to the RAM field 2007 . This operation is carried out independently in both memory modules 303 a and 303 b of the main and secondary memory. The double-arranged memory modules provide each other with the information indicating the termination via the communication signal line 604 . If both memory modules confirm normal termination, main memory notifies the processor module of the termination. Then the contents of the FIFO memory are deleted.

The memory modules 303 a and 303 b as main and secondary memory independently receive the cache block from the system bus 302 in order to carry out the parity check in the system bus interface 2001 . In the case of normal reception, the memory modules 303 a and 303 b deliver the signals to one another via the communication signal line 604 . If the main memory 303 a and the secondary memory 303 b normally receive the signals, the system bus interface 2001 of the main memory and the secondary memory returns a response to the system bus. If a parity error in the main memory 303 a and / or b occurs in the secondary memory 303, the fact of the occurrence of the error is supplied to the processor module.

In addition, if an error occurs in the write operation from the FIFO buffer 602 to the RAM array 2007 , the write operation of the cache block by the FIFO buffer 602 is repeated from the beginning of the process. If an error occurs despite the repetition of the process predetermined by predetermined times, the consideration of the occurrence of a constant malfunction is performed, and thus a disconnection from the system is made. The main and the secondary memory 303 a, 303 b receive the alternate state through the communication signal line 604 . In the event that the secondary memory 303 b is disconnected from the system, the main memory 303 a stops communication with it and performs the operation alone. On the other hand, when the main memory 303 a is disconnected from the system, the secondary memory 303 b functions as the main memory and performs the operation alone.

Although in the exemplary embodiment the buffer memory with a FIFO memory, it can also be expedient to run it with a static RAM to lead.

The operation on the system bus 302 is explained below with reference to FIGS. 11 to 14. In the following description, the request and the release of the signal due to the memory module is carried out from the main memory after the communication between the double memory modules. In the illustrations, "-0" means a low level and "-1" means a high level.

The processor module, which is granted the right of use by system bus 302, requests the cache flush transaction signal ct * ( 1001 ) and issues the request for the cache flush transaction. Furthermore, an address synchronization signal as * is requested ( 1102 ). If it is determined that AS * on system bus 302 goes low, the memory module requests an address sync signal ak * ( 1103 ) and issues the request indicating receipt, and then decodes the information on the system bus. All memory modules know the cache flush transaction since CT * is at the low level ( 1104 ) and request a data synchronization signal di * ( 1105 ). If execution is impossible ( 1106 ), a busy signal bs * is requested ( 1107 ) to provide the repeated request related to the processor module. Thereafter, all memory modules release the address sync signal ai * ( 1108 ) to give the message that the decision to participate / not participate in the transaction is complete. The process module determines that AI * jumps to the high level and confirms the BS * is high ( 1109 ) and then enters the transfer cycle. If BS * is at the low level, the process is finished and will start again after a period of time.

The cache block transfer ( FIG. 12) is then started. The processor module gives the address of the updated cache block to be forwarded to the memory to the address / data bus ad [] * ( 1201 ) and claims the data synchronization signal ds * ( 1202 ). If it is determined that DS * goes low, the memory module assumes data synchronization signal dk * ( 1203 ) and enables di * ( 1204 ). At this point, the memory module decodes the address and the memory module that has space to store this cache block takes up the data synchronization signal di * ( 1207 , 1208 ). All memory modules release the data synchronization signal dk * ( 1209 ) and provide the information indicating the fact that the decision to grant / block the transfer with respect to the address has been completed. The processor module releases the data synchronization signal ds * and an end of block signal eb * at the time when DI * goes high ( 1205 1206 ).

The transaction enters the cache block data transfer state. The processor module detects that DK * goes high and passes the cache block data to the address / data bus ad [] * ( 1210 ) and inverts the data synchronization signal ds * ( 1211 ). The memory module responsible for the address asserts the data sync signal dk * ( 1212 ) to provide the notification of receipt and writes the cache block data to the FIFO buffer 602 and enables the data sync signal di * ( 1213 ) . The processor module determines that DI * goes high and outputs the data of the next cache block ( 1214 ) and inverts ds * ( 1217 ). The memory module responsible for the address asserts the data sync signal di * ( 1218 ) to provide the notification of receipt and writes the cache block data to the FIFO buffer 602 and enables the data sync signal dk * ( 1219 ). The aforementioned cache block transfer is performed repeatedly until all cache block data is forwarded ( 1222 ).

At the time of the transfer of the last data of the cache block ( 1215 ), the processor module uses the block end signal eb * ( 1216 ). After the transfer of the last data of the cache block, the processor module sends the address of the next cache block to the address / data bus ad [] * ( 1201 ) and requests the data synchronization signal ds * ( 1202 ). If it is determined that DS * and EB * go low, the memory module assumes the data synchronization signal dk * ( 1203 ) and releases di * ( 1204 ). The memory module decodes the address to allow reception and repeat the cache block transfer. After the transfer of all updated cache blocks has ended, the processor module releases the address synchronization signal as * ( 1221 ) and the bus. Upon completion of the transfer from FIFO buffer 602 to RAM field 2007 being processed in the memory module, the processor module ends the transaction.

In the event that the memory module takes a long time to transfer from FIFO buffer 602 to RAM array 2007 , so that the response delays the processor module, the distribution response is selected. In that case, the processor module ends the transaction without waiting for the response from the memory module. At the time the transfer operation is completed, the memory module accesses the processor module via system bus 302 to return the completion response. In the event that in FIG. 14 one of the memory modules is in the process termination state and the other memory module is in the processing state, the incomplete memory module detects the access (termination signal) of the memory module with process termination to the processor module ( 1410 ) in order to issue an invalid response request ir * to demand ( 1403 ). The processing-complete memory module determines that ir * is low and then interrupts the response ( 1404 ). Access ( 1406 ) of the subsequently completed memory module to the processor module becomes valid and the cache flush process is terminated when the processor module receives this response ( 1409 ).

In the data transfer system for the cache flush operation, the cache flush information device, the cache block transfer device and the response device are implemented by the control unit 403 , the processor 1902 in the processor module and by the control section 601 in the memory module.

In the cache controller of this invention a storage device for storing the input addresses of the updated cache block and the con roll device for registering the input address of the updated cache block into the previously mentioned Storage device and for performing the cache Flush transfers related to the registered one gear address with regard to the storage device for Time of the cache flush provided, where possible is the time required for the cache flush shorten and the process at high speed constant reliability.

In addition, the Erfin fault tolerance computer with a corresponding storage device and Control device equipped to thereby approx che flush operation at high speed possible.

In addition, the counter is used to count the number updated cache blocks, timing for measuring elapsed time and bus monitoring circuit for monitoring the system bus of the re Manufacturing point set on the condition that the number of cache blocks of cache memory that not up to date for the respective lines or lines lized are reached a predetermined value, the Total number of cache blocks updated in the Cache reaches a predetermined value other processor module on the updated cache Block in cache memory related to the bus system takes or any of the aforementioned cases does not occur in the predetermined period. Consequently it is possible to restore the maximum interval  to ensure positioning points to ensure real-time processing to realize processing.

It can also be used in the memory module seen and double in the same physical space provided cache memory the cache flush transak tion due to the cache flush operation only once be carried out, which means that for setting the Restore point required time reduced becomes.

Furthermore, the processor module designates for implementation cache flush operation, the cache flush trans action and in response to the designation choose the relevant memory modules the cache flush informa tion device for preparing the reception of the Cache flushes and the memory module for storing the Cache blocks with the transfer of the cache block addresses se, and the cache block transfer facility is in front seen that continuously the transfer cycle of the Executes cache blocks in which the data transfer of the Cache blocks is performed, the cache flush by performing the bus transaction only once can be realized, whereby the for the setting of the Restore point necessary time who reduced that can.

Furthermore, with the cache block transfer device device the cache block forwarded to the buffer memory leads and upon completion of the transaction that leads Memory module the data transfer from the buffer memory to the RAM field and receives the bus again after the Completion of the process, the responder device to return the answer to the processor  dul releases the system bus, so that an effective System bus really is.

Claims (10)

1. Cache controller for controlling a write-back type cache with
a memory device for storing an input address of an updated cache block and
a control unit for registering the input address of the updated cache block into the storage device and, moreover, for performing a cache flush transfer with respect to the registered input address with reference to the storage device at the time of the cache flush. 2. Cache controller according to claim 1, which for a fault tolerance computer in the multiprocessor operation is used in which each processor a write-back cache points. 3. Cache controller according to claim 2, which in a fault tolerance computer in the multiprocessor operation is used with a license plate memory, a comparator, a control unit and a bus monitor, with a plurality of modules that have a microprocessor, a ca che controller, a cache and have an interface circle that coincide with one another other by one with a main memory bound system bus are connected, characterized, that the cache controller with a Sta pelspeicher as storage device for Spei  save the input address of the updated Cache blocks is provided, the stacking saved by the control unit and the input address of the updated approx che blocks registered in the stack , and being the write back regarding of the registered input addresses that are on get the stack is done, if the updated cache blocks are all too are to be written back. 4. Cache control device according to claim 1, characterized characterized in that the storage device a Stack is from a FIFO memory consists. 5. Fault tolerance computer that with a plurality of processor modules and a plurality of Memory modules is equipped, characterized, that the processor module a processor, a Restore type cache, a store chereinrichtung for storing an input address of one updated by the processor Cache blocks and a control unit for the regi the input address of the updated Cache blocks and to forward a cache Blocks according to the registered input address to the memory module with reference on the storage device at the time of Cache flush. 6. Fault tolerance computer, which is equipped with a plurality of processor modules and a memory module, characterized in that the processor module has a processor, a cache memory of the write-back type, a control device for controlling the cache memory, a counter for counting the number of updated Cache blocks and a timer for measuring the elapsed time, wherein the processor sets a restore point under at least one of the conditions that:

• a) the number of cache blocks in the cache memory that are not updated by cache lines or lines reaches a predetermined value,
• b) the total number of updated cache blocks in the cache memory reaches a predetermined value, and
• c) the cases shown in (a) and (b) do not occur in a predetermined period of time.

7. Fault tolerance computer according to claim 6, characterized characterized in that the processor module with a Bus monitoring circuit for monitoring the Opera tion of the different processor modules is set up to set the restore point zen when the locally updated cache block in the cache of the different ones Processor modules is accessed or if the se access operation is not in a predetermined time. 8. fault tolerance computer, characterized in that he has a variety of processor modules and  Has memory modules in the same physical storage space arranged twice are, the processor module being a processor, a write-back type cache and a control device for controlling the cache Has memory and wherein the memory module a buffer memory for short-term storage of a transferred cache block, a communication cation device for the production of communication tion between two assigned memory modules and a control unit for controlling the buffer memory and the communication device points. 9. Fault tolerance computer according to claim 8, characterized characterized that he is a data transfer system which is cache flush information Direction to notify all memory modules le about the cache flush transfer and a cache Block transfer device for forwarding a Address and data for each cache block in order to the transfer of all updated To perform cache blocks. 10. Fault tolerance computer according to claim 9, characterized characterized in that the data transfer system knows further equipped with an answering device which is after the cache block transfer direction to all of the updated cache blocks the memory module has forwarded one of the memory module in which the received cache Block last saved to the processor response to the module.