DE4136525A1 - Electronic circuit testing for PCB mounted devices - reprogramming logic components for test function, stimulating circuit nodes for testing and reprogramming useful function - Google Patents

Abstract

Reprogrammable logic components are programmed to carry out test functions for the circuit, and after the end of the test they are reprogrammed for the actual useful function. The programming may involve the formation of test function signal paths that would be too expensive to sensitise for useful functions, in order to stimulate circuit nodes for testing. Signal paths may be formed which are not present for the useful function or which would be two expensive to sensitise for the useful function, in order to allow observation of circuit nodes. ADVANTAGE - Number of adaptor pins is reduced (ideally to nought) without components requiring additional test cells or circuits.

Description

The invention relates to a method for Assembly test.

In the assembly test, fully assembled and soldered Assemblies for short circuits and interruptions in the Conductor tracks, on non-soldered component connections, checked for incorrect assembly and other errors, whereby actually all possible errors are included should.

The prior art offers two basic for this different procedures, namely firstly the Contacting the assembly via a needle bed adapter on an in-circuit test system, secondly the use of Boundary scan techniques such as B. JTAG.

The former method allows access to internal ones Node of the assembly, but encounters high-density SMD assembled modules to physical limits, some of which from the feasible dimensions and mechanical Properties of the needles, partly from unwanted ones parasitic electrical effects caused by the Needle bed adaptation exist. Other than that, the construction of the adapter, especially for smaller series insignificant cost factor, so that this by Minimization of the number of needles should be kept small, without however affecting the quality of the test. A Another problem is that the state of the art Technology appropriate programs for automatic Generation of test vectors based on the Functional complexity of today's integrated modules often fail, so test quality suffers, even if a complete needle adaptation of all networks is required  is.

The second method assigns the component connection additional internal test cell via a test bus becomes accessible. In this way, contacts can be made largely avoided by needles. Since the Useful function of the component by the test cell from the Component connections can be separated, the outer Connection networks can be checked in a simple manner without that the often complex useful function requires for this would. The disadvantage of this method is that of Test cells and their control increased effort Chip area, which is especially the case with smaller LSI functions Building block costs would increase so much that this procedure is no longer practical. The result is that straight such functions do not work with boundary scan test cells Tobe offered.

The task for the inventor is to create a new one Procedure to find assembly test in which the number of Adaptation needles can be reduced (ideally to Zero) without the components used additional Test cells or circuits must contain.

According to the invention, this object is achieved by a method solved according to claim 1, preferred embodiments are the See subclaims. This is made possible Test procedure through the unusual use of the Properties of reprogrammable logic modules, e.g. B. in EEPROM technology, which is otherwise commercially available are. Depending on the design of the programming method of Building blocks, d. H. depending on the number of for programming required connections reduces the number of connections required Module test required needles, since essentially only these connections still need to be contacted.  

The state of the art today provides such modules with 44 to 120 pins that can be programmed via 4-8 pins. If necessary, the programming voltage can also be supplied within the circuit if it is blocked by a diode 1 from the supply voltage, and there are already families of modules that can be reprogrammed via a four-wire bus within the module without additional programming voltage. Although this was intended to avoid damage to the components when handling them in automatic programmers or with manual programming on programming devices, it allows the test method described here to do entirely without needle adaptation. These statements show that the reprogrammability in the assembly poses no problems, so that the method described is practical.

The invention is explained below with reference to the example circuit shown in the drawing. This consists of three reprogrammable logic modules 2 , 4 and 6 , which are connected to one another by signal lines 3 and 5 and via a connector 7 to the outside world. Diode 1 shows an example of how a programming voltage can be supplied to individual logic modules, which is known to be higher than the normal operating voltage. The connections for programming are not shown, this aspect has already been discussed.

It is now assumed that each of the three logic modules contains a sequential function, a state machine. If the middle module 4 and its connection networks are now to be checked on the module, this means that not only its own useful function, but also the useful functions of the logic modules 2 and 6 flow into the test generation and increase their complexity.

In practice, this often leads to program failure for automatic test vector generation, one Then test generation is not possible. Without needle adaptation is, however, a targeted stimulation and observation of the internal networks no longer feasible in this case, and nor a test.

The invention will now be described with reference to the drawing explained.

If module 2 is reprogrammed with a simple function, for example with direct combinatorial signal paths between the pins (shown in dashed lines in the picture), as is module 6 , then the test vector generation can only deal with module 4 , which simplifies the test problem. The test patterns thus generated can then be easily stimulated or observed via the simple signal paths from the plug connector 7 in the sense of claims 2 and 3.

Once the test of module 4 and the networks connected to it has been completed, and module 2 is then to be tested, for example, this is reprogrammed with its useful function, modules 4 and 6 with simple test functions. In this way, the simplest possible test is ensured in the sense of claim 4 by repeated case-specific reprogramming.

In this way, all building blocks can be built step by step and connection networks are checked. Only at the end all blocks receive the final programming with their useful function.  

It should be noted that the main claim of the invention also further possibilities over the construction of signal paths going out includes. For example, individual Logic modules for testing connected Circuit parts as complete pseudorandom Test vector generators for stimulation and as Signature register for the observation of signals be reprogrammed, since the procedure is basically the The entire scope of a logic module is available stands.

It should also be noted that the described here Process due to its simplicity lends itself to automatic software tools. So can make the necessary manufacturer-specific Programming algorithms along with automatic generated test circuits and Reprogramming strategies easily into that Pattern format of an in-circuit test system translated on which the process is then carried out. A hardware or software expansion of the Test systems are usually not required for this.

Claims (4)

1. A method for module testing, characterized in that reprogrammable logic modules perform test functions for the module by reprogramming on the module and are reprogrammed to the actual useful functions after the tests have been completed. 2. The method according to claim 1, characterized in that by reprogramming logic modules with a Test function signal paths that are built in the Usage function would be too expensive to sensitize to Purpose to stimulate circuit nodes for testing. 3. The method according to claim 1, characterized in that by reprogramming logic modules Test function signal paths that are built in the User function are not available, or signal paths be built up, which is too expensive in the useful function would be sensitizing for the purpose of switching nodes to Watch test. 4. The method according to any one of claims 1 to 3, characterized characterized in that the reprogramming during the Test phase depending on the circuit part to be tested is done several times so that the individual test sections can be kept as simple as possible.