DE4126953A1 - CORDIC trigonometric algorithms for processing of arithmetic operations - involves iterative computation of XYZ values with data word-width of N bits using adder and subtractor units - Google Patents

Abstract

A so called CORDIC trigonometric computing technique provides a simplified means of processing of arithmetic functions. The process uses algorithms performing iterative operations and has adder/subtractor blocks (X, Y, Z). One block (Z) has n/3 adder units, where 'n' is the number of adders previously utilised. A code conversion process is used (U) that is in table form. In a rotation mode, a specific number of bits are used (delta, sigma). In a vector mode, values are fed to an adder/subtractor (S, A). ADVANTAGE - Reduced hardware requiremnt.

Description

The invention relates to circuit arrangements for implementation of the CORDIC algorithm according to the generic term of Claims 1 and 2 and methods for performing the CORDIC algorithm according to the preamble of the claims 5 and 6.

Many areas of signal, image and data processing require the fast and inexpensive calculation of arithmetic expressions. A development in this direction mainly becomes more and more complex through the use Algorithms and the simultaneous increasing level of VLSI integration promoted.

As a suitable method for solving such arithmetic intensive Tasks has been in the recent past the CORDIC algorithm is increasingly used. In this context is referred to the publications J.E. Volder, "The CORDIC Trigonometric Computing Technique "IRE Transactions on Electronic Computers, Vol. EC-8, No. 3, pp. 330-334, Sept. 1959 and J. S. Walther, "A Unified Algorithm For Elementary Functions ", Spring Joint Computer Conference (SJCC) 1971, p. 379-385. The CORDIC algorithm stands out due to its high functionality or the high number of provided arithmetic, especially so-called elementary Functions and the basic operations required for this, namely addition / subtraction and binary shifting out.

The advances in integration density are now fully parallel CORDIC arrays are also possible, in which the CORDIC-typical n-fold implementation of three iteration equations  (n data word width in bits) into a matrix Arrangement of three n-bit wide iteration levels is implemented. Depending on whether between the individual Steps registers are inserted or not, one speaks of a synchronous pipeline or an asynchronous array architecture. It is assumed that these architectures increase in importance because with them either systems with high data throughput rate or low latency in one be structured in a regular, VLSI-compliant manner can. A similar development has already occurred the implementation of multiplier arrays in high performance applications performed where recursive orders, although cheaper in terms of chip area, none Play more role.

In the following, the previous procedure is first described using the usual iteration equations are described. These equations ring:

x _{i + 1} = x _i - σ _i 2 ^-i y _i (1)

y _{i + 1} = y _i + σ _i 2 ^-i x _i (2)

z _{i + 1} = z _i - σ _i arctg (2 ^-i ) (3)

where σ _i ε {-1,1} indicates the direction of rotation of the iteration. In ROTATION mode, σ _{i is determined} from the sign of z _i :

whereby z _i is driven towards zero in the course of the iteration process. In VECTORING mode, i is determined from the sign of y _i , which drives y _i towards zero:

The CORDIC method normally requires n iterations to be carried out for an accuracy of n bits. As a result, in a pipeline or array architecture, three n-bit adders / subtractors are required n times for the implementation of equations (1) to (3), namely for n iterations. In FIG. 2, a stage or row is shown of such an array.

Direct mapping of the iterative CORDIC equations a pipeline or array architecture precludes that the chip area of these architectures grows proportionally 3n², where n denotes the data word width in bits. This relationship currently only has non-recursive implementations of up to approx. 20 bits possible. Each Reduce chip area complexity without sacrificing speed seems sensible because in digital signal processing Word widths up to approx. 40 bits and especially in numerical data processing up to 80 bits occur.

Compared to other methods, the hardware expenditure increases particularly strong in the CORDIC method because three data paths for the implementation of the x, y and z iteration equations are necessary. As already mentioned, this is the case the chip area proportionally 3n².

The invention has for its object a circuit arrangement to specify for the implementation of the CORDIC algorithm, which require less space for the Implementation required for a semiconductor chip.

This object is achieved by the circuit arrangement with those specified in claims 1 and 2 Features resolved.  

The invention is also based on the object Procedure for implementing the CORDIC algorithm specify that compared to the known CORDIC process simplified and faster.

This object is achieved by the method with the solved in claims 5 and 6 specified features.

The invention is based on the knowledge that the third Setup for the iterative calculation of the z values by about two thirds of the levels can be shortened by the steps by a subtractor or a Adders and a subtractor are replaced.

According to the invention, according to a first circuit alternative, the third device (Z) for calculating the third final value z _n

• - On the one hand comprises a first section with j steps for calculating the third value z _j using the following iteration rule: z _{i + 1} = z _i - σ _i · arctg (2 ^-i ), for i = 1,. . ., j; where jn / 3 and j is an integer; and
• on the other hand includes a second section which calculates the third end value z _n on the basis of the value z _j and the values σ _i for the jth to (n-1) th stage on the basis of the following rule: z _n = z _j - A + B; with

According to the invention, according to a second circuit alternative, the third device (Z) for calculating the third final value z _n

• - On the one hand comprises a first section with j steps for calculating the third value z _j using the following iteration rule: z _{i + 1} = z _i - σ _i · arctg (2 ^-i ), for i = 1,. . ., j; where jn / 3 and j is an integer; and
• - on the other hand includes a second section which calculates the third end value z _n on the basis of the values z _j and the values σ _i for the i-th to n-th stage on the basis of the following rule: z _n = z _j - z _t ; in which With

On the basis of the invention, it is possible to the implementation effort for the z iteration equation decrease about 2/3. This leads to an overall (Chip area) savings of almost 20%, but practically none Loss of speed occurs. The effort behaves then only proportional to 2.5n².

Advantageous further developments are in dependent Claims specified.

The subject matter of the invention is based on an embodiment described with reference to the drawing. It shows

Fig. 1 shows a circuit arrangement of the invention for performing the CORDIC-algorithm; and

FIG. 2 shows a stage of a CORDIC array in the circuit arrangement according to FIG. 1.

Considerations for equation (3) for the z iteration now follow.

z _{i + 1} = z _i - σ _i arctg (2 ^-i ) (3)

In equation (3), the n-bit constant arctg (2 ^-i ) is subtracted or added in the (i + 1) th iteration from the value z _i .

The invention is based on the knowledge that in the iterative calculation of z _i after a defined number of iterations, the following additions / subtractions can be substituted with much less effort.

The arctg function can be represented as a series development with an error less than or equal to 2 ^{-n as} follows:

arctg (2 ^-i ) = 2 ^-i - (1/3) 2 ^-3i +. . . = 2 ^-i for i <n / 3 (4)

Equation (3) can therefore be written for i <n / 3 as:

z _{i + 1} = z _i - σ _i 2 ^-i (5)

or with j as the smallest integer greater or equal to n / 3:

In practice, equation (6) means that the desired end value z _{n of} the iteration can be calculated directly from z _j by adding / subtracting (nj) single-digit binary words. For example, for j = 3, n = 8, σ₃ = 1, σ₄ = -1, σ₅ = -1, σ₆ = 1, σ₇ = -1

z₈ = z₃ - 2 ^-3 + 2 ^-4 + 2 ^-5 - 2 ^-6 + 2 ^-7

These (n-j) one-digit binary words can be divided into two n-digit Binary words are summarized, namely the summands with a positive sign in the one data word and the Summands with negative signs in the other.

The conversion of the (n-j) additions of equation (6) into one The following describes addition and subtraction Expression:

With

Applied to the previous example:

z₈ = z₃ - 0.0010010₂ + 0.0001101₂

So approximately 2/3 of the iterations in the z-path can add up and subtraction can be reduced. For the practical Execution with a circuit arrangement means this the loss of the z-path after n / 3 iterations.

It remains to be seen how the σ _{i are} determined. In the VECTORING operating mode, the derivation from the signs of y _i remains as before. However, the sign of the z _i can no longer be determined in the ROTATION because no iteration is carried out. However, one can then use the method of predicting the direction of rotation, as described in the dissertation D. Timmermann, "CORDIC Algorithms, Architectures and Monolithic Realizations with Applications in Image Processing", Gesamthochschule Universität Duisburg, 1990, pp. 157-162. The σ _i are generated directly from the bits of z _j by recoding, as described below.

Let us consider the state at the beginning of the jth iteration. The value z _j in the z path is given by its binary representation:

On the other hand, the following iteration process according to equation (3) divides the value z _j into arctg (2 ^-i ) terms. In addition, by definition, z _n in ROTATION mode is less than or equal to 2 ^-n , so that from equation (6) with an error of less than 2 ^{-n it} follows:

According to equation (4) arctg (2 ^-i ) = 2 ^-i is loaded with an error of less than or equal to 2 ^-n for i <n / 3. The comparison of the last two equations and the permissible values for Z _i and σ _i then shows that the sought σ _{i can be obtained} from the bits Z _i of z _j by recoding. This recoding is carried out using the following table:

For negative numbers z _i , invert the σ _i . The following example illustrates the conversion process.

With this recoding, all of the σ _j to σ _n-1 sought are obtained directly from z _j .

A circuit comprising the subject of the invention is shown schematically in FIG. 1. The large blocks labeled X, Y and Z contain the adders / subtractors for the x, y and z paths. In the z path, only n / 3 are required instead of n adders as before. U denotes a recoder which implements the recoding table given above and in the ROTATION mode obtains the σ _i from the bits of z _j . In the VECTORING mode, the σ _{i are determined} as usual from the signs of y _i and combined into two data words according to equation (7) and then used with the adder A and the subtractor S to calculate z _n .

In the above, it was partially assumed that that so-called non-redundant adders for implementation of the iteration equations are used. As part of the invention it is also possible to add redundant adders (Carry-Save (compare R. Künemund, H. Söldner, S. Wohlleben and T. Noll, "CORDIC Processor With Carry-Save Architecture", Proceedings of 16th European Solid-State Circuits Conference, Grenoble, France, pp. 193-196, Sept. 1990); Redundant Binary (compare the publication of H. Yoshimura, T. Nakanishi and H. Tamauchi "A 50 MHz CMOS Geometrical Mapping Processor ", IEEE Digest of Technical Papers, ISSCC'88, pp. 162-163, Feb. 1988)). in the Circuit arrangements can also be used within the scope of the invention for performing the CORDIC algorithm on others Execute coordinate systems in which the CORDIC algorithm is applicable, which is commonly associated with the Parameter m is specified. From the invention too includes the cases for m = 0 and m = -1.

The adder A and the subtractor B in FIG. 1 can be combined to form a subtractor, which further reduces the outlay. This follows from the fact that equation (7) can also be written as follows:

The bracketed term, here designated z _t , can be calculated without subtraction, because it applies in an n-bit two's complement representation

in which

The term z _t can therefore easily be determined from the σ ′ _i .

Claims (12)

1. Circuit arrangement for carrying out the CORDIC algorithm for the iterative calculation of the x, y and z values with a data word width of n bits, with

• - a first device (X) with n stages for calculating a first end value x _n using the following iteration rule, which applies to each stage: x _{i + 1} = x _i - σ _i · 2 ^-i · y _i , for i = 1 ^,. . ., n;
• - a second device (Y) with n stages for calculating a second final value y _n using the following iteration rule, which applies to each stage: y _{i + 1} = y _i - σ _i 2 ^-i x _i , for i = 1 ^,. . ., n; and
• - a third device (Z) for calculating a third final value z _n with at least one step for calculating the value z _i using the following iteration rule: z _{i + 1} = z _i - σ _i arctg (2 ^-i ); where σ _i ε { -1.1} indicates the direction of rotation of the iteration,

characterized in that the third device (Z) for calculating the third end value z _n

• - On the one hand comprises a first section with j steps for calculating the third value z _j using the following iteration rule: z _{i + 1} = z _i - σ _i · arctg (2 ^-i ), for i = 1,. . ., j; where jn / 3 and j is an integer; and
• - On the other hand, includes a second section which calculates the third end value z _n on the basis of the value z _j and the values σ _i for the jth to (n-1) th stage on the basis of the following rule: z _n = z _j - A + B; with

2. Circuit arrangement for carrying out the CORDIC algorithm for the iterative calculation of the x, y and z values with a data word width of n bits, with

• - a first device (X) with n stages for calculating a first end value x _n using the following iteration rule, which applies to each stage: x _{i + 1} = x _i - σ _i · 2 ^-i · y _i , for i = 1 ^,. . ., n;
• - a second device (Y) with n stages for calculating a second final value y _n using the following iteration rule, which applies to each stage: y _{i + 1} = y _i - σ _i 2 ^-i x _i , for i = 1 ^,. . ., n; and
• - a third device (Z) for calculating a third final value z _n with at least one step for calculating the value z _i using the following iteration rule: z _{i + 1} = z _i - σ _i arctg (2 ^-i ); where σ _i ε { -1.1} indicates the direction of rotation of the iteration,

characterized in that the third device (Z) for calculating the third end value z _n

• - On the one hand comprises a first section with j steps for calculating the third value z _j using the following iteration rule: z _{i + 1} = z _i - σ _i · arctg (2 ^-i ), for i = 1,. . ., j; where jn / 3 and j is an integer; and
• - on the other hand includes a second section which calculates the third end value z _n on the basis of the values z _j and the values σ _i for the i-th to n-th stage based on the following rule: z _n = z _j - z _t ; with in which With

3. Circuit arrangement according to claim 1 or 2, characterized in that the third device comprises a third section which determines the values σ _i in the VECTORING operating mode as follows based on the sign of the values y _i : 4. Circuit arrangement according to one of claims 1 to 3, characterized in
that the third device comprises a fourth section which, in the ROTATION mode, determines the values σ _i based on the following recoding rule from the bits Z _{i of} the value z _j : With and
that the third device inverts the values σ _i for negative values of z _j . 5. Method for performing the CORDIC algorithm for the iterative calculation of the x, y and z values with a data word width of n bits, with the following steps:

• a first sequence of steps for the n-stage calculation of a first end value x _n using the following iteration rule, which applies to each stage: x _{i + 1} = x _i - σ _i · 2 ^-i · y _i , for i = 1 ^,. . ., n;
• a second sequence of steps for the n-stage calculation of a second final value y _n using the following iteration rule, which applies to each stage: y _{i + 1} = y _i + σ _i 2 ^-i x _i , for i = 1 ^,. . ., n; and
• a third sequence of steps for calculating a third final value z _n with at least one step for calculating the value z _i using the following iteration rule: z _{i + 1} = z _i - σ _i arctg (2 ^-i ); where σ _i ε {-1, 1} indicates the direction of rotation of the iteration,

characterized in that the third sequence of steps for calculating the third final value z _n

• - On the one hand comprises a first section with j steps for calculating the third value z _j using the following iteration rule: z _{i + 1} = z _i - σ _i · arctg (2 ^-i ), for i = 1,. . ., j; where jn / 3 and j is an integer; and
• on the other hand includes a second section which calculates the third end value z _n on the basis of the value z _j and the values σ _i for the jth to (n-1) th stage on the basis of the following rule: z _n = z _j - A + B; with

6. Method for performing the CORDIC algorithm for the iterative calculation of the x, y and z values with a data word width of n bits, with the following steps:

• a first sequence of steps for the n-stage calculation of a first end value x _n using the following iteration rule, which applies to each stage: x _{i + 1} = x _i - σ _i · 2 ^-i · y _i , for i = 1 ^,. . ., n;
• a second sequence of steps for the n-stage calculation of a second final value y _n using the following iteration rule, which applies to each stage: y _{i + 1} = y _i + σ _i 2 ^-i x _i , for i = 1 ^,. . ., n; and
• a third sequence of steps for calculating a third final value z _n with at least one step for calculating the value z _i using the following iteration rule: z _{i + 1} = z _i - σ _i arctg (2 ^-i ); where σ _i ε {-1, 1} indicates the direction of rotation of the iteration,

characterized in that the third sequence of steps for calculating the third final value z _n

• - On the one hand comprises a first section with j steps for calculating the third value z _j using the following iteration rule: z _{i + 1} = z _i - σ _i · arctg (2 ^-i ), for i = 1,. . ., j; where jn / 3 and j is an integer; and
• - on the other hand includes a second section which calculates the third end value z _n on the basis of the values z _j and the values σ _i for the i-th to n-th stage on the basis of the following rule: z _n = z _j - z _t ; in which With

7. The method according to claim 5 or 6, characterized in that the third sequence of steps comprises a third section, through which in the VECTORING mode the values σ _{i are determined as} follows based on the sign of the values y _i : 8. The method according to any one of claims 5 to 7, characterized in
that the third sequence of steps comprises a fourth section, through which in the ROTATION mode the values σ _i are determined from the bits Z _{i of} the value z _j on the basis of the following recoding rule: With and
that the third sequence of steps inverts the values σ _i for negative values of z _j .