DE4122060A1 - Multiport memory with RAM and SAM ports - has inner data bus and memory cell field with line and column matrix of memory cells - Google Patents

Abstract

A data bus provides serial, external input and output of data. A memory cell field (1) is in the form of a two-dimensional field of lines and columns of memory cells. A data resistor (4) has a number of elements determined by the facility for a simultaneous transfer of memory cell data of a line. A counter (6') is provided for clock pulse signals, and a selector (5) receives the counting data as a register element selection signal for sequential selection of the register elements and coupling each one to the internal data bus (SO). The counter contains a counter value generator (60,70), changing sequentially in response to the clock pulse signal until all register elements have been selected. USE/ADVANTAGE - Signal processing with CRT display. High speed processing of two dimensional image data.

Description

The present invention relates to multi-port memory cher with random access and in particular on a body a dual port memory for image display purposes and a ver drive to access such.

In information processing, image information to be processed or processed is displayed on a CRT display (cathode ray tube). For this purpose, a memory, called an image buffer, is used to store an image of image information (graphic information). This frame buffer is commonly referred to as video RAM (VRAM). In addition to this video RAM, an image plane memory for storing a plane of image information and a field memory for storing a partial image (field) of image information exist as video RAMs. The following is a description of a structure and operation of an image processing system with video RAM with reference to FIG. 1.

As shown in FIG. 1, a video signal processing system includes a CPU (central processing unit) 100 , a CRT display control unit 102 , a video RAM 104 and a CRT display unit 106 . The CPU 100 is operated to write desired data into the video RAM 104 or to read data therefrom.

The CRT display controller 102 generates horizontal / vertical sync signals for the CRT display 106 and also generates addresses for reading data from the video RAM 104 and for applying data to the video RAM 104 . The video RAM 104 has stored image information to be processed or already processed. The image information stored in the video RAM 104 is read out under the control of the CRT display control unit 102 and is applied to the CRT display unit 106 .

The CRT display unit 106 displays the data of the video RAM 104 on a screen.

The CPU 100 can provide optional access for reading and writing information to the video RAM 104 . This can effect the desired processing operation of the information stored in the video RAM 104 , and then the processed data can be rewritten in the video RAM 104 .

The CRT display unit 106 receives the data read out serially from the video RAM 104 and displays an image on a screen corresponding to the received data.

When a general dynamic random access memory (DRAM) is used as a frame buffer, it is necessary to read out data from the DRAM during a display period without interruption so that video signals for displaying an image on a screen of the CRT display unit 106 are generated can. A memory cycle of the general DRAM is determined either as a read cycle or as a write cycle. Therefore, during the above display period, the CPU 100 cannot access the DRAM, and the period for accessing the video RAM 104 by the CPU 100 is restricted to a horizontal or vertical blanking phase outside the display phase. This increases the waiting time of a CPU and reduces the execution speed of a program.

In order to overcome these disadvantages of the general DRAM as an image buffer, multi-port RAMs (dual-port RAMs) are widely used as image information memories. A multi-port RAM includes an I / O port (RAM port) which can be accessed by the CPU 100 and a serial I / O port (SAM port) for serial reading of display data control of the CRT display control circuit 102 and to apply the data to the CRT display 106 .

In the multi-port RAM, when data of one line (which corresponds to data of a horizontal line) is transferred from the RAM port to the SAM port, display data is read from the SAM port during the display period during which the CPU 100 is on the RAM -Port can access. This reduces the waiting time of the CPU and increases the execution speed of the program.

The diagram in FIG. 2 schematically illustrates an example of an overall structure of a conventional multi-port RAM. The multi-port RAM shown in FIG. 2 comprises a RAM I / O port and a SAM I / O port and is therefore usually referred to as dual-port RAM. This dual port RAM is described below.

The dual-port RAM shown in FIG. 2 can be roughly divided into a RAM port part and a SAM port part. The RAM port part comprises a memory cell array 1 with a plurality of memory cells arranged in a two-dimensional array of rows and columns, a row decoder 2 for decoding an internal address signal Add, which was generated in accordance with an external address, for selecting a corresponding row in the Memory cell array 1 , and a column decoder I / O control circuit 3 , which receives an internal address signal generated according to an external address as column address in order to select a corresponding column in field 1 , and which also inputs and outputs data in or controls from the selected column.

In response to an internal row address pulse signal RAS, the row decoder 2 locks an applied internal address signal Add as row address, decodes it and selects a corresponding row in the memory cell array 1 .

In response to the internal column address pulse signal CAS, the column decoder I / O control circuit 3 locks an applied internal address signal Add as a column address, decodes it and selects a corresponding column in the memory cell array 1 . This column address I / O control circuit 3 also responds to a read / write signal R / which determines reading and writing of the data for controlling the reading and writing process. This means that the column decoder I / O control circuit 3 transmits data to be written to a selected memory cell in response to the later drop of the signals and the signal R /. The column decoder I / O control circuit 3 is also connected to an I / O buffer (not shown) via a data bus DQ. The operation of the RAM I / O buffer is controlled by an I / O control area of the column decoder I / O control circuit 3 .

The internal row address pulse signal RS and the internal gap tenadreßpulssignal CAS are internal control signals that as Response to an external row address pulse signal or a  external column address pulse signal are generated, both be created externally.

The SAM port area comprises a SAM register 4 with a number of register elements that is large enough to allow a simultaneous transfer of memory cell data of one row in the memory cell array 1 , a counter 6 for counting clock signals SC and a SAM -Decoder 5 , which decodes a count of the counter 6 and selects the corresponding regi ster element in register 4 , so that the selected regi ster element is connected to an internal serial data bus SO.

The SAM register 4 includes a transfer gate device for simultaneously receiving the memory cell data of a selected row in the memory cell array 1 in response to a transfer command signal. Data transferred from the SAM register 4 to the internal serial data bus SO is output through a SAM I / O buffer (Not shown).

In response to the internal column address pulse signal CAS, the counter 6 latches an internal address signal Add to set its original count value. This function of setting an initial value of the counter 6 is activated by the transfer command signal. The operation is described below. Image data to be displayed are generated by a CPU or the like and then transmitted to the RAM port of the dual-port RAM. In the RAM port area, an address signal Add is decoded by the row decoder 2 and the column decoder I / O control circuit 3 by controlling the control signals RAS and CAS, and then a corresponding memory cell is selected from the memory cell array 1 .

The image data formed by the CPU is transferred to the selected memory cell for display via the data bus DQ and the column decoder I / O control circuit 3 . In the data write operation, the read / write signal R / W is at "L" level, indicating the data write operation.

As the address signals, the row address signal and the column address signal are applied in time-division multiplexing. A distinction between the row address signal and the column address signal is effected by the row address pulse signal RAS and the column address pulse signal CAS. The writing of data from e.g. B. the CPU via this RAM port in the memory cell field 1 corresponds to that in a general DRAM.

The image data formed in the memory cell array 1 are read out via the SAM port for high transmission speed, e.g. B. a CRT, which forms a display unit of the raster scan type. The reading of data from the SAM port is described below with reference to the operating pulse diagram shown in FIG. 3.

The reading of data from the SAM port begins such that data for one row from the memory cell array 1 to the SAM register 4 are transmitted and controlled by control of the address signal Add and external control signals. This transfer of the data from the memory cell array 1 to the SAM register 4 is effected by setting the transfer command signal to "L" and setting the signal R / to "H" at the time when the external row address pulse signal is activated (ie to "L "Level is set). In this mode, the control signal can be transmitted.

In response to the drop in the external column address pulse signal, the address signal Add is loaded into the counter 6 . The column address signal loaded into the counter 6 designates the memory element which is to be selected first in the SAM register 4 . The counter 6 is activated for reading by "L" of the transfer command signal, and is loaded with an applied column address signal CAS in response to the signal CAS.

The counter 6 counts the control clock signals SC and applies the counted value to the SAM decoder 5 as a register element designation signal. The SAM decoder 5 decodes this applied count value in order to select a corresponding register element in the SAM register 4 and to connect it to the lower serial data bus SO. The data SO on the internal serial data bus SO are output by the SAM I / O buffer. Therefore, in response to the clock signals SC, the register elements in the SAM register 4 are selected sequentially and the data in the selected register elements are transferred to the internal data bus SO.

The serial data SO are from the SAM port in response read out on the clock signals SC so that it is not necessary is memory cells by switching the signals and to designate how it is handled with a conventional DRAM becomes what reads data at high speed leads. The serial data SO read from the SAM port are then transmitted to a display unit.

As described above, in a conventional dual Port RAM memory cells selected by the address signals which are synchronized with the address pulse signals and as with conventional general memories, and the Image data is inserted into the selected memory cells wrote.

In order to provide image data for a display unit, the transfer command signal is first set to "L" to select the transfer mode. Then, in synchronization with the row address pulse signal, an address signal for selecting a transfer row is provided in the memory cell array 1 . In addition, another address signal (column address) Add is applied in synchronism with the column address pulse signal to the counter 6 , which determines the addresses of the SAM port, so that a start address for starting reading of SAM data is specified. Thereafter, the count value of the counter 6 is increased each time the clock signal SC is applied to the counter 6 , and the data is successively output from the SAM port in synchronism with the clock signal SC.

Fig. 4 illustrates a relationship between Speicherzel lenpositionen in memory cell array 1 and display positions on a screen of a display unit. As shown in Fig. 4 ge, the memory cell positions in the memory cell array 1 and the display positions on the screen have a 1 to 1 relationship. This means that a line in the storage cell lenfeld 1 corresponds to a horizontal line on the display screen CRT. In the example shown in Fig. 4, one row in the memory cell array 1 includes 256-bit memory cells and a horizontal line on the display screen consists of 256 dots. Each memory cell position in Fig. 4 is designated by a hexadecimal number.

The SAM register 6 comprises a number of register elements corresponding to the number of columns in the memory cell array 1 , and during data transfer operation, the data of one row in the memory cell array are simultaneously and directly transferred to the SAM register 4 . Therefore, the addresses in the column direction (column addresses) of the memory cell array 1 and the read addresses of the SAM (ie select addresses of the SAM register) have a 1-to-1 relationship.

According to the memory mapping process described above, image data can be processed at a high speed in accordance with the scan sequence of a raster scan type display unit. Therefore, when processing the image data corresponding to the memory mapping shown in Fig. 4, a CPU can make high-speed access to the RAM port to process data by using a high-speed access mode such as a page mode or a static column mode .

Although this high speed access mode does not Speed access in column direction allowed, required the access in the row direction a switching of the signal RAS to change the row address. Changing the row address by switching the signal RAS the control of the RAS and CAS signals for locking the row address and the Column address corresponding to a general DRAM, so that the access speed in the line direction is reduced is compared with that in the column direction.

In addition, in some image processing applications, the image data can be processed with a memory map shown in FIG. 5, in which a row in the memory cell array extends over a plurality of rows on the screen. When processing image data for such a memory map, each row on the screen requires access to each row in the memory cell array 1 . This requires frequent access in the row direction, which leads to the problem that the high-speed access mode generally provided in the RAM port as described above cannot be used effectively.

Fig. 5 illustrates an example of the memory map in which one row in the memory cell array corresponds to four rows on the display screen.

In addition, even if the data in the memory cell array 1 were processed by the RAM port in accordance with the memory map described above, the SAM port has a structure that sequentially outputs the data corresponding to one row on the display screen, and therefore it would be impossible to read the data from the SAM port serially and display it on the screen without changing the order of the read data. Since further processing such as a change in the arrangement of the data on the display unit is required, image processing systems with simple circuit structures cannot be implemented in this case.

Even if an external device for rearranging the from the SAM port read data could be used, it would be necessary, the line address for each line on the display screen for access by the CPU to the RAM port increase. In this case, access is in the row direction necessary for each line on the display screen, and therefore high-speed data processing cannot be settled.

Japanese Patent Laid-Open No. 61-2 92 676 discloses a structure for moving and partially changing the display pictures. In this state of the art there is an address counter provided at the start addresses of X and Y addresses be determined by external addresses. A counter reading of the Address counter is increased or decreased by a clock signal device. In this prior art, the address counter is called Address generator for designating rows and columns in the Memory cell array is used, and therefore is an optional to accessed the memory cell array impossible.

The aim of the invention is to provide a multi-port RAM of the disadvantages of multi-port RAM described above overcomes the state of the art and is able to high-speed processing of two-dimensional Make image data.

A multi-port RAM is to be created, the memory cells of a row in the memory cell array to a plurality of numbers on a display screen.  

Ultimately, a method for accessing a multi Port RAM can be created at high speed.

A multi-port RAM according to the invention comprises a memory cell lenfeld with a plurality of memory cells in one two-dimensional field are arranged with a data register a plurality of register elements, the simultaneous data Transfer with the memory cells of a row in the memory allow cell field, a counter for counting clock signals and a selection circuit that shows a counter reading of the counter used as a designation signal for a register element and a corresponding register element from the data register selects to connect it to an internal data bus. The counter skips its counter value by a predetermined amount value to output the skipped meter reading. These Operation is repeated until the entire content of the Data register is read out. The count value of the counter is advance by the predetermined value and in response to the clock signal is output. The selection circuit uses the skipped count value of the counter as an address signal for off select the register element from the data register. Therefore, data of a row in the memory cell array in relation to a plurality of lines are set on the display screen will.

Further features and advantages of the invention result itself from the description of an exemplary embodiment of the figures. Show from the figures

Fig. 1 shows an example of a system structure in a general image processing system;

Fig. 2 shows a schematic structure of a conven union dual port RAM;

Fig. 3 is a signal waveform diagram for illustrating a data read operation of a SAM port in a conventional RAM;

4 shows a relationship between the bit positions of a screen of a display unit and a memory cell array in a conventional forth dual-port RAM.

Fig. 5 is a diagram showing a problem with a dual-port RAM according to the prior art;

Fig. 6 shows an example of an overall structure of a dual-port RAM according to an embodiment of the invention;

Fig. 7 is a signal waveform diagram for illustrating the operation of a dual-port RAM according to the invention;

Fig. 8 shows an example of a specific construction of a counter shown in Fig. 6;

Fig. 9A is a signal pulse diagram illustrating the operation of the offset register shown in Fig. 8;

FIG. 9B is a signal pulse diagram illustrating the operation of a counter circuit shown in FIG. 8;

Fig. 10 shows an example of a memory system using a dual-port RAM according to the invention; and

Fig. 11 is a relationship between the bit positions of a display screen of a Anzeigeein integrated and a storage area of OF INVENTION to the invention the dual-port RAM.

Fig. 6 illustrates an example of an overall structure of a dual-port RAM according to an embodiment of the dung OF INVENTION. Identical reference numerals are assigned to the parts of FIG. 6 which correspond to the dual-port RAM shown in FIG. 2. The dual-port RAM shown in Fig. 6 comprises instead of the counter 6 for counting the clock signal SC a counter 6 ', which has an offset function and skips a predetermined counter value during a counting operation.

The counter 6 'comprises a counter circuit 60 , which is activated as a reaction to a transfer command signal, for loading the internal address signal Add, which is applied synchronously with the signal CAS, and which counts the clock signals SC, and an offset register 70 , which in response to that Transfer command signal is activated to load data DQ applied to a data I / O area of a RAM port synchronously with the signal CAS. A transmission signal C of the counter circuit 60 is applied to the offset register 70 . Upon receipt of the carry signal C of the counter circuit 60 , the offset register 70 increases its stored content.

Output signals of the counter circuit 60 and the offset register 70 are applied to the SAM decoder 5 as a register element designation signal for the SAM register 4 . The counter circuit 60 provides the higher order bits of the read address (register designation signal), and the offset register 70 provides the lower order bits of the read address. The counter circuit 60 therefore locks the address signal bits as its start address, except for the bits provided by the offset register 70 , in the internal address signal Add, which is applied by the address buffer 40 .

The address buffer 40 receives externally applied address signal bits A0 to An, and in response to external row address pulse signals and external column address pulse signals, it latches the applied address signals to generate the internal row address signals and the internal column address signals therefrom.

A control unit 50 receives various externally applied signals R /, SC, and to generate internal control signals RAS, CAS, R /, SC and. The operation will now be described with reference to FIG. 7 as the operation pulse diagram.

As in the conventional case, at the time of the signal falling, the transfer command signal is set to "L" and the read / write signal R / is set to "H". This dual-port RAM is therefore intended for a transfer mode. The address buffer 40 responds to the drop of the signal by locking an external address signal of bits A0 to An to generate an internal address signal Add. The row decoder 2 decodes as the row address signal the address signal applied to it in response to the rise of the internal signal RAS, for selecting a row in the memory cell field.

If the signal then drops, the external address signal already applied at the time is locked by the address buffer 40 and applied as an internal column address signal Add to the counter 6 'and the column decoder I / O control circuit 3 .

In response to the rise of the CAS signal, the offset register 70 in the counter 6 'locks the data to the RAM I / O port DQ in order to store this as an offset value (offset). The counter circuit 60 latches predetermined bits of the applied internal address signal Add in response to the signal CAS and stores them as a start address.

When the clock signal SC is subsequently switched, the counter circuit 60 increments its counter value. The SAM decoder 5 deco diert the signal from the counter circuit 60 and the offset register 70 formed counter 6 'as a read address and selects a corresponding register element in the SAM register 4 to this with the internal data bus SO to output the serial data SO connect to.

It is now assumed that the offset register 70 is a 2-bit register, the counter circuit 60 is a 6-bit counter and one row of the memory cell array comprises 1 256 bits ( 0 -255; 00 -FF). In this case, a 6-bit counter value of the counter circuit 60 is used as the high-order address signal bits of the SAM port read address, and the 2-bit data in the offset register 70 are used as the lowest-order read address signal bits of the SAM port.

It is assumed that the data latched by the offset register 70 in response to the rise of the internal signal CAS is 00 .

For example, when the row decoder 2 selects the 0th row in the memory cell array, the 256 bit data on the 0th row in the memory cell array 1 is collectively or simultaneously transferred to the SAM register 4 in response to the transfer command signal. It is also assumed that the column address signal denotes the 0th column in field 1 . In this case, the offset value set in the offset register 70 is 00 and an originally defined value in the counter circuit 60 is an address 00 ... 00 , so that the address in the SAM register 4 is that of the SAM decoder 5 in response to the clock signal SC should be selected from 00 H is.

If the clock signal SC is then applied, the counter value of the counter circuit 60 is increased by 1. At this time, the content of the offset register is still 00 , so that the SAM decoder 5 designates the address 04 H in the SAM port. Then who with each switch of the clock signal SC selects the addresses with an offset of 4 bits, such as the addresses 08 H, 0 CH, 10 H, 14 H, 18 H and 1 CH in succession from the SAM register, and the data of the corresponding register elements who are issued sequentially.

When the counter value of the counter circuit reaches 60 FCH, the display operation of one line on the display screen is ended.

When the counter value of the counter circuit 60 returns from FCF to 00 H, the counter circuit 60 applies the transmission signal C to the offset register 70 . The content of the offset register 70 is increased by 1 in response to the transfer signal C of the counter circuit 60 . The stored content of the offset register 70 becomes 01 H. With each subsequent application of the clock signal SC, the counter value of the counter circuit 60 is increased, and therefore the counter 6 ′ becomes the SAM port read addresses 01 H, 05 H, 09 H, ... describe.

The above-described operations are repeated so that the content of the offset register 70 is increased by 1 every time a line is completely displayed on the display unit screen. When the stored content of the offset register reaches 70 00 H, the data of one row in the memory cell array 1 , which were stored in the SAM register 4 , are completely output. Consequently, it can be said that the SAM register outputs 4 image data for four lines on the screen.

Due to the effect of the offset register 70 with a counter function, the data (for four lines in the embodiment described above) that are developed two-dimensionally on the screen can be continuously output from the memory cells of one line in the memory cell array 1 .

Through the function of the offset register 70 , the reading addresses of the SAM port can be made independent of the column addresses of the RAM port, so that the memory map according to FIG. 5 can be implemented without an external device.

By adding the counter function to the offset register 70 as is the case with the structure described above, data to be displayed two-dimensionally on the screen is represented by the data of one line in the RAM port, so that a high-speed access mode can be used to access the RAM -Access port for image processing, whereby the image data to be displayed can be written to the RAM port at high speed, which results in efficient image data processing.

In the above description, the number of data DQ is 2 bits when the data DQ applied to the RAM port is loaded into the offset register 70 . Since the dual-port RAM can usually be accessed by a multi-bit unit, and a plurality of RAM data I / O ports are provided. For access via a unit of several bits, the memory cell array is usually divided into blocks that correspond to the data bits concerned, and the SAM register 4 is provided corresponding to each block. Even in this case, the same lines are selected from the respective blocks, and the data of one line selected in each block corresponds to one line on the display screen of the display device.

Therefore, in the structure for access via a unit of several bits, it can be said that the memory cell array 1 shown in Fig. 6 constitutes a memory cell array block and that 4 memory cell array blocks are provided. In addition, a plurality of SAM registers corresponding to the respective blocks are provided for access by a unit of multiple bits, and usually the data is read in parallel by these SAM registers.

The counter circuit 60 and the offset register 70 have a specific structure, which will be described below.

In FIG. 8 is an example illustrating a specific configuration of the counter shown in Fig. 6. In FIG. 8, the offset register 70 comprises flip-flops 71 and 72 and an AND gate 73 . The flip-flop 71 has a D input terminal for receiving offset data DQ 0 , a clock input terminal C for receiving a transmission signal C of the counter circuit 60 , an L input terminal for receiving a load command signal DT 1 and a Q output terminal. This flip-flop 71 outputs a least significant read address bit A 0 from the Q output terminal.

The AND gate 73 receives the transmission signal C of the counter circuit 60 and the output signal A 0 of the Q output terminal of the flip-flop 71 .

The flip-flop 72 comprises a D input terminal for receiving the offset data DQ 1 , a C input terminal for receiving the output signal of the AND gate 73, an L input terminal for receiving the code command signal DT 1 and a Q output terminal . This flip-flop 72 outputs a read address bit A 1 from its Q output terminal.

The load command signal DT 1 is generated by an AND gate 74 , which receives the transfer command signal at its negated input and the internal signal CAS at its non-negated input. These flip-flops 71 and 72 work in response to a drop in the signals applied to their clock signal input connections C, for inverting the signal states at their Q output connections. When they receive the load command signals DT 1 at their L input ports, they lock the data applied to their D input ports to transmit to the Q output ports in response to an increase in the data load command signals DT 1 .

Correspondingly, the counter circuit 60 comprises flip-flops 61 , 62 , ..., 63 and AND gates 64 and 65 . The flip-flops 61 to 63 have a structure which corresponds to that of the flip-flops 71 and 71 of the offset register 70 . The flip-flop 61 receives an internal address signal Add 2 at its D input terminal and receives the clock signal SC at its clock signal input terminal C. The flip-flop 61 outputs a read address signal bit A 2 from its Q output terminal.

The flip-flop 62 receives an internal address signal bit Add 3 at its D input terminal and receives a signal passed through the AND gate 64 at its clock input terminal C. The flip-flop 62 outputs a read address bit A 3 from its Q output terminal. The AND gate 64 receives the clock signal SC and the output signal A 2 from the Q output terminal of the flip-flop 61 . The flip-flop 63 receives an internal address signal bit Addn at its D input terminal and receives an output signal of the AND gate 65 at its clock input terminal C. The flip-flip 63 outputs at its Q-output connection the transmission signal C, which is transferred to the offset register 70 , and also outputs a most significant address signal bit An. The AND gate 65 receives the clock signals SC and the Q output signals of all higher-level flip-flops (which output the read address signal bits A 2 to An-1). A clock signal input inclusion C of a flip-flop at or below half the third stage in the counter circuit 60 receives, corresponding to the AND gate 65 , an output signal of an AND gate that the output signals of the Q output terminals of all flip-flops of the corresponding further higher) levels received, as well as the clock signals.

The data load command signal DT 2 is generated by an AND gate 66 which receives the data transfer command signal at its negated input terminal and receives the internal signal CAS at its non-negative terminal. This loading command signal DT 2 is transmitted together to the charging inputs L of flip-flops 61 to 63 . The flip-flops 71 , 72 and 61 to 63 invert the outputs Q in response to a fall from the applied to the relevant clock inputs C signals. The counter shown in FIG. 8 operates as described below with reference to FIGS. 9A and 9B, which illustrate its operating pulse diagrams.

First, the operation of the offset register 70 will be described with reference to FIG. 9A. When the data transfer command signal falls to "L", the AND gate 74 allows the internal signal CAS applied to its non-negative input to be passed. Therefore, when the internal signal CAS rises to "H", the flip-flops 71 and 72 latch the data DQ 0 and DQ 2 applied to their D input terminals and output them from their respective Q output terminals. In this operation, the data DQ is applied to the RAM data I / O ports (not shown) in synchronism with the external signal. Therefore, as shown in Fig. 7, the data DQ 0 and DQ 1 set the offset value in the offset register 70 in synchronization with the drop of the control signal

In this state, the read address signal bits A 0 and A 1 correspond to the offset data DQ 0 and DQ 1 , respectively, which are applied by the RAM port. When the clock signal SC is generated, a counting operation is carried out in the counter circuit 60 . When the counter value of the counter circuit 60 returns from a maximum value ( 11 ... 1 ) to the original value ( 00 ... 0 ), the transmission signal C is generated. This transmission signal C is applied to the clock input terminal C of the flip-flop 71 . The flip-flop 71 inverts the state of the output signal A 0 from its Q output terminal in response to the drop of the signal applied to its clock input terminal C. If the count of the counter circuit to reset 60 returns to its original value after it has counted up to the maximum value, the offset register 70 to the outputs of A 1 and A 2 by 0 to 1st Since the AND gate 73 is "H" only then outputs, when "H" - signals are applied to both inputs, the output of the AND gate is not inverted 73, so that the signal A 1 of the Q output terminal of flip-flop 72 remains at 0, ie the original state.

The counter circuit 60 then again performs the counting operation to give off the transmission signal C. The AND gate 73 outputs the signal "H" because the transmission signal C and the signal A 0 are at "H". When the transmission signal C falls, the flip-flop 72 inverts the state of the signal A 1 at its Q output terminal to "H". The flip-flop 71 inverts the state of the signal A 0 at its Q output terminal to "L" in response to the drop in the transmission signal C. By repeating this operation, the output signals A 1 and A 0 of the offset register 70 repeat the sequence from 00, 01, 10, 11 and 00 , where "0" corresponds to a potential with "L" level and "1" speaks ent with a potential with "H" level.

The operation of the counter circuit 60 will now be described with reference to FIG. 9B. In this counter circuit 60 , the rise in the internal signal CAS also causes the load command signal DT 2 of the AND gate 60 to rise to "H". Consequently, the flip-flops 61 to 63 can lock the address signal bits Add 2 to Addn applied to their respective D input connections as set initial values, and can also output these from the Q connections as the initial value of the SAM read addresses.

Whenever the clock signals SC thereafter rise to "H", the SAM decoder 5 serves to sequentially read the content of the SAM register 4 . Each time the clock signal SC drops, the state of the signal A 2 of the Q output terminal of the flip-flop 61 is inverted. Even if the signal A 2 rises to "1" for the first time in response to the drop of the clock signal SC, the output signal of the AND gate 64 remains at "L" potential since one of the two outputs of the AND gate 64 is already open "L" stands (the clock signal SC was at "L"). Therefore, the outputs of the AND gates 64 and 65 remain at "L", and the signals A 3 to An at the Q output terminals of the flip-flop 63 of a higher order than this flip-flop 62 retain their original states.

When the clock signal SC drops for the second time, the signal A 2 of the flip-flop 61 falls to "L". During a second "H" - period of the clock signal SC, the AND gate 64 has covered an off output signal of "H", and this output signal of the AND Gat ters 64 is in response to the fall of the signal A 2 in. As a result, the state of the signal A 3 of the Q output terminal of the flip-flop 62 is inverted to "H". When the clock signal SC falls 2 ^n-1 times when the above operations are repeated, the most significant read address signal bit An falls from "H" to "L", and the counter circuit 60 returns to the original state. The signal An rises from "L" to "H" when the clock signal SC rises 2 ^n-1 times.

The structure described above can be set to Off realize set function.

As shown in Fig. 8, the internal address signal bits Add 2 to Addn are used as the originally set value, the data DQ 1 and DQ 1 applied to the RAM I / O data bus are used as the data determining the offset, and the output besignal of the offset register 70 and the output signal of the address counter 60 are used as a read address signal of the two lowest rigorous bits or as the most significant read address signal bits A 2 to An, which are to be applied to the SAM decoder 5 . The structure creates the counter circuit, in which the counter jumps by 4 bits, each time the clock signal is applied.

The structure of the counter circuit with offset function is not limited to that shown in FIG. 8. Such a circuit structure can be realized, for example, by using two binary counters to be assigned separately and using them independently as offset register and counter circuit 60 , and a transmission signal from counter circuit 60 causes the offset register to be counted. This structure can realize the same advantages as the illustrated embodiment.

In addition, the counter circuit shown in Fig. 8 increments the count value in response to the clock signal SC, and the offset register performs the counting operation by using the transmission signal of the counter circuit as the clock signal. Alternatively, the counter may have a structure in which the counter circuit 60 decrements its content in response to the clock signals SC and generates the transfer signal to the offset register 70 when it reaches its minimum target value, the offset register also performing a countdown. With this structure, the same advantages as in the illustrated embodiment can be realized.

In the embodiment described above, the memory cells for one line are distributed over four lines on the display screen. Data in a row of memory (storage device) therefore only corresponds to a quarter of the screen. In this case, four dual-port RAMs having the same configuration as shown in Fig. 10 can be used, and each of them can be configured to correspond to a quarter of an area on the display screen.

As shown in Fig. 10, dual-port memories M 1 , M 2 , M 3 and M 4 have identical structures and are provided in parallel to each other so that they are addressed sequentially or simultaneously by the CPU 100 , and output data of these memories M 1 to M 4 are provided so that they can be read out and transmitted sequentially to the CRT 106 . Although the number of dual-port RAMs increases, a storage capacity of each dual-port RAM can be reduced to a quarter compared to the conventional structure, so that the total storage capacity is substantially the same as the conventional structure.

In the memory structure shown in FIG. 10, the CPU 100 outputs the data and the address in accordance with the memory transfer operation described in FIG. 5. In this operation, the memories M 1 to M 4 are addressed sequentially or simultaneously by the CPU, depending on the structure of this memory system. If a CPU data bus width is four times the I / O bus of the RAM data in each of the memories M 1 to M 4 , parallel and simultaneous access is possible. In both cases of simultaneous access or sequential access, each of the dual-port RAMs M 1 to M 4 writes the data for four lines of the display screen with respect to the same line, so that the high-speed access mode provided in the RAM port for that High speed data writing can be used. To transfer data from the dual-port RAMs M 1 to M 4 to the CRT 16 , the data can be read sequentially from the relevant dual-port RAMs, or they can be read simultaneously from the RAMs M 1 to M 4 . In the second case, the data is z. B. stored in a shift register and are then sequentially read out in a predetermined order.

The memories M 1 to M 4 of the memory system shown in FIG. 10 and the display screen of the CRT have a relationship shown in FIG. 11. As shown there, the dual-port RAMS correspond to M 1 through M 4 quarter areas on the CRT display screen.

Fig. 10 illustrates the structure with four dual port RAMs provided in parallel. Alternatively, these four memory cell fields and the SAM registers can be integrated on a semiconductor chip, in which case each memory area is assigned to a SAM register for independent operation such that the data can be processed in each of the quarter areas and successive data from each quarter area can be read out in parallel or in series. In addition, these SAM registers can be constructed so that they can be activated sequentially with the corresponding memory areas, for serial readout of the data, which enables the readout of the data at high speed.

Even in this case, the CPU can store data for four lines write by clicking on each line in each memory area is accessed at the same time so that a high speed processing of the image data can be realized.

Although in the embodiments described in detail above the offset register and counter have been specifically written with a width of 2 bits or 6 bits, these bit values can be chosen arbitrarily. Due to the structure according to the invention, the number of bits of the read address skipped by the offset register is 2 ⁿ bits, where n is a data bit number of the offset register.

In the operating pulse diagram shown in FIG. 7, the data DQ applied to the RAM port are locked in the offset register as a reaction to the rise in the internal signal CAS. Alternatively, the address bits Add 0 and Add 1 , which are applied synchronously with the rise of the signal CAS, can be used for the offset, or a structure can be used with which to the data I / O connection of the RAM port created data DQ are locked when the internal signal RAS rises. In this case, the circuit structure shown in Fig. 8 is changed so that the internal signal RAS is applied to the non-inverted input terminal of the AMD gate 74 instead of the internal signal CAS.

As offset data applied to the offset register, the Data of the RAM data input terminal is used, whereby the Vor see an additional connection is prevented. If however, with a dual-port RAM in the case, a free con clock connection exists, this connection can be used as an offset Data input connection can be used.

In the embodiment described above, the dual Port RAM described as an example. Any multi- Port RAM with a plurality of RAM data entry areas and SAM data I / O ports can be used for the above described embodiments reali sieren.

As described in the previous section, this invention data read out while the read addresses of the SAM port skipped by the predetermined distance in the multi-port RAM so that the column addresses of the RAM port and the Read addresses of the SAM port are made independent of each other  that can, and there can be a correspondence between one Line in the RAM port and a plurality of lines in the picture screen of the display unit can be produced, thereby creating a two-dimensional processing of image data using of high speed access mode realized on the RAM port becomes. The processing of data one line in the RAM port ent speaks of processing data for a plurality of times len on the screen of the display unit, so that the two dimensional image data efficiently at high speed can be processed.

Claims (11)

1. Multi-port memory for random access with a RAM port for random access, a SAM port for serial access and an internal data bus (SO) for serial input and output of data from or to the outside with
a memory cell array ( 1 ) with a plurality of memory cells arranged in the form of a two-dimensional array of rows and columns,
a data register device ( 4 ) with register elements, the number of which is determined by the fact that simultaneous transfer of memory cell data of one row in the memory cell array ( 1 ) is made possible,
a counting device counting clock signals ( 6 ') and
a selection device ( 5 ) which receives counting data of the counting device ( 6 ′) as a register element selection signal for sequentially selecting the register elements in the data register device ( 4 ), for connecting each register element to the internal data bus (SO),
wherein the counting device ( 6 ') comprises a counter value generating device ( 60 , 70 ) for generating counter values which jump by a predetermined value and which change sequentially in response to the clock signal until all register elements of the data register device ( 4 ) are selected. 2. Multi-port memory according to claim 1, characterized in that the counter value generating device comprises a first counting device ( 70 ) for setting the predetermined value and a second counting device ( 60 ) for counting the clock signals, and
a counter value of the first counter device ( 70 ) and a counter value of the second counter device ( 60 ) are applied in parallel to the selection device ( 5 ) as a register element selection signal. 3. Multi-port memory according to claim 2, characterized in that the second counter device ( 60 ) comprises a device ( 63 ) for generating a limit value detection signal when a counter value of the second counter device ( 60 ) reaches a limit value, and the first counter device ( 70 ) comprises a device ( 71 , 72 ) for counting the limit value detection signal. 4. Multi-port memory according to claim 2 or 3, characterized in that the first counter device ( 70 ) comprises a binary counter ( 71 , 72 ) with n bits and the n bits indicate the jump to the predetermined value. 5. Multi-port memory according to one of claims 2 to 4, characterized in that the register element selection signal comprises a plurality of address bits, and the counter value of the first counter device ( 70 ) and the counter value of the second counter device ( 60 ) the select device ( 5 ) are created as lower-value address bits or as higher-value address bits of the register element selection signal. 6. Multi-port memory according to one of claims 1 to 5, characterized in that the memory stores data to be displayed on a screen (CRT) of a display unit in horizontal lines, and the memory cell array ( 1 ) in one of its Lines stores the data to be displayed over a plurality of horizontal lines of the screen in sequential order of the lines along this one line. 7. Multi-port memory according to one of claims 1 to 5, characterized in that the memory cell array ( 1 ) stores data to be displayed on a screen of a display unit, the screen having horizontal lines, and the memory cell array ( 1 ) in one of its Lines stores the data for 1 / k of a horizontal line, where k is the predetermined value. 8. Multi-port memory according to one of claims 2 to 7, characterized by a device ( 66 , 74 ) for setting initial values for the first and second counter devices ( 70 , 60 ) in response to a data transfer command signal, the one Data transfer from the memory cell array ( 1 ) to the register device ( 4 ) indicates. 9. Image processing system with
a display unit with a screen (CRT) which has scanning lines in the horizontal direction and is divided into k small areas along the horizontal direction,
k memory blocks (M 1- M 3 ), one of which is provided for each small area and each have a memory cell array ( 1 ) which is formed from a plurality of memory cells arranged in rows and columns,
a first counter device ( 60 ) for counting clock signals (SC), which comprises a device ( 63 ) for generating a limit value detection signal when a counter value of the first counter device ( 60 ) reaches a limit value,
a second counter device ( 70 ) with an n-bit binary counter ( 71 , 72 ) for counting the limit value detection signals, where k = 2 ⁿ ,
a register device ( 4 ) for storing data of one row in the memory cell array ( 1 ), the register device ( 4 ) having a plurality of register elements for storing data from each of the columns, and
a selection device ( 5 ) which receives counter values of the first and second counter devices ( 60 , 70 ) as a register element selection signal and selects a corresponding register element in the data register device ( 4 ) in order to connect it to an internal data bus (SO),
wherein data on the internal data bus (SO) are displayed sequentially on a corresponding area of the screen (CRT). 10. The image processing system according to claim 9, characterized by a device ( 66 , 74 ) for setting initial values in the first and second counter devices ( 60 , 70 ) in response to a data transfer command signal that transfers data from the memory cell array ( 1 ) to Register device ( 4 ) indicates. 11. A method of accessing a multi-port memory with random access with a RAM port for random access and a SAM port for serial access, the multi-port memory,
has a memory cell array ( 1 ) which is formed from a plurality of memory cells arranged in a matrix of rows and columns,
a register device ( 4 ) having a plurality of register elements for storing data of one line in the storage cell field ( 1 ), and
has an internal data bus (SO) provided in the SAM port,
with the steps
Counting externally applied clock signals (SC) and
Selecting a register element in the register device ( 4 ) corresponding to a counter value of the clock signals for connecting it to the internal data bus (SO), the counting step comprising the steps of
sequentially counting the clock signals with a predetermined value to be jumped, and
Resuming the counting of the clock signals with the predetermined value to be jumped after changing an initial counter value for counting the clock signals after reaching a counting limit value,
includes.