DE4113756A1 - Field effect-controllable semiconductor device - has insulation layer to prevent switch-on of bipolar structure - Google Patents

Field effect-controllable semiconductor device - has insulation layer to prevent switch-on of bipolar structure

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Publication number
DE4113756A1
DE4113756A1 DE4113756A DE4113756A DE4113756A1 DE 4113756 A1 DE4113756 A1 DE 4113756A1 DE 4113756 A DE4113756 A DE 4113756A DE 4113756 A DE4113756 A DE 4113756A DE 4113756 A1 DE4113756 A1 DE 4113756A1
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Prior art keywords
zone
source
insulating layer
insulation layer
source region
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DE4113756A
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DE4113756C2 (en
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Jens-Peer Stengl
Jenoe Dr Tihanyi
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Siemens AG
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Siemens AG
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
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    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
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    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
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    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
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    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
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    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0856—Source regions
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
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    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform

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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A field effect-controllable semiconductor device has a semiconductor body with two main faces (5,6), the first (5) of which adjoins a first conductivity type source region (4) adjacent a second conductivity type gate region (3), the novelty being that an insulation layer (7) is adjacent the source region (4) at a location between the source region (4) and the second main face (6). The insulation layer (7) may be a silicon oxide or a silicon nitride layer having at least the same lateral dimensions as the source region (4) and pref. being less than 1 micron thick. The source region (4) is pref. electrically connected to the gate region (3). USE/ADVANTAGE - The device may be a MOS transistor, a field effect-controlled thyristor or an IGBT, esp. a vertical MOSFET, a lateral MOSFET or a lateral MOSFET and a CMOSFET. The insulation layer prevents or at least hinders switch-on of the bipolar structure, thus preventing latch-up or sec. breakdown.

Description

Die Erfindung bezieht sich auf ein durch Feldeffekt steuer­ bares Halbleiterbauelement mit einem Halbleiterkörper mit zwei Hauptflächen, an dessen erste Hauptfläche eine Source­ zone vom ersten Leitungstyp angrenzt, mit einer an die Source­ zone angrenzenden Gatezone vom zweiten Leitungstyp.The invention relates to a tax through field effect bares semiconductor device with a semiconductor body two main surfaces, on the first main surface of which there is a source zone of the first conduction type, with one adjacent to the source zone adjacent gate zone of the second conduction type.

Halbleiterbauelemente der erwähnten Art können MOS-Transisto­ ren, feldeffektgesteuerte Thyristoren oder IGBT (Isolated Gate Bipolar Transistor) sein. Die erwähnten Bauelemente enthalten wenigstens eine parasitäre bipolare Struktur, die aus der Sourcezone, der Gatezone und einer sich an die Gatezone an­ schließenden Zone besteht, die einen der Gatezone entgegenge­ setzten Leitungstyp hat.Semiconductor components of the type mentioned can MOS-Transisto Ren, field effect controlled thyristors or IGBT (isolated gate Bipolar transistor). The components mentioned contain at least one parasitic bipolar structure resulting from the Source zone, the gate zone and one attached to the gate zone closing zone exists, the one opposite the gate zone set line type.

Bei Überlastung z. B. beim Lawinendurchbruch oder bei zu hohem Strom kann diese bipolare Struktur eingeschaltet werden. Das Einschalten der bipolaren Struktur, die im Fall eines NMOS- Transistors ein npn-Bipolartransistor ist, führt in den meisten Fällen zur Zerstörung des Halbleiterbauelements durch "latch-up" oder "second break down" und muß daher verhindert werden.In case of overload z. B. in avalanche breakdown or too high Current can be switched on this bipolar structure. The Turn on the bipolar structure, which in the case of an NMOS Transistor is an NPN bipolar transistor, leads in most Cases for the destruction of the semiconductor component by "latch-up" or "second break down" and must therefore be prevented.

Der Erfindung liegt die Aufgabe zugrunde, ein Halbleiterbau­ element der erwähnten Art so weiterzubilden, daß ein Einschal­ ten der Bipolarstruktur verhindert oder wenigstens erschwert wird.The invention has for its object a semiconductor construction element of the type mentioned so that a scarf prevented or at least made difficult the bipolar structure becomes.

Diese Aufgabe wird gelöst durch eine zwischen der Sourcezone und der zweiten Hauptfläche des Halbleiterkörpers liegende, an die Sourcezone angrenzende Isolierschicht.This problem is solved by a between the source zone and the second main surface of the semiconductor body insulating layer adjacent to the source zone.

Weiterbildungen der Erfindung sind Gegenstand der Unteransprü­ che.Developments of the invention are the subject of the dependent claims che.

Die Erfindung wird anhand einiger Ausführungsbeispiele in Ver­ bindung mit den Fig. 1 bis 5 näher erläutert. Dabei zeigtThe invention is explained in more detail using some exemplary embodiments in conjunction with FIGS . 1 to 5. It shows

Fig. 1 einen Ausschnitt eines prinzipiellen Ausführungsbei­ spiels und Fig. 1 shows a section of a basic game Ausführungsbei and

Fig. 2 bis 5 Ausschnitte von vier weiteren, speziellen Aus­ führungsbeispielen der Erfindung. Fig. 2 to 5 excerpts from four other, special examples from the invention.

Das Halbleiterbauelement nach Fig. 1 ist auf einem Substrat 1 aufgebaut, auf dem eine Zone 2 angeordnet ist. Die Zone 2 dient als Drainzone. In die Zone 2 ist eine Gatezone 3 planar eingebettet, die an eine erste Hauptfläche 5 des Halbleiter­ körpers tritt. In die Gatezone 3 ist eine Sourcezone 4 einge­ bettet, die ebenfalls an die Oberfläche 5 tritt. Die Leitfähig­ keit ist von der Zone 4 ausgehend n⁺pn⁻n⁺. An die Sourcezone 4 grenzt eine Isolierschicht 7 an. Die Isolierschicht 7 liegt zwischen der Sourcezone 4 und der drainseitigen Hauptfläche 6 des Halbleiterkörpers.The semiconductor device of FIG. 1 is constructed on a substrate 1, is arranged on which a Zone 2. Zone 2 serves as a drain zone. In the zone 2 , a gate zone 3 is embedded planar, which occurs on a first main surface 5 of the semiconductor body. In the gate zone 3 , a source zone 4 is embedded, which also occurs on the surface 5 . The conductivity is n⁺pn⁻n⁺ starting from zone 4 . An insulating layer 7 adjoins the source zone 4 . The insulating layer 7 lies between the source zone 4 and the main surface 6 of the semiconductor body on the drain side.

Dadurch, daß die Isolierschicht 7 direkt an die Sourcezone 4 angrenzt, kann sich an der Grenze zwischen der Isolierschicht 7 und der Sourcezone 4 kein pn-Übergang ausbilden. Ein pn-Über­ gang kann sich nur dort ausbilden, wo die Sourcezone 4 an eine Kanalzone 8 anstößt, die Teil der Gatezone 3 ist und die unmit­ telbar unter der Oberfläche 5 des Halbleiterkörpers liegt. Der pn-Übergang ist mit 19 bezeichnet. Die Hauptfläche 5 ist minde­ stens über der Kanalzone 8 mit einer Oxidschicht 9 versehen, auf der eine Gateelektrode 10 angeordnet ist.Characterized in that the insulating layer 7 is directly adjacent to the source zone 4, can not form a pn junction at the boundary between the insulating layer 7 and the source region. 4 A pn junction can only form where the source zone 4 abuts a channel zone 8 , which is part of the gate zone 3 and which lies immediately below the surface 5 of the semiconductor body. The pn junction is designated 19 . The main surface 5 is at least least provided over the channel zone 8 with an oxide layer 9 on which a gate electrode 10 is arranged.

Wird an die mit der Sourcezone 4 und dem Substrat 1 verbunde­ nen Anschlüsse 12, 13 eine Source-Drain-Spannung angelegt und an den mit der Gateelektrode 10 verbundenen Gateanschluß 11 eine Gatespannung, so bildet sich unter der Gateelektrode 10 in der Kanalzone 8 ein Kanal aus und der MOS-Transistor lei­ tet. Da die Sourcezone 4 nun gemessen an ihrer gesamten Fläche nur noch einen kleinflächigen pn-Übergang 19 hat, ist die Bi­ polarstruktur sehr klein und das Einschalten einer aus den Zo­ nen 4, 3 und 2 bestehenden Bipolarstruktur fällt nicht ins Ge­ wicht. If a source-drain voltage is applied to the connections 12 , 13 connected to the source zone 4 and the substrate 1 , and a gate voltage is applied to the gate connection 11 connected to the gate electrode 10 , a channel is formed under the gate electrode 10 in the channel zone 8 off and the MOS transistor conducts. Since the source zone 4 now has only a small-area pn junction 19 measured over its entire area, the bipolar structure is very small and the activation of a bipolar structure consisting of the zones 4 , 3 and 2 is not important.

Es ist wesentlich, daß die lateralen Abmessungen der Isolier­ schicht 7 mindestens so groß wie die lateralen Abmessungen der Sourcezone 4 sind, so daß die Isolierschicht 7 die Sourcezone 4 überall lateral überragt. Die Isolierschicht 7 kann z. B. durch Implantation von Sauerstoff- oder Stickstoffionen und nachfol­ gendes Aufheizen des Halbleiterkörpers erzeugt werden. Als Implantationsdosis kommen z. B. 1014 bis 1016 Atome/cm2 in Frage. Ein Aufheizen auf eine Temperatur zwischen 800 und 1200°C ge­ nügt zur Bildung eines Siliziumoxids bzw. von Siliziumnitrid.It is essential that the lateral dimensions of the insulating layer 7 are at least as large as the lateral dimensions of the source zone 4 , so that the insulating layer 7 laterally projects beyond the source zone 4 . The insulating layer 7 can, for. B. generated by implantation of oxygen or nitrogen ions and subsequent heating of the semiconductor body. The implantation dose comes e.g. B. 10 14 to 10 16 atoms / cm 2 in question. Heating to a temperature between 800 and 1200 ° C is sufficient to form a silicon oxide or silicon nitride.

Zusätzlich zur Isolierschicht 7 kann die Sourcezone 4 noch elektrisch mit der Gatezone 3 verbunden sein. Dies ist durch die eingezeichnete, nicht näher bezeichnete Leitungsverbindung angedeutet. Die Zonen 3, 4 und die Isolierschicht können strei­ fenförmig oder ringförmig ausgebildet sein. Im übrigen ist die Erfindung nicht auf eine bestimmte Geometrie beschränkt.In addition to the insulating layer 7 , the source zone 4 can also be electrically connected to the gate zone 3 . This is indicated by the line connection, not shown, which is shown. Zones 3 , 4 and the insulating layer can be formed in a strip-like or ring-shaped manner. Otherwise, the invention is not restricted to a specific geometry.

Das Ausführungsbeispiel nach Fig. 2 zeigt die Realisierung eines vertikalen MOS-Transistors. Ist das Substrat statt n⁺-dotiert p⁺-dotiert, ist das Halbleiterbauelement ein IGBT. Auch bei einem IGBT ist es wesentlich, daß die Bildung eines Bipolartransistors unterbunden wird, der aus der Sourcezone 4, der Gatezone 3 und der Zone 2 besteht. Dies wird wieder durch die Isolierzone 7 erreicht, die an die Sourcezone 4 angrenzt und zwischen dieser und der unteren Hauptfläche 6 des MOS-Tran­ sistors bzw. IGBT liegt. Die Gatezone 3 besteht hier aus einem stark dotierten, relativ tief eindiffundierten Teil 15 und einem schwächer dotierten, weniger tief eindiffundierten Teil 16. Das schwächer dotierte Teil 16 enthält die Kanalzone 8.The embodiment of FIG. 2 shows the implementation of a vertical MOS transistor. If the substrate is p⁺-doped instead of n⁺-doped, the semiconductor component is an IGBT. It is also essential for an IGBT that the formation of a bipolar transistor is prevented, which consists of the source zone 4 , the gate zone 3 and the zone 2 . This is again achieved by the isolation zone 7 , which is adjacent to the source zone 4 and between this and the lower main surface 6 of the MOS transistor sistor or IGBT. The gate zone 3 here consists of a heavily doped, relatively deeply diffused part 15 and a weakly doped, less deeply diffused part 16 . The weakly doped part 16 contains the channel zone 8 .

Die Sourcezone 4 und die Gatezone 3 sind über ein Kontaktloch durch eine Sourceelektrode 18 kontaktiert und elektrisch mit­ einander verbunden. Die Sourceelektrode 18 ist auf einer Oxid­ schicht 17 angeordnet. Die Oxidschicht 17 ihrerseits bedeckt die Gateelektrode 10 und die Sourcezone 4.The source zone 4 and the gate zone 3 are contacted via a contact hole by a source electrode 18 and are electrically connected to one another. The source electrode 18 is arranged on an oxide layer 17 . The oxide layer 17 in turn covers the gate electrode 10 and the source zone 4 .

In Fig. 3 ist wieder ein MOS-Transistor mit Vertikalstruktur dargestellt. In die Zone 2 ist eine Zone 20 entgegengesetzten Leitungstyps eingebettet. Auf der Zone 20 ist eine lsolier­ schicht 7 angeordnet, auf der eine Sourcezone 4 liegt. Die Sourcezone 4 ist elektrisch über eine Kanalzone 24 vom der Sourcezone entgegengesetzten Leitungstyp mit einer Epitaxie­ schicht 23 verbunden, die auf der Oberfläche der Zone 2 ange­ ordnet ist. Die Epitaxieschicht 23 ist vom gleichen Leitungs­ typ wie die Zone 2, jedoch höher dotiert als diese. Die Epi­ taxieschicht 23 ist mit der Oxidschicht 9 bedeckt, auf der die Gateelektrode 10 angeordnet ist. Die Sourceelektrode 18 kon­ taktiert gemeinsam die Sourcezone 4 und die Zone 20. Sie ist durch die Oxidschicht 17 gegen die Gateelektrode 10 isoliert. Beim Einschalten des MOS-Transistors fließt der Strom von der Sourcezone 4 durch die Kanalzone 24 und die Epitaxieschicht 23 in die Zone 2, die als Drainzone dient. Die Zone 20 begrenzt den Kanal auf der Unterseite.In Fig. 3, a MOS transistor is illustrated with vertical structure. A zone 20 of opposite conduction type is embedded in zone 2 . On the zone 20 , an insulating layer 7 is arranged, on which a source zone 4 is located. The source zone 4 is electrically connected via a channel zone 24 of the opposite conductivity type to the source zone with an epitaxial layer 23 , which is arranged on the surface of zone 2 . The epitaxial layer 23 is of the same line type as the zone 2 , but doped higher than this. The epi-taxie layer 23 is covered with the oxide layer 9 , on which the gate electrode 10 is arranged. The source electrode 18 contacts the source zone 4 and zone 20 together . It is insulated from the gate electrode 10 by the oxide layer 17 . When the MOS transistor is switched on, the current flows from the source zone 4 through the channel zone 24 and the epitaxial layer 23 into the zone 2 , which serves as a drain zone. Zone 20 delimits the channel on the underside.

Für höhere Sperrspannungen kann die Sourcezone mit einer lateral gegen die Kanalzone 24 abnehmenden Dotierung versehen sein. Dies wird dadurch erreicht, daß die Sourcezone durch eine Spaceroxid­ schicht 25 implantiert wird. Diese Schicht hat an der Grenze zwischen Kanalzone 24 und Sourcezone 4 ihre größte Dicke. Die Dicke nimmt mit steigender Entfernung von der Kanalzone 24 ab.For higher reverse voltages, the source zone can be provided with a doping that decreases laterally against the channel zone 24 . This is achieved in that the source zone is implanted through a spacer oxide layer 25 . This layer has its greatest thickness at the boundary between channel zone 24 and source zone 4 . The thickness decreases with increasing distance from the channel zone 24 .

In Fig. 4 ist ein Lateral-MOS-Transistor dargestellt, bei dem auf der Zone 2 eine schwach dotierte Zone 28 des der Zone 2 entgegengesetzten Leitungstyps angeordnet ist. Die Sourcezone 4 ist in die Zone 28 eingebettet. An die Sourcezone 4 schließt sich wieder eine Isolierschicht 7 an, die zwischen der Source­ zone 4 und der unteren Hauptfläche 6 des Halbleiterbauelements liegt. Die Sourcezone 4 und die Isolierschicht 7 sind in Rich­ tung zur Drainzone 32 von zwei Zonen 29, 30 umschlossen. Sie bilden eine Patentialbarriere zu Elektronen, um die Struktur beim UG = 0 gesperrt zu halten. Die Zonen 29 und 30 sind vom gleichen Leitungstyp wie die Zone 28, jedoch stärker dotiert als diese. An der oberen Hauptfläche 5 des Halbleiterkörpers ist eine Driftstrecke 31 angeordnet, die vom gegenüber der Zone 28 entgegengesetzten Leitungstyp ist. Sie ist mit der Drainzone 32 verbunden. Die Kanalzone liegt zwischen der Sourcezone 4 und der Driftstrecke 31 und ist mit 14 bezeichnet. Die Oberfläche des Halbleiterkörpers ist mit einer Oxidschicht 9 bedeckt, die von der Sourcezone 4 zur Drainzone 32 einen von der Hauptfläche 5 zunehmenden Abstand aufweist. Damit läßt sich die Feldstärke­ verteilung in der Driftstrecke vergleichmäßigen und es lassen sich höhere Sperrspannungen erzielen. Auch bei diesem Ausführungs­ beispiel ist der parasitäre Bipolartransistor weitgehend aus­ geschaltet, der aus der Sourcezone 4, den Zonen 28 und 29 und der Zone 2 besteht.In FIG. 4 is a lateral MOS transistor is shown, a lightly doped region 28 of the opposite conductivity type Zone 2 is located at the on the zone 2. The source zone 4 is embedded in the zone 28 . The source zone 4 is followed by an insulating layer 7 , which lies between the source zone 4 and the lower main surface 6 of the semiconductor component. The source zone 4 and the insulating layer 7 are enclosed in Rich direction to the drain zone 32 by two zones 29 , 30 . They form a potential barrier to electrons to keep the structure locked at U G = 0. Zones 29 and 30 are of the same conductivity type as zone 28 , but more heavily doped than this. Arranged on the upper main surface 5 of the semiconductor body is a drift path 31 , which is of the opposite conduction type to the zone 28 . It is connected to the drain zone 32 . The channel zone lies between the source zone 4 and the drift section 31 and is designated by 14 . The surface of the semiconductor body is covered with an oxide layer 9 , which is at an increasing distance from the main surface 5 from the source zone 4 to the drain zone 32 . This makes it possible to even out the field strength distribution in the drift section and to achieve higher blocking voltages. In this embodiment, too, the parasitic bipolar transistor is largely switched off, which consists of the source zone 4 , the zones 28 and 29 and the zone 2 .

In Fig. 5 ist als Ausführungsbeispiel eine CMOS-Anordnung dargestellt. Sie besteht aus einem NMOS-Transistor mit der Sourcezone 4 und einer Drainzone 35. Beide Zonen sind in eine Zone 34 eingebettet, die gegenüber den Zonen 4 und 35 vom ent­ gegengesetzten Leitungstyp ist. Der NMOS-Transistor wird über eine Gateelektrode 37 gesteuert, die auf einer Oxidschicht 36 angeordnet ist. An die Sourcezone 4 schließt sich wieder die Isolierschicht 7 an, die zwischen der Sourcezone und der unte­ ren Hauptfläche 6 des Halbleiterkörpers angeordnet ist. Damit ist wieder nur jener kleine pn-Übergang 19 wirksam, der unter der Hauptfläche 5 bzw. unter der Gateelektrode 37 sitzt. Der PMOS-Transistor besteht aus einer Sourcezone 40, einer Drain­ zone 41 und einer Gateelektrode 42.In Fig. 5 is a CMOS device is shown as an exemplary embodiment. It consists of an NMOS transistor with source zone 4 and a drain zone 35 . Both zones are embedded in a zone 34 which is opposite the zones 4 and 35 of the opposite conduction type. The NMOS transistor is controlled via a gate electrode 37 which is arranged on an oxide layer 36 . The source zone 4 is followed by the insulating layer 7 , which is arranged between the source zone and the main surface 6 of the semiconductor body. Again, only that small pn junction 19 is effective, which is located under the main surface 5 or under the gate electrode 37 . The PMOS transistor consists of a source zone 40 , a drain zone 41 and a gate electrode 42 .

Die parasitäre Bipolarstruktur würde in diesem Fall aus der Sourcezone 4, der Zone 34 und der Zone 2 bestehen. Ihr Ein­ schalten wird durch die Isolierschicht 7 stark erschwert.In this case, the parasitic bipolar structure would consist of source zone 4 , zone 34 and zone 2 . Your turn on is made very difficult by the insulating layer 7 .

Zum Verhindern der Bildung einer parasitären Bipolarstruktur hat es sich als ausreichend erwiesen, die Isolierschicht 7 dünner als 1 µm, z. B. 0,1 µm dick zu machen.To prevent the formation of a parasitic bipolar structure, it has proven to be sufficient to make the insulating layer 7 thinner than 1 μm, e.g. B. 0.1 µm thick.

Claims (9)

1. Durch Feldeffekt steuerbares Halbleiterbauelement mit einem Halbleiterkörper mit zwei Hauptflächen (5, 6), an dessen erste Hauptfläche (5) eine Sourcezone (4) vom ersten Leitungstyp an­ grenzt, mit einer an die Sourcezone angrenzenden Gatezone (3) vom zweiten Leitungstyp, gekennzeichnet durch eine zwischen der Sourcezone (4) und der zweiten Hauptfläche (6) des Halbleiterkörpers liegende, an die Source­ zone (4) angrenzende Isolierschicht (7).1. A field effect controllable semiconductor component with a semiconductor body with two main surfaces ( 5 , 6 ), on the first main surface ( 5 ) of which a source zone ( 4 ) borders on the first conductivity type, with a gate zone ( 3 ) of the second conductivity type adjacent to the source zone, characterized by a lying between the source region (4) and the second main surface (6) of the semiconductor body, to the source zone (4) adjoining the insulating layer (7). 2. Halbleiterbauelement nach Anspruch 1, dadurch ge­ kennzeichnet, daß die Isolierschicht (7) eine Siliziumoxidschicht ist.2. Semiconductor component according to claim 1, characterized in that the insulating layer ( 7 ) is a silicon oxide layer. 3. Halbleiterbauelement nach Anspruch 1, dadurch ge­ kennzeichnet, daß die Isolierschicht (7) eine Si­ liziumnitridschicht ist.3. A semiconductor device according to claim 1, characterized in that the insulating layer ( 7 ) is a Si silicon nitride layer. 4. Halbleiterbauelement nach einem der Ansprüche 1 bis 3, dadurch gekennzeichnet, daß die Isolier­ schicht (7) mindestens die gleichen lateralen Abmessungen wie die Sourcezone (4) hat.4. Semiconductor component according to one of claims 1 to 3, characterized in that the insulating layer ( 7 ) has at least the same lateral dimensions as the source zone ( 4 ). 5. Halbleiterbauelement nach einem der Ansprüche 1 bis 4, dadurch gekennzeichnet, daß die Isolier­ schicht eine Dicke von weniger als 1 µm hat.5. Semiconductor component according to one of claims 1 to 4, characterized in that the insulating layer has a thickness of less than 1 micron. 6. Halbleiterbauelement nach einem der Ansprüche 1 bis 5, dadurch gekennzeichnet, daß die Source­ zone (4) elektrisch mit der Gatezone (3) verbunden ist.6. Semiconductor component according to one of claims 1 to 5, characterized in that the source zone ( 4 ) is electrically connected to the gate zone ( 3 ). 7. Halbleiterbauelement nach einem der Ansprüche 1 bis 6, dadurch gekennzeichnet, daß es ein Vertikal-MOSFET ist. 7. Semiconductor component according to one of claims 1 to 6, characterized in that it is a Vertical mosfet is.   8. Halbleiterbauelement nach einem der Ansprüche 1 bis 6, dadurch gekennzeichnet, daß es ein Lateral-MOSFET ist.8. Semiconductor component according to one of claims 1 to 6, characterized in that it is a Lateral MOSFET is. 9. Halbleiterbauelement nach einem der Ansprüche 1 bis 6, dadurch gekennzeichnet, daß es einen Lateral-MOSFET und einen komplementären MOSFET enthält.9. Semiconductor component according to one of claims 1 to 6, characterized in that there is a Contains lateral MOSFET and a complementary MOSFET.
DE4113756A 1991-04-26 1991-04-26 Semiconductor component controllable by field effect Expired - Fee Related DE4113756C2 (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0726602A2 (en) * 1995-02-09 1996-08-14 Mitsubishi Denki Kabushiki Kaisha Insulated gate semiconductor device
EP0750351A2 (en) * 1995-06-19 1996-12-27 Siemens Aktiengesellschaft MOS semiconductor device with improved m-characteristics
DE19741972C1 (en) * 1997-09-23 1998-09-17 Siemens Ag Silicon-on-Isolator cells, e.g. for IGBT, MOS controlled thyristor, FET power semiconductor

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
IEEE Electron Device Letters, Vol. 9, No. 1, January 1988, pp 29-31 *
IEEE Transactions on Electron Devices, Vol. 36, No. 9, September 1989, pp. 1824-1829 *

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0726602A2 (en) * 1995-02-09 1996-08-14 Mitsubishi Denki Kabushiki Kaisha Insulated gate semiconductor device
EP0726602A3 (en) * 1995-02-09 1996-09-04 Mitsubishi Electric Corp
US5623152A (en) * 1995-02-09 1997-04-22 Mitsubishi Denki Kabushiki Kaisha Insulated gate semiconductor device
EP0750351A2 (en) * 1995-06-19 1996-12-27 Siemens Aktiengesellschaft MOS semiconductor device with improved m-characteristics
EP0750351A3 (en) * 1995-06-19 1997-02-05 Siemens Ag
DE19741972C1 (en) * 1997-09-23 1998-09-17 Siemens Ag Silicon-on-Isolator cells, e.g. for IGBT, MOS controlled thyristor, FET power semiconductor
US6225643B1 (en) 1997-09-23 2001-05-01 Infineon Technologies Ag SOI cell and method for producing it

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