DE4106784C2 - Signal processor for use in a digital radio telephone - Google Patents

Description

The invention relates to a signal processor one for generating addresses for a storage unit serving addressing unit that an address register order and contains a decoder that is dependent a program command during the execution of a pro or an interrupt cycle (interrupt cycle) to release a Registers of the address register arrangement for reading or Address writing is provided.

Signal processors are special microcomputers for real time applications. Such a signal processor, the z. B. from the essay "Connected Europe - high-tech DSP brings new light in mobile telephony "by P. McAlinden and D. Hartley, Electronics 25/1990, pages 46 to 52 is used, for example, in a mobile radio telephone for speech coding and decoding, equalization, Synchronization etc. The processor usually includes a storage unit, an addressing unit for Er generation for addresses for the storage unit, a data processing unit for performing arithmetic and logical operations, peripheral devices, a pro gram storage unit and a control unit, coupled are the units via at least one program bus and a data bus. The units are connected via the program bus Program commands and data words added via the data bus leads. There are also connections between individual units via control lines.  

In a signal processor one is used by a user given program executed. When processing a Such a program contains, among other things, certain data read from the storage unit, written and white processed. Here, the data that is output read will be addressed via an address. For Forming such an address is used for addressing unit, which has at least one decoder and one address contains a arrangement with several address registers. The The decoder receives a binary coding via a program bus program command that it executes. Here, a Address register for writing or reading addresses serve. The address for a is in the program command Address register included. To avoid a program command The number of address registers is large limited. In modern signal processors are high at least four address registers are available, i. H. two binary are in the program instruction for the address one Address register reserved. The read address can to create a new address using an arithmetic / logical unit can also be changed.

A program executed by the signal processor can by an interrupt (program interruption) e.g. B. for Execution of an input / output operation interrupted the. In this case, the processing of the current Program interrupted and an interrupt subroutine started. After the end of the interrupt subroutine the signal processor moves with the program sequence on the Resume where the program was interrupted was interrupted.

To execute an interrupt subroutine usually need addresses from the addressing unit does. These addresses for interrupt subroutines are in Address registers are saved or they have to be used  dige program operations from other memory areas of the signal processor in the Address register can be fetched. In the first case, some of the address registers can only be used for the normal program flow can be used because the other address register addresses included for interrupt subroutines. This makes certain operations time consuming to execute because certain addresses from other memory areas of the Signal processor must be brought to an address register. In the second case it takes Computing time longer, because only addresses of the normal program from address registers must be read out and saved and then new addresses for the Interrupt subroutine must be fetched into the address register. At the end the reverse subroutine requires a reverse process. Because this means that Computing time is increased, there may be problems with certain operations that occur in Must be run in real time.

A processor with "checkpoint retry" is also known from US Pat. No. 4,912,707 mechanism ", which includes a shadow status register contains. This register is intended for storing the content of a status register, when a new address value is stored in a particular address register.

The invention is therefore based on the object of providing a signal processor which with the program flow without additional major time-consuming operations the register arrangements.

This problem is solved in a signal processor of the type mentioned at the outset by
that the address register arrangement contains a main address register part and a shadow address register part,
that after an interrupt the decoder is provided for releasing a register of the shadow address register part which is intended for storing the start address of an interrupt cycle, and
that at the end of an interrupt cycle the decoder is intended to release the register of the address register arrangement which is provided for writing or reading before the interrupt.

The shadow address is used in this signal processor register part in the address register arrangement essentially for storing addresses for the interrupt subpro gram. If there are still address registers in the shadow address register parts are freely assignable, they can be used in normal Program sequence can be used. To distinguish the Address register parts in the normal program flow could be there ago an additional program command before the address program order related to the ghost arrangement. On such an additional program command requires a great deal less time than the program instructions for Holvor Previously, operations and backup processes of addresses were required are such. The number of address registers has increased the measure according to the invention increases, although a Enlargement of the binary digits for an address of a Address register in the program instruction is not required. This increases the size of the program storage unit not necessary. At an address there will be an address register in the main address register part or an address register in the Shadow address register part addressed. The shadow- Address register part is selected if an interrupt is present. A register of the shadow address register part can also be used in a normal program flow the. For this, however, as mentioned above, special Be missing necessary.

In an address register of the shadow address register part a start address of an interrupt cycle is saved chert. This starting address is the first time at Ini Initialization of the signal processor via an initialization program into the address register of the shadow address enrolled in part. This start address can be un remain changed or during an interrupt cycle be changed and as a newly formed starting address available for the next interrupt cycle hen. After the end of the interrupt cycle, the sig  processor continues with the program sequence at the point, at which he was interrupted. This will be done before Interrupt registers intended for writing or reading addressed the address register arrangement again. By the above measures are not time-intensive sive operations required.

In a program command to process a program or also in a program command, which after a Interrupt in a called interrupt subroutine is an address for an address register available. This address applies to an address register in the Main address register part and in the shadow address register part. The address registers are selected after opening join an interrupt or other program instructions the execution of a program. This selection can e.g. B. in the decoder. Another one Embodiment is provided that the outputs of the Main address register part with a first input and the Shadow address register part outputs with a two th input of a first one controlled by the decoder Multiplexer is coupled, whose output with the Spei chereinheit is coupled, and that the decoder to the delivery a control command to the first multiplexer seen the one in the address register arrangement relevant program command optionally for coupling the first or second input with the output of the first Multiplexers and with an interrupt to couple the second input with the output of the first multiplexer serves.

This means that the write outputs of the two addresses register parts optionally coupled with a storage unit pelt. The coupling of the two inputs of the first Multi plexers with its output depends on one from the decoder delivered control command. If there is an Inter  rupts is the second input of the first multiplexer coupled to its output. With the exit of the first Multiplexers can also be an arithmetic / logic unit be coupled, which from an address register read address changed and as new address the Address register feeds again.

In the event of an interrupt, the control command issued by the Decoder is fed to the first multiplexer that the second input with the output of the first multiplexer is coupled. Control of the first multiplexer at a program can have an additional program failed. It is provided that at least before the first occurrence of the address register arrangement program command with a loader command a control register to load a data word is determined and that a bit of this data word controls Command of the decoder in the absence of an interrupt certainly. The decoder evaluates the bit of the data word and then forms the corresponding control command for the first multiplexer. It can be provided here that the bit of the data word which the control area The program with the least significant bit failed is.

In a further embodiment it is provided that the Output of the control's least significant memory cell registers is coupled to the decoder and that the one corridor of the least significant memory cell with one output a second multiplexer is coupled, the first Input for feeding the least significant bit of the Data word and its second input for feeding a bit is provided, which the decoder for Bil a control command caused by an interrupt. In the event of an interrupt, the decoder becomes the second multi  plexer switched so that it instead of the low value most bits of the data word reads in a bit from which the control command is generated in the event of an interrupt. The Decoder evaluates when processing a program and likewise in the case of an interrupt cycle the bit which is in the least significant memory cell of the control register stands, and then determines the control command for the first multiplexer.

It can happen that during an interrupt cycle another interrupt cycle begins. So the content the least significant memory cell of the first made Interrupt cycle is not lost, is provided that when another interrupt occurs during of an interrupt cycle, a reserve memory for on write the in the least significant memory cell of the Control register located bits is provided and that at the end of the last interrupt cycle that bits for enrollment stored in the reserve memory in the least significant memory cell of the control room sters is determined. If more than two are nested Interrupt cycles occur, the reserve memory is used Registration of the in the least significant memory cell bits of several of the control register Interrupt cycles provided. The number of memory cells the reserve memory should be chosen so large that they are at least equal to the number of interrupt sources is. An interrupt source is, for example, an on / Output unit. The registration and readout of the bits from the reserve memory can reali in a simple manner be siert by the reserve memory at Ein Write the bits to work according to the shift register principle and for reading out the last registered Bits is provided at the end of an interrupt cycle.  

Due to the measures according to the invention in the Addressing unit of the signal processor is this especially suitable for real-time requirements. In the Telecommunications, especially in the mobile radio area real-time requirements occur with this Signal processor can be solved. Hence the Signal processor for use in a digital Radio telephone particularly suitable.

An embodiment of the invention is shown below explained in more detail with reference to the drawings. Show it

Fig. 1 is a block diagram of a digital mobile phone with a signal processor,

Fig. 2 is a block diagram of the signal processor used in Fig. 1 and

Fig. 3 shows an embodiment of an addressing unit used in Fig. 2 in a signal processor.

The block diagram of a digital radio telephone shown in FIG. 1 contains a transmission and reception path. The voice signals received by a microphone 1 are converted into binary coded data words via an analog-digital converter 2 . These data words are fed to a signal processor 3 . For the various functions that the signal processor 3 performs, blocks 4 to 10 are shown in FIG. 1 in the signal processor 3 . With the data words generated by the analog-to-digital converter 2 , speech coding is performed in block 4 , then channel coding in block 5 and then encryption in block 6 . These encrypted data words are GMSK-modulated in a modulator 12 . This is connected to an output of the signal processor 3 . The modulated digital signals are then converted into analog modulated signals in a digital-to-analog converter 13 . These modulated analog signals are fed to a transmission circuit 14 which generates radio signals which are radiated via an antenna 15 . The path described so far represents the transmission path of the digital radio telephone.

The reception path of the digital radio telephone is described in the fol lowing. Analog radio signals received by an antenna 16 are processed in a receiving circuit 17 and analog modulated signals are supplied to an analog-to-digital converter 18 . The digitally modulated signals emitted by the analog-to-digital converter are demodulated in a demodulator 19 and supplied to the signal processor 3 . The block 10 in the signal processor 3 is intended to show the subsequent equalization of the demodulated signals. A decryption function is then carried out, which is symbolized by block 9 . After a channel decoding in block 8 and a speech decoding in block 7 , the signal processor 3 forwards digital data words to a digital-to-analog converter 20 , which gives the analog voice signals to a loudspeaker 21 .

The signal processor used in FIG. 1 is shown in somewhat more detail in FIG. 2. The signal processor 3 has an addressing unit 22 in which addresses are formed for a memory unit 23 which contains a ROM and RAM. In a data processing unit 24 , data are processed by means of an arithmetic / logic unit and a multiplier. Furthermore, there is also a control unit 25 and a program storage unit 26 in which a program to be executed is stored in the signal processor 3 .

The units 22 to 26 are connected to one another via a bus system. This bus system consists of a program bus, via which program commands are transmitted, a data bus, via which data words are transmitted, and control lines, via which control information is passed on. Furthermore, a peripheral unit 27 is also coupled to the bus system, via which input / output units are coupled to the bus system via various interfaces. A special unit 28 is also available for certain units and can perform intensive operations at the computing time.

An embodiment of the addressing unit 22 is shown in FIG. 3. This contains an address register arrangement 29 with a main address register part 30 and a shadow address register part 31 . The main address register part 30 and the shadow address register part 31 each contain four address registers. The output of the main address register part 30 is connected to a first input 32 of a first multiplexer 33 and the output of the shadow address register part 31 is connected to a second input 34 of the first multiplexer 33 . The output 35 of the first multiplexer 33 is coupled to an arithmetic / logic unit 36 and the memory unit 23 not shown here. The first multiplexer 33 is controlled by means of a control command ST from a decoder 37 , which consists of basic logic elements (AND, OR, EXOR, NAND, NOR gates and other gatters). Control signals A1, A2, RWS and RWH are fed to address register parts 30 and 31 via four further control connections 38 , 39 , 53 and 54 .

The output of the arithmetic / logic unit 36 has a connection to a first input 40 of a third multiplexer 41 . The second input 42 of the third multiplexer 41 is connected to the data bus. The third multiplexer 41 is controlled via a control signal M3 from the decoder 37 . The output 43 of the third multiplexer 41 is coupled to the two inputs of the address register parts 30 and 31 .

To explain the operation of the previously described elements in the addressing unit 22 , the following should be noted. A logical "1" is hereinafter referred to as "1" and a logical "0" is referred to as "0".

The control signals A1 and A2 identify an address of both address register parts 30 and 31 . The control signals RWS and RWH indicate whether reading out and / or writing in. If both control signals RWS and RWH are set to "1", both a register of the main address register part 30 and a register of the shadow address register part 31 are read out. If one of the two signals RWS and RWH "0" is set, is read from a register of the address register parts 30 and 31, specifically from the register whose address register part 30 or 31 receives "0". This read address can then be modified in the arithmetic / logic unit 36 . The address is modified or unmodified in the same register again. If necessary, an address from the data bus is also written via a second multiplexer 41 .

If an address is to be read from the shadow address register part 31 , the control signals RWS and RWH with the value "1" are supplied by the decoder 37 via the connections 53 and 54 . The two other control signals A1 and A2 identify a specific address register in the address register parts 30 and 31 . Addresses from the two address register parts 30 and 31 are present on the lines leading to the first input 32 and to the second input 34 of the first multiplexer 33 . Which address is given to the output 35 of the first multiplexer 33 depends on the control command ST. Since an address from the shadow address register part 31 is to be given to the output 35 , the control command ST is set to "1". This means that the second input 34 is connected to the output 35 . If the control command ST is "0", the first input 32 is connected to the output 35 . The address at the output 35 can now be processed further to the memory unit 23 or from the arithmetic / logic unit 36 . If the address is e.g. B. after a modification to be returned to the same register, the third multiplexer is influenced by the control signal M3, ie logically equal to "1", that its first input 40 is connected to its output 43 .

In the addressing unit 22 , a control register 44 , a second multiplexer 45 and a reserve memory 46 are also included. The first input 47 of the second multiplexer 45 is connected to the line of the data bus, which transports the least significant bit of a data word. A logic "1" is supplied to the second input 48 of the second multiplexer 45 . The output 49 of the second multiplexer 45 is connected to the least significant memory cell 50 of the control register 44 . The second multiplexer 45 is controlled by means of a signal M2 from the decoder 37 . A control signal MK also receives the least significant memory cell 50 from the decoder 37 . The output of the least significant memory cell 50 is connected to the reserve memory 46 and to the decoder 37 . The reserve memory 46 is still controlled by means of two control signals R1 and R2 from the decoder 37 . The decoder 37 is also connected to the program bus. A program command which is fed from the program bus to the decoder 37 can be processed in the decoder 37 if another control signal PF to be supplied to the decoder 37 indicates this. If a program is interrupted by an interrupt, this indicates an interrupt start signal IS and the end of an interrupt cycle indicates an interrupt end signal IE. Both signals IS and IE are fed to the Deco 37 on additional lines.

If an address is to be used in a program sequence from an address register part 30 or 31 , a load command is first sent from the program bus, which can be processed by the decoder 37 if the control signal PF is "1". In this case, the decoder sets the control signal M2 to "0", so that the first input 47 of the second multiplexer 45 is coupled to its output 49 . The control signal MK is set to "1", so that the least significant bit NB of a data word is read into the least significant memory cell 50 of the control register 44 . This bit NB is fed to the decoder 37 via the line 51 . If the bit NB contained in the memory cell 50 is "1", the control command ST is set to "1". If the bit NB in the memory cell 50 is "0", the control command ST is set to "0". After the load program command, in a later step the bus program supplies a command with which an action in an address register part 30 or 31 is to be carried out. For example, a program command could result in an address being given to the memory unit 23 from an address register in the address register part 30 .

If an interrupt occurs during a program run, so that IS is set to "1", the program run is interrupted. The decoder then sets the control signal M2 equal to "1" and the value offered by the output 49 of the second multiplexer 45 is read into the memory cell 50 . Before the content of the memory cell 50 is read via line 51 into the reserve storage 46th For this purpose, the control signal R1 is set to "1", which means that the first memory cell in the reserve memory 46 is ready for reading in the bit NB from the memory cell 50 . An interrupt subroutine can now run in the following. Here, all address registers of the address register arrangement 29 can also be used. When an interrupt cycle has ended, the control signal IE is set to "1". Then, the control signal R1 is equal to "0" and the control signal R2 is equal to "1", which means that the reserve memory 46 is ready to dispense the value contained in the top memory cell of the reserve memory 46 to the memory cell 50th With the control signal bit from the MK, the reserve memory 46 is read into the memory cell 50 via the line 51st The content of the memory cell 50 indicates via line 51 to the decoder 37 which value the control command ST must have. The first multiplexer 33 is switched accordingly. The program starts at the point where it stopped after an interrupt occurred.

Another interrupt may occur during an interrupt cycle. In this case, the current interrupt cycle is interrupted and a new interrupt cycle begins. Here, at the beginning of an interrupt cycle, the interrupt start signal IS is set to "1", a connection is established between the input 48 and the output 49 of the second multiplexer 45 and a new value is read into the memory cell 50 . The value NB previously stored in the memory cell 50 was previously read into the reserve memory 46 . The program of the Pro-derived value in the backup memory 46 is thereby shifted to the shift register principle in an adjacent memory cell of spare memory 46th In this operation, the control signal R1 is set to "1" and the control signal R2 is set to "0". In this way, different interrupt cycles can be interleaved. If the reserve memory 46 has four memory cells, a total of four interleaved interrupt cycles can occur.

As mentioned above, the decoder consists of logic switching elements. In the event of a program command or an interrupt, the outputs and inputs of the decoder 37 have certain logic states. In the following, the logical states are listed in the tables below for the various input and output signals. On the basis of these tables, a decoder 37 with corresponding logic switching elements can be constructed.

The following states occur in a program command for an address register operation in which the memory unit 23 is to be addressed:

The following states occur when an interrupt cycle starts:

The following states occur at the end of an interrupt cycle:

The following states occur with a program command for loading the control register 44 :

The following states occur with a program command for loading an address register:

"x" means that a signal or command has the status "0" or may have "1".

Claims (10)

1. Signal processor ( 3 ) with an addressing unit ( 22 ) for generating addresses for a memory unit ( 23 ), which contains an address register arrangement ( 29 ) and a decoder ( 37 ), which is a function of a program command during the processing of a pro Gram or an interrupt cycle for releasing a register of the address register arrangement for reading or writing addresses is provided, characterized in that the address register arrangement ( 29 ) contains a main address register part ( 30 ) and a shadow address register part ( 31 ) that after an interrupt the decoder ( 37 ) is provided for releasing a register of the shadow address register part which is intended for storing the start address of an interrupt cycle and that at the end of an interrupt cycle the decoder is intended for releasing the register of the address register arrangement which is provided for writing or reading before the interrupt . 2. Signal processor according to claim 1, characterized in that the outputs of the main address register part ( 30 ) with a first input ( 32 ) and the outputs of the shadow address register part ( 31 ) with a second input ( 34 ) of a first of the decoder ( 37 ) controlled multiplexer ( 33 ) is coupled, the output ( 35 ) of which is coupled to the memory unit ( 23 ), and that the decoder is provided for supplying a control command (ST) to the first multiplexer, which in a register arrangement relating to the address address Program command optionally for coupling the first or second input to the output of the first multiplexer and, in the case of an interrupt, for coupling the second input to the output of the first multiplexer. 3. Signal processor according to claim 2, characterized in that at least before the first occurrence of a program instruction relating to the address register arrangement ( 29 ) with a load program instruction, a control register ( 44 ) is determined for loading a data word and that a bit of this data word is the control instruction (ST) of the Decoder ( 37 ) determined in the absence of an interrupt. 4. signal processor according to claim 3, characterized, that the bit of the data word which contains the control command (ST) determined for a program that is the least significant bit. 5. Signal processor according to claim 4, characterized in that the output of the least significant memory cell ( 50 ) of the control register ( 44 ) is coupled to the decoder ( 37 ) and that the input of the least significant memory cell with an output ( 49 ) of a second multiplexer ( 45 ) is coupled, the first input ( 47 ) for supplying the least significant bit of the data word and the second input for supplying a bit is provided, which causes the decoder to form a control command (ST) in the event of an interrupt. 6. Signal processor according to claim 5, characterized in that when a further interrupt occurs during an interrupt cycle, a reserve memory ( 46 ) for inscription of the bits in the least significant memory cell ( 50 ) of the control register ( 44 ) is provided and that at the end of the last Interrupt cycle done, the bit stored in the reserve memory is intended to be written into the least significant memory cell of the control register. 7. Signal processor according to claim 6, characterized in that even when further interrupts the reserve memory ( 46 ) for writing in the least significant memory cell ( 50 ) of the control register ( 44 ) is provided bits provided. 8. Signal processor according to claim 7, characterized in that the number of memory cells of the reserve memory ( 46 ) is at least equal to the number of interrupt sources. 9. Signal processor according to claim 7 or 8, characterized in that the reserve memory ( 46 ) is provided when writing the bits to work according to the shift register principle and for reading out the last written bit at the end of an interrupt cycle. 10. Signal processor according to one of the preceding An sayings for use in a digital telephone.